llvm.org GIT mirror llvm / 5d5ef4a
Handle spilling around an instruction that has an early-clobber re-definition of the spilled register. This is quite common on ARM now that some stores have early-clobber defines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129714 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 9 years ago
1 changed file(s) with 15 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
133133 bool foldMemoryOperand(MachineBasicBlock::iterator MI,
134134 const SmallVectorImpl &Ops,
135135 MachineInstr *LoadMI = 0);
136 void insertReload(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
136 void insertReload(LiveInterval &NewLI, SlotIndex,
137 MachineBasicBlock::iterator MI);
137138 void insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
138 MachineBasicBlock::iterator MI);
139 SlotIndex, MachineBasicBlock::iterator MI);
139140
140141 void spillAroundUses(unsigned Reg);
141142 void spillAll();
779780
780781 /// insertReload - Insert a reload of NewLI.reg before MI.
781782 void InlineSpiller::insertReload(LiveInterval &NewLI,
783 SlotIndex Idx,
782784 MachineBasicBlock::iterator MI) {
783785 MachineBasicBlock &MBB = *MI->getParent();
784 SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
785786 TII.loadRegFromStackSlot(MBB, MI, NewLI.reg, StackSlot,
786787 MRI.getRegClass(NewLI.reg), &TRI);
787788 --MI; // Point to load instruction.
795796
796797 /// insertSpill - Insert a spill of NewLI.reg after MI.
797798 void InlineSpiller::insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
798 MachineBasicBlock::iterator MI) {
799 SlotIndex Idx, MachineBasicBlock::iterator MI) {
799800 MachineBasicBlock &MBB = *MI->getParent();
800
801 // Get the defined value. It could be an early clobber so keep the def index.
802 SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
803 VNInfo *VNI = OldLI.getVNInfoAt(Idx);
804 assert(VNI && VNI->def.getDefIndex() == Idx && "Inconsistent VNInfo");
805 Idx = VNI->def;
806
807801 TII.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, StackSlot,
808802 MRI.getRegClass(NewLI.reg), &TRI);
809803 --MI; // Point to store instruction.
853847 SmallVector Ops;
854848 tie(Reads, Writes) = MI->readsWritesVirtualRegister(Reg, &Ops);
855849
850 // Find the slot index where this instruction reads and writes OldLI.
851 // This is usually the def slot, except for tied early clobbers.
852 SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
853 if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getUseIndex()))
854 if (SlotIndex::isSameInstr(Idx, VNI->def))
855 Idx = VNI->def;
856
856857 // Check for a sibling copy.
857858 unsigned SibReg = isFullCopyOf(MI, Reg);
858859 if (SibReg && isSibling(SibReg)) {
866867 }
867868 } else {
868869 // This is a reload for a sib-reg copy. Drop spills downstream.
869 SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
870870 LiveInterval &SibLI = LIS.getInterval(SibReg);
871871 eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx));
872872 // The COPY will fold to a reload below.
883883 NewLI.markNotSpillable();
884884
885885 if (Reads)
886 insertReload(NewLI, MI);
886 insertReload(NewLI, Idx, MI);
887887
888888 // Rewrite instruction operands.
889889 bool hasLiveDef = false;
898898 hasLiveDef = true;
899899 }
900900 }
901 DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI);
901902
902903 // FIXME: Use a second vreg if instruction has no tied ops.
903904 if (Writes && hasLiveDef)
904 insertSpill(NewLI, OldLI, MI);
905 insertSpill(NewLI, OldLI, Idx, MI);
905906
906907 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
907908 }