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Delete trailing whitespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62307 91177308-0d34-0410-b5e6-96231b3b80d8 Mikhail Glushenkov 11 years ago
8 changed file(s) with 420 addition(s) and 420 deletion(s). Raw diff Collapse all Expand all
77 //===----------------------------------------------------------------------===//
88 //
99 // Defines a registry template for discovering pluggable modules.
10 //
10 //
1111 //===----------------------------------------------------------------------===//
1212
1313 #ifndef LLVM_SUPPORT_REGISTRY_H
2222 class SimpleRegistryEntry {
2323 const char *Name, *Desc;
2424 T *(*Ctor)();
25
25
2626 public:
2727 SimpleRegistryEntry(const char *N, const char *D, T *(*C)())
2828 : Name(N), Desc(D), Ctor(C)
2929 {}
30
30
3131 const char *getName() const { return Name; }
3232 const char *getDesc() const { return Desc; }
3333 T *instantiate() const { return Ctor(); }
3434 };
35
36
35
36
3737 /// Traits for registry entries. If using other than SimpleRegistryEntry, it
3838 /// is necessary to define an alternate traits class.
3939 template
4040 class RegistryTraits {
4141 RegistryTraits(); // Do not implement.
42
42
4343 public:
4444 typedef SimpleRegistryEntry entry;
45
45
4646 /// nameof/descof - Accessors for name and description of entries. These are
4747 // used to generate help for command-line options.
4848 static const char *nameof(const entry &Entry) { return Entry.getName(); }
4949 static const char *descof(const entry &Entry) { return Entry.getDesc(); }
5050 };
51
52
51
52
5353 /// A global registry used in conjunction with static constructors to make
5454 /// pluggable components (like targets or garbage collectors) "just work" when
5555 /// linked with an executable.
5858 public:
5959 typedef U traits;
6060 typedef typename U::entry entry;
61
61
6262 class node;
6363 class listener;
6464 class iterator;
65
65
6666 private:
6767 Registry(); // Do not implement.
68
68
6969 static void Announce(const entry &E) {
7070 for (listener *Cur = ListenerHead; Cur; Cur = Cur->Next)
7171 Cur->registered(E);
7272 }
73
73
7474 friend class node;
7575 static node *Head, *Tail;
76
76
7777 friend class listener;
7878 static listener *ListenerHead, *ListenerTail;
79
79
8080 public:
8181 class iterator;
82
83
82
83
8484 /// Node in linked list of entries.
85 ///
85 ///
8686 class node {
8787 friend class iterator;
88
88
8989 node *Next;
9090 const entry& Val;
91
91
9292 public:
9393 node(const entry& V) : Next(0), Val(V) {
9494 if (Tail)
9696 else
9797 Head = this;
9898 Tail = this;
99
99
100100 Announce(V);
101101 }
102102 };
103
104
103
104
105105 /// Iterators for registry entries.
106 ///
106 ///
107107 class iterator {
108108 const node *Cur;
109
109
110110 public:
111111 explicit iterator(const node *N) : Cur(N) {}
112
112
113113 bool operator==(const iterator &That) const { return Cur == That.Cur; }
114114 bool operator!=(const iterator &That) const { return Cur != That.Cur; }
115115 iterator &operator++() { Cur = Cur->Next; return *this; }
116116 const entry &operator*() const { return Cur->Val; }
117117 const entry *operator->() const { return &Cur->Val; }
118118 };
119
119
120120 static iterator begin() { return iterator(Head); }
121121 static iterator end() { return iterator(0); }
122
123
122
123
124124 /// Abstract base class for registry listeners, which are informed when new
125125 /// entries are added to the registry. Simply subclass and instantiate:
126 ///
126 ///
127127 /// class CollectorPrinter : public Registry::listener {
128128 /// protected:
129129 /// void registered(const Registry::entry &e) {
130130 /// cerr << "collector now available: " << e->getName() << "\n";
131131 /// }
132 ///
132 ///
133133 /// public:
134134 /// CollectorPrinter() { init(); } // Print those already registered.
135135 /// };
136 ///
136 ///
137137 /// CollectorPrinter Printer;
138 ///
138 ///
139139 class listener {
140140 listener *Prev, *Next;
141
141
142142 friend void Registry::Announce(const entry &E);
143
143
144144 protected:
145145 /// Called when an entry is added to the registry.
146 ///
146 ///
147147 virtual void registered(const entry &) = 0;
148
148
149149 /// Calls 'registered' for each pre-existing entry.
150 ///
150 ///
151151 void init() {
152152 for (iterator I = begin(), E = end(); I != E; ++I)
153153 registered(*I);
154154 }
155
155
156156 public:
157157 listener() : Prev(ListenerTail), Next(0) {
158158 if (Prev)
161161 ListenerHead = this;
162162 ListenerTail = this;
163163 }
164
164
165165 virtual ~listener() {
166166 if (Next)
167167 Next->Prev = Prev;
173173 ListenerHead = Next;
174174 }
175175 };
176
177
176
177
178178 /// A static registration template. Use like such:
179 ///
179 ///
180180 /// Registry::Add
181181 /// X("fancy-gc", "Newfangled garbage collector.");
182 ///
182 ///
183183 /// Use of this template requires that:
184 ///
184 ///
185185 /// 1. The registered subclass has a default constructor.
186 //
186 //
187187 /// 2. The registry entry type has a constructor compatible with this
188188 /// signature:
189 ///
189 ///
190190 /// entry(const char *Name, const char *ShortDesc, T *(*Ctor)());
191 ///
191 ///
192192 /// If you have more elaborate requirements, then copy and modify.
193 ///
193 ///
194194 template
195195 class Add {
196196 entry Entry;
197197 node Node;
198
198
199199 static T *CtorFn() { return new V(); }
200
200
201201 public:
202202 Add(const char *Name, const char *Desc)
203203 : Entry(Name, Desc, CtorFn), Node(Entry) {}
204204 };
205
206
205
206
207207 /// A command-line parser for a registry. Use like such:
208 ///
208 ///
209209 /// static cl::opt::entry, false,
210210 /// Registry::Parser>
211211 /// GCOpt("gc", cl::desc("Garbage collector to use."),
212212 /// cl::value_desc());
213 ///
213 ///
214214 /// To make use of the value:
215 ///
215 ///
216216 /// Collector *TheCollector = GCOpt->instantiate();
217 ///
217 ///
218218 class Parser : public cl::parser, public listener{
219219 typedef U traits;
220220 typedef typename U::entry entry;
221
221
222222 protected:
223223 void registered(const entry &E) {
224224 addLiteralOption(traits::nameof(E), &E, traits::descof(E));
225225 }
226
226
227227 public:
228228 void initialize(cl::Option &O) {
229229 listener::init();
230230 cl::parser::initialize(O);
231231 }
232232 };
233
233
234234 };
235
236
235
236
237237 template
238238 typename Registry::node *Registry::Head;
239
239
240240 template
241241 typename Registry::node *Registry::Tail;
242
242
243243 template
244244 typename Registry::listener *Registry::ListenerHead;
245
245
246246 template
247247 typename Registry::listener *Registry::ListenerTail;
248
248
249249 }
250250
251251 #endif
2121 namespace llvm {
2222 class Module;
2323 class TargetMachine;
24
24
2525 struct TargetMachineRegistryEntry {
2626 const char *Name;
2727 const char *ShortDesc;
2828 TargetMachine *(*CtorFn)(const Module &, const std::string &);
2929 unsigned (*ModuleMatchQualityFn)(const Module &M);
3030 unsigned (*JITMatchQualityFn)();
31
31
3232 public:
3333 TargetMachineRegistryEntry(const char *N, const char *SD,
3434 TargetMachine *(*CF)(const Module &, const std::string &),
3737 : Name(N), ShortDesc(SD), CtorFn(CF), ModuleMatchQualityFn(MMF),
3838 JITMatchQualityFn(JMF) {}
3939 };
40
40
4141 template<>
4242 class RegistryTraits {
4343 public:
4444 typedef TargetMachineRegistryEntry entry;
45
45
4646 static const char *nameof(const entry &Entry) { return Entry.Name; }
4747 static const char *descof(const entry &Entry) { return Entry.ShortDesc; }
4848 };
6666 /// themselves with the tool they are linked. Targets should define an
6767 /// instance of this and implement the static methods described in the
6868 /// TargetMachine comments.
69 /// The type 'TargetMachineImpl' should provide a constructor with two
69 /// The type 'TargetMachineImpl' should provide a constructor with two
7070 /// parameters:
7171 /// - const Module& M: the module that is being compiled:
72 /// - const std::string& FS: target-specific string describing target
72 /// - const std::string& FS: target-specific string describing target
7373 /// flavour.
74
74
7575 template
7676 struct RegisterTarget {
7777 RegisterTarget(const char *Name, const char *ShortDesc)
8484 private:
8585 TargetMachineRegistry::entry Entry;
8686 TargetMachineRegistry::node Node;
87
87
8888 static TargetMachine *Allocator(const Module &M, const std::string &FS) {
8989 return new TargetMachineImpl(M, FS);
9090 }
99 // This file implements printing the assembly code for an Ocaml frametable.
1010 //
1111 //===----------------------------------------------------------------------===//
12
12
1313 #include "llvm/CodeGen/GCs.h"
1414 #include "llvm/CodeGen/AsmPrinter.h"
1515 #include "llvm/CodeGen/GCMetadataPrinter.h"
2727 public:
2828 void beginAssembly(raw_ostream &OS, AsmPrinter &AP,
2929 const TargetAsmInfo &TAI);
30
30
3131 void finishAssembly(raw_ostream &OS, AsmPrinter &AP,
3232 const TargetAsmInfo &TAI);
3333 };
34
34
3535 }
3636
3737 static GCMetadataPrinterRegistry::Add
4242 static void EmitCamlGlobal(const Module &M, raw_ostream &OS, AsmPrinter &AP,
4343 const TargetAsmInfo &TAI, const char *Id) {
4444 const std::string &MId = M.getModuleIdentifier();
45
45
4646 std::string Mangled;
4747 Mangled += TAI.getGlobalPrefix();
4848 Mangled += "caml";
5050 Mangled.append(MId.begin(), std::find(MId.begin(), MId.end(), '.'));
5151 Mangled += "__";
5252 Mangled += Id;
53
53
5454 // Capitalize the first letter of the module name.
5555 Mangled[Letter] = toupper(Mangled[Letter]);
56
56
5757 if (const char *GlobalDirective = TAI.getGlobalDirective())
5858 OS << GlobalDirective << Mangled << "\n";
5959 OS << Mangled << ":\n";
6363 const TargetAsmInfo &TAI) {
6464 AP.SwitchToSection(TAI.getTextSection());
6565 EmitCamlGlobal(getModule(), OS, AP, TAI, "code_begin");
66
66
6767 AP.SwitchToSection(TAI.getDataSection());
6868 EmitCamlGlobal(getModule(), OS, AP, TAI, "data_begin");
6969 }
7070
7171 /// emitAssembly - Print the frametable. The ocaml frametable format is thus:
72 ///
72 ///
7373 /// extern "C" struct align(sizeof(intptr_t)) {
7474 /// uint16_t NumDescriptors;
7575 /// struct align(sizeof(intptr_t)) {
7979 /// uint16_t LiveOffsets[NumLiveOffsets];
8080 /// } Descriptors[NumDescriptors];
8181 /// } caml${module}__frametable;
82 ///
82 ///
8383 /// Note that this precludes programs from stack frames larger than 64K
8484 /// (FrameSize and LiveOffsets would overflow). FrameTablePrinter will abort if
8585 /// either condition is detected in a function which uses the GC.
86 ///
86 ///
8787 void OcamlGCMetadataPrinter::finishAssembly(raw_ostream &OS, AsmPrinter &AP,
8888 const TargetAsmInfo &TAI) {
8989 const char *AddressDirective;
9898
9999 AP.SwitchToSection(TAI.getTextSection());
100100 EmitCamlGlobal(getModule(), OS, AP, TAI, "code_end");
101
101
102102 AP.SwitchToSection(TAI.getDataSection());
103103 EmitCamlGlobal(getModule(), OS, AP, TAI, "data_end");
104
104
105105 OS << AddressDirective << 0; // FIXME: Why does ocaml emit this??
106106 AP.EOL();
107
107
108108 AP.SwitchToSection(TAI.getDataSection());
109109 EmitCamlGlobal(getModule(), OS, AP, TAI, "frametable");
110
110
111111 for (iterator I = begin(), IE = end(); I != IE; ++I) {
112112 GCFunctionInfo &FI = **I;
113
113
114114 uint64_t FrameSize = FI.getFrameSize();
115115 if (FrameSize >= 1<<16) {
116116 cerr << "Function '" << FI.getFunction().getNameStart()
119119 cerr << "(" << uintptr_t(&FI) << ")\n";
120120 abort(); // Very rude!
121121 }
122
122
123123 OS << "\t" << TAI.getCommentString() << " live roots for "
124124 << FI.getFunction().getNameStart() << "\n";
125
125
126126 for (GCFunctionInfo::iterator J = FI.begin(), JE = FI.end(); J != JE; ++J) {
127127 size_t LiveCount = FI.live_size(J);
128128 if (LiveCount >= 1<<16) {
131131 << "Live root count " << LiveCount << " >= 65536.\n";
132132 abort(); // Very rude!
133133 }
134
134
135135 OS << AddressDirective
136136 << TAI.getPrivateGlobalPrefix() << "label" << J->Num;
137137 AP.EOL("call return address");
138
138
139139 AP.EmitInt16(FrameSize);
140140 AP.EOL("stack frame size");
141
141
142142 AP.EmitInt16(LiveCount);
143143 AP.EOL("live root count");
144
144
145145 for (GCFunctionInfo::live_iterator K = FI.live_begin(J),
146146 KE = FI.live_end(J); K != KE; ++K) {
147147 assert(K->StackOffset < 1<<16 &&
148148 "GC root stack offset is outside of fixed stack frame and out "
149149 "of range for ocaml GC!");
150
150
151151 OS << "\t.word\t" << K->StackOffset;
152152 AP.EOL("stack offset");
153153 }
154
154
155155 AP.EmitAlignment(AddressAlignLog);
156156 }
157157 }
88 //
99 // This file implements lowering for the llvm.gc* intrinsics compatible with
1010 // Objective Caml 3.10.0, which uses a liveness-accurate static stack map.
11 //
11 //
1212 // The frametable emitter is in OcamlGCPrinter.cpp.
1313 //
1414 //===----------------------------------------------------------------------===//
15
15
1616 #include "llvm/CodeGen/GCs.h"
1717 #include "llvm/CodeGen/GCStrategy.h"
1818
147147 /// have aggregate-typed registers. The values at this point do not necessarily
148148 /// have legal types, so each value may require one or more registers of some
149149 /// legal type.
150 ///
150 ///
151151 struct VISIBILITY_HIDDEN RegsForValue {
152152 /// TLI - The TargetLowering object.
153153 ///
157157 /// may need be promoted or synthesized from one or more registers.
158158 ///
159159 SmallVector ValueVTs;
160
160
161161 /// RegVTs - The value types of the registers. This is the same size as
162162 /// ValueVTs and it records, for each value, what the type of the assigned
163163 /// register or registers are. (Individual values are never synthesized
168168 /// it is necessary to have a separate record of the types.
169169 ///
170170 SmallVector RegVTs;
171
171
172172 /// Regs - This list holds the registers assigned to the values.
173173 /// Each legal or promoted value requires one register, and each
174174 /// expanded value requires multiple registers.
175175 ///
176176 SmallVector Regs;
177
177
178178 RegsForValue() : TLI(0) {}
179
179
180180 RegsForValue(const TargetLowering &tli,
181 const SmallVector ®s,
181 const SmallVector ®s,
182182 MVT regvt, MVT valuevt)
183183 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
184184 RegsForValue(const TargetLowering &tli,
185 const SmallVector ®s,
185 const SmallVector ®s,
186186 const SmallVector ®vts,
187187 const SmallVector &valuevts)
188188 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
200200 Reg += NumRegs;
201201 }
202202 }
203
203
204204 /// append - Add the specified values to this one.
205205 void append(const RegsForValue &RHS) {
206206 TLI = RHS.TLI;
208208 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
209209 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
210210 }
211
212
211
212
213213 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
214 /// this value and returns the result as a ValueVTs value. This uses
214 /// this value and returns the result as a ValueVTs value. This uses
215215 /// Chain/Flag as the input and updates them for the output Chain/Flag.
216216 /// If the Flag pointer is NULL, no flag is used.
217217 SDValue getCopyFromRegs(SelectionDAG &DAG,
218218 SDValue &Chain, SDValue *Flag) const;
219219
220220 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
221 /// specified value into the registers specified by this object. This uses
221 /// specified value into the registers specified by this object. This uses
222222 /// Chain/Flag as the input and updates them for the output Chain/Flag.
223223 /// If the Flag pointer is NULL, no flag is used.
224224 void getCopyToRegs(SDValue Val, SelectionDAG &DAG,
225225 SDValue &Chain, SDValue *Flag) const;
226
226
227227 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
228 /// operand list. This adds the code marker and includes the number of
228 /// operand list. This adds the code marker and includes the number of
229229 /// values added into it.
230230 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
231231 std::vector &Ops) const;
233233 }
234234
235235 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
236 /// PHI nodes or outside of the basic block that defines it, or used by a
236 /// PHI nodes or outside of the basic block that defines it, or used by a
237237 /// switch or atomic instruction, which may expand to multiple basic blocks.
238238 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
239239 if (isa(I)) return true;
290290 if (ConstantInt *CUI = dyn_cast(AI->getArraySize())) {
291291 const Type *Ty = AI->getAllocatedType();
292292 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
293 unsigned Align =
293 unsigned Align =
294294 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
295295 AI->getAlignment());
296296
320320 PHINode *PN;
321321 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast(I)); ++I){
322322 if (PN->use_empty()) continue;
323
323
324324 unsigned PHIReg = ValueMap[PN];
325325 assert(PHIReg && "PHI node does not have an assigned virtual register!");
326326
666666 PtrVT));
667667 else
668668 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
669 IntermediateVT, Val,
669 IntermediateVT, Val,
670670 DAG.getConstant(i, PtrVT));
671671
672672 // Split the intermediate operands into legal parts.
776776 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
777777 #include "llvm/Instruction.def"
778778 }
779 }
779 }
780780
781781 void SelectionDAGLowering::visitAdd(User &I) {
782782 if (I.getType()->isFPOrFPVector())
795795 SDValue SelectionDAGLowering::getValue(const Value *V) {
796796 SDValue &N = NodeMap[V];
797797 if (N.getNode()) return N;
798
798
799799 if (Constant *C = const_cast(dyn_cast(V))) {
800800 MVT VT = TLI.getValueType(V->getType(), true);
801
801
802802 if (ConstantInt *CI = dyn_cast(C))
803803 return N = DAG.getConstant(*CI, VT);
804804
805805 if (GlobalValue *GV = dyn_cast(C))
806806 return N = DAG.getGlobalAddress(GV, VT);
807
807
808808 if (isa(C))
809809 return N = DAG.getConstant(0, TLI.getPointerTy());
810
810
811811 if (ConstantFP *CFP = dyn_cast(C))
812812 return N = DAG.getConstantFP(*CFP, VT);
813
813
814814 if (isa(C) && !isa(V->getType()) &&
815815 !V->getType()->isAggregateType())
816816 return N = DAG.getNode(ISD::UNDEF, VT);
821821 assert(N1.getNode() && "visit didn't populate the ValueMap!");
822822 return N1;
823823 }
824
824
825825 if (isa(C) || isa(C)) {
826826 SmallVector Constants;
827827 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
857857
858858 const VectorType *VecTy = cast(V->getType());
859859 unsigned NumElements = VecTy->getNumElements();
860
860
861861 // Now that we know the number and type of the elements, get that number of
862862 // elements into the Ops array based on what kind of constant it is.
863863 SmallVector Ops;
878878 Op = DAG.getConstant(0, EltVT);
879879 Ops.assign(NumElements, Op);
880880 }
881
881
882882 // Create a BUILD_VECTOR node.
883883 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
884884 }
885
885
886886 // If this is a static alloca, generate it as the frameindex instead of
887887 // computation.
888888 if (const AllocaInst *AI = dyn_cast(V)) {
891891 if (SI != FuncInfo.StaticAllocaMap.end())
892892 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
893893 }
894
894
895895 unsigned InReg = FuncInfo.ValueMap[V];
896896 assert(InReg && "Value not in map!");
897
897
898898 RegsForValue RFV(TLI, InReg, V->getType());
899899 SDValue Chain = DAG.getEntryNode();
900900 return RFV.getCopyFromRegs(DAG, Chain, NULL);
906906 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
907907 return;
908908 }
909
909
910910 SmallVector NewValues;
911911 NewValues.push_back(getControlRoot());
912 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
912 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
913913 SmallVector ValueVTs;
914914 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
915915 unsigned NumValues = ValueVTs.size();
932932 MVT PartVT = TLI.getRegisterType(VT);
933933 SmallVector Parts(NumParts);
934934 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
935
935
936936 const Function *F = I.getParent()->getParent();
937937 if (F->paramHasAttr(0, Attribute::SExt))
938938 ExtendKind = ISD::SIGN_EXTEND;
962962 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
963963 // No need to export constants.
964964 if (!isa(V) && !isa(V)) return;
965
965
966966 // Already exported?
967967 if (FuncInfo.isExportedInst(V)) return;
968968
978978 // Can export from current BB.
979979 if (VI->getParent() == FromBB)
980980 return true;
981
981
982982 // Is already exported, noop.
983983 return FuncInfo.isExportedInst(V);
984984 }
985
985
986986 // If this is an argument, we can export it if the BB is the entry block or
987987 // if it is already exported.
988988 if (isa(V)) {
992992 // Otherwise, can only export this if it is already exported.
993993 return FuncInfo.isExportedInst(V);
994994 }
995
995
996996 // Otherwise, constants can always be exported.
997997 return true;
998998 }
10331033 }
10341034 if (FiniteOnlyFPMath())
10351035 return FOC;
1036 else
1036 else
10371037 return FPC;
10381038 }
10391039
11011101 SwitchCases.push_back(CB);
11021102 }
11031103
1104 /// FindMergedConditions - If Cond is an expression like
1104 /// FindMergedConditions - If Cond is an expression like
11051105 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
11061106 MachineBasicBlock *TBB,
11071107 MachineBasicBlock *FBB,
11091109 unsigned Opc) {
11101110 // If this node is not part of the or/and tree, emit it as a branch.
11111111 Instruction *BOp = dyn_cast(Cond);
1112 if (!BOp || !(isa(BOp) || isa(BOp)) ||
1112 if (!BOp || !(isa(BOp) || isa(BOp)) ||
11131113 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
11141114 BOp->getParent() != CurBB->getBasicBlock() ||
11151115 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
11171117 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
11181118 return;
11191119 }
1120
1120
11211121 // Create TmpBB after CurBB.
11221122 MachineFunction::iterator BBI = CurBB;
11231123 MachineFunction &MF = DAG.getMachineFunction();
11241124 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
11251125 CurBB->getParent()->insert(++BBI, TmpBB);
1126
1126
11271127 if (Opc == Instruction::Or) {
11281128 // Codegen X | Y as:
11291129 // jmp_if_X TBB
11321132 // jmp_if_Y TBB
11331133 // jmp FBB
11341134 //
1135
1135
11361136 // Emit the LHS condition.
11371137 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1138
1138
11391139 // Emit the RHS condition into TmpBB.
11401140 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
11411141 } else {
11481148 // jmp FBB
11491149 //
11501150 // This requires creation of TmpBB after CurBB.
1151
1151
11521152 // Emit the LHS condition.
11531153 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1154
1154
11551155 // Emit the RHS condition into TmpBB.
11561156 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
11571157 }
11601160 /// If the set of cases should be emitted as a series of branches, return true.
11611161 /// If we should emit this as a bunch of and/or'd together conditions, return
11621162 /// false.
1163 bool
1163 bool
11641164 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector &Cases){
11651165 if (Cases.size() != 2) return true;
1166
1166
11671167 // If this is two comparisons of the same values or'd or and'd together, they
11681168 // will get folded into a single comparison, so don't emit two blocks.
11691169 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
11721172 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
11731173 return false;
11741174 }
1175
1175
11761176 return true;
11771177 }
11781178
11891189 if (I.isUnconditional()) {
11901190 // Update machine-CFG edges.
11911191 CurMBB->addSuccessor(Succ0MBB);
1192
1192
11931193 // If this is not a fall-through branch, emit the branch.
11941194 if (Succ0MBB != NextBlock)
11951195 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
12061206 // this as a sequence of branches instead of setcc's with and/or operations.
12071207 // For example, instead of something like:
12081208 // cmp A, B
1209 // C = seteq
1209 // C = seteq
12101210 // cmp D, E
1211 // F = setle
1211 // F = setle
12121212 // or C, F
12131213 // jnz foo
12141214 // Emit:
12181218 // jle foo
12191219 //
12201220 if (BinaryOperator *BOp = dyn_cast(CondVal)) {
1221 if (BOp->hasOneUse() &&
1221 if (BOp->hasOneUse() &&
12221222 (BOp->getOpcode() == Instruction::And ||
12231223 BOp->getOpcode() == Instruction::Or)) {
12241224 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
12261226 // exported from this block, export them now. This block should always
12271227 // be the first entry.
12281228 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1229
1229
12301230 // Allow some cases to be rejected.
12311231 if (ShouldEmitAsBranches(SwitchCases)) {
12321232 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
12331233 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
12341234 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
12351235 }
1236
1236
12371237 // Emit the branch for this block.
12381238 visitSwitchCase(SwitchCases[0]);
12391239 SwitchCases.erase(SwitchCases.begin());
12401240 return;
12411241 }
1242
1242
12431243 // Okay, we decided not to do this, remove any inserted MBB's and clear
12441244 // SwitchCases.
12451245 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
12461246 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1247
1247
12481248 SwitchCases.clear();
12491249 }
12501250 }
1251
1251
12521252 // Create a CaseBlock record representing this branch.
12531253 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
12541254 NULL, Succ0MBB, Succ1MBB, CurMBB);
17841784 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
17851785
17861786 // We know that we branch to the LHS if the Value being switched on is
1787 // less than the Pivot value, C. We use this to optimize our binary
1787 // less than the Pivot value, C. We use this to optimize our binary
17881788 // tree a bit, by recognizing that if SV is greater than or equal to the
1789 // LHS's Case Value, and that Case Value is exactly one less than the
1789 // LHS's Case Value, and that Case Value is exactly one less than the
17901790 // Pivot's Value, then we can branch directly to the LHS's Target,
17911791 // rather than creating a leaf node for it.
17921792 if ((LHSR.second - LHSR.first) == 1 &&
18151815 }
18161816
18171817 // Create a CaseBlock record representing a conditional branch to
1818 // the LHS node if the value being switched on SV is less than C.
1818 // the LHS node if the value being switched on SV is less than C.
18191819 // Otherwise, branch to LHS.
18201820 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
18211821
20932093 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
20942094 SDValue Op1 = getValue(I.getOperand(0));
20952095 SDValue Op2 = getValue(I.getOperand(1));
2096
2096
20972097 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
20982098 }
20992099
21062106 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
21072107 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
21082108 }
2109
2109
21102110 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
21112111 }
21122112
21562156 SDValue Op2 = getValue(I.getOperand(1));
21572157 ISD::CondCode Condition = getFCmpCondCode(predicate);
21582158 MVT DestVT = TLI.getValueType(I.getType());
2159
2159
21602160 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
21612161 }
21622162
22122212 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
22132213 }
22142214
2215 void SelectionDAGLowering::visitFPExt(User &I){
2215 void SelectionDAGLowering::visitFPExt(User &I){
22162216 // FPTrunc is never a no-op cast, no need to check
22172217 SDValue N = getValue(I.getOperand(0));
22182218 MVT DestVT = TLI.getValueType(I.getType());
22192219 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
22202220 }
22212221
2222 void SelectionDAGLowering::visitFPToUI(User &I) {
2222 void SelectionDAGLowering::visitFPToUI(User &I) {
22232223 // FPToUI is never a no-op cast, no need to check
22242224 SDValue N = getValue(I.getOperand(0));
22252225 MVT DestVT = TLI.getValueType(I.getType());
22332233 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
22342234 }
22352235
2236 void SelectionDAGLowering::visitUIToFP(User &I) {
2236 void SelectionDAGLowering::visitUIToFP(User &I) {
22372237 // UIToFP is never a no-op cast, no need to check
22382238 SDValue N = getValue(I.getOperand(0));
22392239 MVT DestVT = TLI.getValueType(I.getType());
22402240 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
22412241 }
22422242
2243 void SelectionDAGLowering::visitSIToFP(User &I){
2243 void SelectionDAGLowering::visitSIToFP(User &I){
22442244 // SIToFP is never a no-op cast, no need to check
22452245 SDValue N = getValue(I.getOperand(0));
22462246 MVT DestVT = TLI.getValueType(I.getType());
22562256 SDValue Result;
22572257 if (DestVT.bitsLT(SrcVT))
22582258 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2259 else
2259 else
22602260 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
22612261 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
22622262 setValue(&I, Result);
22702270 MVT DestVT = TLI.getValueType(I.getType());
22712271 if (DestVT.bitsLT(SrcVT))
22722272 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2273 else
2273 else
22742274 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
22752275 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
22762276 }
22772277
2278 void SelectionDAGLowering::visitBitCast(User &I) {
2278 void SelectionDAGLowering::visitBitCast(User &I) {
22792279 SDValue N = getValue(I.getOperand(0));
22802280 MVT DestVT = TLI.getValueType(I.getType());
22812281
2282 // BitCast assures us that source and destination are the same size so this
2282 // BitCast assures us that source and destination are the same size so this
22832283 // is either a BIT_CONVERT or a no-op.
22842284 if (DestVT != N.getValueType())
22852285 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
24422442 } else {
24432443 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
24442444 if (MaxRange[Input] - StartIdx[Input] < MaskNumElts &&
2445 StartIdx[Input] + MaskNumElts < SrcNumElts)
2445 StartIdx[Input] + MaskNumElts < SrcNumElts)
24462446 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
24472447 }
24482448 }
24762476 else {
24772477 Idx = Idx - SrcNumElts - StartIdx[1] + MaskNumElts;
24782478 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2479 }
2479 }
24802480 }
24812481 }
24822482 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
26032603 // If this is a constant subscript, handle it quickly.
26042604 if (ConstantInt *CI = dyn_cast(Idx)) {
26052605 if (CI->getZExtValue() == 0) continue;
2606 uint64_t Offs =
2606 uint64_t Offs =
26072607 TD->getTypePaddedSize(Ty)*cast(CI)->getSExtValue();
26082608 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
26092609 DAG.getIntPtrConstant(Offs));
26102610 continue;
26112611 }
2612
2612
26132613 // N = N + Idx * ElementSize;
26142614 uint64_t ElementSize = TD->getTypePaddedSize(Ty);
26152615 SDValue IdxN = getValue(Idx);
27312731 Values[i] = L;
27322732 Chains[i] = L.getValue(1);
27332733 }
2734
2734
27352735 if (!ConstantMemory) {
27362736 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
27372737 &Chains[0], NumValues);
27812781
27822782 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
27832783 /// node.
2784 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2784 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
27852785 unsigned Intrinsic) {
27862786 bool HasChain = !I.doesNotAccessMemory();
27872787 bool OnlyLoad = HasChain && I.onlyReadsMemory();
27922792 if (OnlyLoad) {
27932793 // We don't need to serialize loads against other loads.
27942794 Ops.push_back(DAG.getRoot());
2795 } else {
2795 } else {
27962796 Ops.push_back(getRoot());
27972797 }
27982798 }
28012801 TargetLowering::IntrinsicInfo Info;
28022802 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
28032803
2804 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2804 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
28052805 if (!IsTgtIntrinsic)
28062806 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
28072807
28192819 if (VT.isVector()) {
28202820 const VectorType *DestTy = cast(I.getType());
28212821 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2822
2822
28232823 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
28242824 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
28252825 }
2826
2826
28272827 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
28282828 VTs.push_back(VT);
28292829 }
28632863 if (const VectorType *PTy = dyn_cast(I.getType())) {
28642864 MVT VT = TLI.getValueType(PTy);
28652865 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2866 }
2866 }
28672867 setValue(&I, Result);
28682868 }
28692869 }
29702970 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
29712971 }
29722972
2973 /// Inlined utility function to implement binary input atomic intrinsics for
2973 /// Inlined utility function to implement binary input atomic intrinsics for
29742974 /// visitIntrinsicCall: I is a call instruction
29752975 /// Op is the associated NodeType for I
29762976 const char *
29772977 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
2978 SDValue Root = getRoot();
2978 SDValue Root = getRoot();
29792979 SDValue L =
29802980 DAG.getAtomic(Op, getValue(I.getOperand(2)).getValueType().getSimpleVT(),
29812981 Root,
2982 getValue(I.getOperand(1)),
2982 getValue(I.getOperand(1)),
29832983 getValue(I.getOperand(2)),
29842984 I.getOperand(1));
29852985 setValue(&I, L);
31523152 // LogofMantissa =
31533153 // -1.1609546f +
31543154 // (1.4034025f - 0.23903021f * x) * x;
3155 //
3155 //
31563156 // error 0.0034276066, which is better than 8 bits
31573157 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
31583158 getF32Constant(DAG, 0xbe74c456));
32493249 // Get the significand and build it into a floating-point number with
32503250 // exponent of 1.
32513251 SDValue X = GetSignificand(DAG, Op1);
3252
3252
32533253 // Different possible minimax approximations of significand in
32543254 // floating-point for various degrees of accuracy over [1,2].
32553255 if (LimitFloatPrecision <= 6) {
32753275 // (4.07009056f +
32763276 // (-2.12067489f +
32773277 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3278 //
3278 //
32793279 // error 0.0000876136000, which is better than 13 bits
32803280 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
32813281 getF32Constant(DAG, 0xbda7262e));
33593359
33603360 if (LimitFloatPrecision <= 6) {
33613361 // For floating-point precision of 6:
3362 //
3362 //
33633363 // Log10ofMantissa =
33643364 // -0.50419619f +
33653365 // (0.60948995f - 0.10380950f * x) * x;
34573457
34583458 if (LimitFloatPrecision <= 6) {
34593459 // For floating-point precision of 6:
3460 //
3460 //
34613461 // TwoToFractionalPartOfX =
34623462 // 0.997535578f +
34633463 // (0.735607626f + 0.252464424f * x) * x;
34683468 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
34693469 getF32Constant(DAG, 0x3f3c50c8));
34703470 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3471 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3471 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
34723472 getF32Constant(DAG, 0x3f7f5e7e));
34733473 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5);
34743474 SDValue TwoToFractionalPartOfX =
34893489 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
34903490 getF32Constant(DAG, 0x3e65b8f3));
34913491 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3492 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3492 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
34933493 getF32Constant(DAG, 0x3f324b07));
34943494 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
34953495 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
35153515 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
35163516 getF32Constant(DAG, 0x3ab24b87));
35173517 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3518 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3518 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
35193519 getF32Constant(DAG, 0x3c1d8c17));
35203520 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
35213521 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
35863586
35873587 if (LimitFloatPrecision <= 6) {
35883588 // For floating-point precision of 6:
3589 //
3589 //
35903590 // twoToFractionalPartOfX =
35913591 // 0.997535578f +
35923592 // (0.735607626f + 0.252464424f * x) * x;
3593 //
3593 //
35943594 // error 0.0144103317, which is 6 bits
35953595 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
35963596 getF32Constant(DAG, 0x3e814304));
35973597 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
35983598 getF32Constant(DAG, 0x3f3c50c8));
35993599 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3600 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3600 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
36013601 getF32Constant(DAG, 0x3f7f5e7e));
36023602 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5);
36033603 SDValue TwoToFractionalPartOfX =
36183618 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
36193619 getF32Constant(DAG, 0x3e65b8f3));
36203620 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3621 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3621 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
36223622 getF32Constant(DAG, 0x3f324b07));
36233623 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
36243624 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
36443644 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
36453645 getF32Constant(DAG, 0x3ab24b87));
36463646 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3647 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3647 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
36483648 getF32Constant(DAG, 0x3c1d8c17));
36493649 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
36503650 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
37563756 DwarfWriter *DW = DAG.getDwarfWriter();
37573757 DbgRegionStartInst &RSI = cast(I);
37583758 if (DW && RSI.getContext() && DW->ValidDebugInfo(RSI.getContext())) {
3759 unsigned LabelID =
3759 unsigned LabelID =
37603760 DW->RecordRegionStart(cast(RSI.getContext()));
37613761 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
37623762 }
37673767 DwarfWriter *DW = DAG.getDwarfWriter();
37683768 DbgRegionEndInst &REI = cast(I);
37693769 if (DW && REI.getContext() && DW->ValidDebugInfo(REI.getContext())) {
3770 unsigned LabelID =
3770 unsigned LabelID =
37713771 DW->RecordRegionEnd(cast(REI.getContext()));
37723772 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
37733773 }
37893789 // Record the source line but does not create a label for the normal
37903790 // function start. It will be emitted at asm emission time. However,
37913791 // create a label if this is a beginning of inlined function.
3792 unsigned LabelID =
3792 unsigned LabelID =
37933793 DW->RecordSourceLine(Subprogram.getLineNumber(), 0, SrcFile);
37943794 if (DW->getRecordSourceLineCount() != 1)
37953795 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
38063806 getValue(DI.getAddress()), getValue(Variable)));
38073807 return 0;
38083808 }
3809
3809
38103810 case Intrinsic::eh_exception: {
38113811 if (!CurMBB->isLandingPad()) {
38123812 // FIXME: Mark exception register as live in. Hack for PR1508.
38283828 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
38293829 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
38303830 MVT::i32 : MVT::i64);
3831
3831
38323832 if (MMI) {
38333833 if (CurMBB->isLandingPad())
38343834 AddCatchInfo(I, MMI, CurMBB);
38523852 } else {
38533853 setValue(&I, DAG.getConstant(0, VT));
38543854 }
3855
3855
38563856 return 0;
38573857 }
38583858
41074107 if (GFI) {
41084108 Value *Alloca = I.getOperand(1);
41094109 Constant *TypeMap = cast(I.getOperand(2));
4110
4110
41114111 FrameIndexSDNode *FI = cast(getValue(Alloca).getNode());
41124112 GFI->addStackRoot(FI->getIndex(), TypeMap);
41134113 }
41504150 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
41514151 return 0;
41524152 }
4153
4153
41544154 case Intrinsic::memory_barrier: {
41554155 SDValue Ops[6];
41564156 Ops[0] = getRoot();
41614161 return 0;
41624162 }
41634163 case Intrinsic::atomic_cmp_swap: {
4164 SDValue Root = getRoot();
4164 SDValue Root = getRoot();
41654165 SDValue L =
41664166 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP,
41674167 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
41684168 Root,
4169 getValue(I.getOperand(1)),
4169 getValue(I.getOperand(1)),
41704170 getValue(I.getOperand(2)),
41714171 getValue(I.getOperand(3)),
41724172 I.getOperand(1));
43014301 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
43024302 return;
43034303 }
4304 } else if (NameStr[0] == 's' &&
4304 } else if (NameStr[0] == 's' &&
43054305 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
43064306 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
43074307 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
43414341
43424342
43434343 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4344 /// this value and returns the result as a ValueVT value. This uses
4344 /// this value and returns the result as a ValueVT value. This uses
43454345 /// Chain/Flag as the input and updates them for the output Chain/Flag.
43464346 /// If the Flag pointer is NULL, no flag is used.
4347 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
4347 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
43484348 SDValue &Chain,
43494349 SDValue *Flag) const {
43504350 // Assemble the legal parts into the final values.
43664366 *Flag = P.getValue(2);
43674367 }
43684368 Chain = P.getValue(1);
4369
4369
43704370 // If the source register was virtual and if we know something about it,
43714371 // add an assert node.
43724372 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
43754375 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
43764376 if (FLI.LiveOutRegInfo.size() > SlotNo) {
43774377 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4378
4378
43794379 unsigned RegSize = RegisterVT.getSizeInBits();
43804380 unsigned NumSignBits = LOI.NumSignBits;
43814381 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4382
4382
43834383 // FIXME: We capture more information than the dag can represent. For
43844384 // now, just use the tightest assertzext/assertsext possible.
43854385 bool isSExt = true;
44004400 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
44014401 else if (NumZeroBits >= RegSize-33)
44024402 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4403
4403
44044404 if (FromVT != MVT::Other) {
44054405 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
44064406 RegisterVT, P, DAG.getValueType(FromVT));
44084408 }
44094409 }
44104410 }
4411
4411
44124412 Parts[i] = P;
44134413 }
4414
4414
44154415 Values[Value] = getCopyFromParts(DAG, Parts.begin(), NumRegs, RegisterVT,
44164416 ValueVT);
44174417 Part += NumRegs;
44244424 }
44254425
44264426 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4427 /// specified value into the registers specified by this object. This uses
4427 /// specified value into the registers specified by this object. This uses
44284428 /// Chain/Flag as the input and updates them for the output Chain/Flag.
44294429 /// If the Flag pointer is NULL, no flag is used.
44304430 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
44544454 }
44554455 Chains[i] = Part.getValue(0);
44564456 }
4457
4457
44584458 if (NumRegs == 1 || Flag)
4459 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4459 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
44604460 // flagged to it. That is the CopyToReg nodes and the user are considered
44614461 // a single scheduling unit. If we create a TokenFactor and return it as
44624462 // chain, then the TokenFactor is both a predecessor (operand) of the
44724472 }
44734473
44744474 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4475 /// operand list. This adds the code marker and includes the number of
4475 /// operand list. This adds the code marker and includes the number of
44764476 /// values added into it.
44774477 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
44784478 std::vector &Ops) const {
44884488 }
44894489 }
44904490
4491 /// isAllocatableRegister - If the specified register is safe to allocate,
4491 /// isAllocatableRegister - If the specified register is safe to allocate,
44924492 /// i.e. it isn't a stack pointer or some other special register, return the
44934493 /// register class for the register. Otherwise, return null.
44944494 static const TargetRegisterClass *
45024502 MVT ThisVT = MVT::Other;
45034503
45044504 const TargetRegisterClass *RC = *RCI;
4505 // If none of the the value types for this register class are valid, we
4505 // If none of the the value types for this register class are valid, we
45064506 // can't use it. For example, 64-bit reg classes on 32-bit targets.
45074507 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
45084508 I != E; ++I) {
45164516 }
45174517 }
45184518 }
4519
4519
45204520 if (ThisVT == MVT::Other) continue;
4521
4521
45224522 // NOTE: This isn't ideal. In particular, this might allocate the
45234523 // frame pointer in functions that need it (due to them not being taken
45244524 // out of allocation, because a variable sized allocation hasn't been seen
45344534 }
45354535 }
45364536 return FoundRC;
4537 }
4537 }
45384538
45394539
45404540 namespace llvm {
45414541 /// AsmOperandInfo - This contains information for each constraint that we are
45424542 /// lowering.
4543 struct VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4543 struct VISIBILITY_HIDDEN SDISelAsmOperandInfo :
45444544 public TargetLowering::AsmOperandInfo {
45454545 /// CallOperand - If this is the result output operand or a clobber
45464546 /// this is null, otherwise it is the incoming operand to the CallInst.
45504550 /// AssignedRegs - If this is a register or register class operand, this
45514551 /// contains the set of register corresponding to the operand.
45524552 RegsForValue AssignedRegs;
4553
4553
45544554 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
45554555 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
45564556 }
4557
4557
45584558 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
45594559 /// busy in OutputRegs/InputRegs.
45604560 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4561 std::set &OutputRegs,
4561 std::set &OutputRegs,
45624562 std::set &InputRegs,
45634563 const TargetRegisterInfo &TRI) const {
45644564 if (isOutReg) {
45704570 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
45714571 }
45724572 }
4573
4573
45744574 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
45754575 /// corresponds to. If there is no Value* for this operand, it returns
45764576 /// MVT::Other.
45774577 MVT getCallOperandValMVT(const TargetLowering &TLI,
45784578 const TargetData *TD) const {
45794579 if (CallOperandVal == 0) return MVT::Other;
4580
4580
45814581 if (isa(CallOperandVal))
45824582 return TLI.getPointerTy();
4583
4583
45844584 const llvm::Type *OpTy = CallOperandVal->getType();
4585
4585
45864586 // If this is an indirect operand, the operand is a pointer to the
45874587 // accessed type.
45884588 if (isIndirect)
45894589 OpTy = cast(OpTy)->getElementType();
4590
4590
45914591 // If OpTy is not a single value, it may be a struct/union that we
45924592 // can tile with integers.
45934593 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
46044604 break;
46054605 }
46064606 }
4607
4607
46084608 return TLI.getValueType(OpTy, true);
46094609 }
4610
4610
46114611 private:
46124612 /// MarkRegAndAliases - Mark the specified register and all aliases in the
46134613 /// specified set.
4614 static void MarkRegAndAliases(unsigned Reg, std::set &Regs,
4614 static void MarkRegAndAliases(unsigned Reg, std::set &Regs,
46154615 const TargetRegisterInfo &TRI) {
46164616 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
46174617 Regs.insert(Reg);
46344634 ///
46354635 void SelectionDAGLowering::
46364636 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4637 std::set &OutputRegs,
4637 std::set &OutputRegs,
46384638 std::set &InputRegs) {
46394639 // Compute whether this value requires an input register, an output register,
46404640 // or both.
46434643 switch (OpInfo.Type) {
46444644 case InlineAsm::isOutput:
46454645 isOutReg = true;
4646
4647 // If there is an input constraint that matches this, we need to reserve
4646
4647 // If there is an input constraint that matches this, we need to reserve
46484648 // the input register so no other inputs allocate to it.
46494649 isInReg = OpInfo.hasMatchingInput();
46504650 break;
46574657 isInReg = true;
46584658 break;
46594659 }
4660
4661
4660
4661
46624662 MachineFunction &MF = DAG.getMachineFunction();
46634663 SmallVector Regs;
4664
4664
46654665 // If this is a constraint for a single physreg, or a constraint for a
46664666 // register class, find it.
4667 std::pair PhysReg =
4667 std::pair PhysReg =
46684668 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
46694669 OpInfo.ConstraintVT);
46704670
46944694 OpInfo.ConstraintVT = RegVT;
46954695 }
46964696 }
4697
4697
46984698 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
46994699 }
4700
4700
47014701 MVT RegVT;
47024702 MVT ValueVT = OpInfo.ConstraintVT;
47034703
47064706 if (PhysReg.first) {
47074707 if (OpInfo.ConstraintVT == MVT::Other)
47084708 ValueVT = *PhysReg.second->vt_begin();
4709
4709
47104710 // Get the actual register value type. This is important, because the user
47114711 // may have asked for (e.g.) the AX register in i32 type. We need to
47124712 // remember that AX is actually i16 to get the right extension.
47134713 RegVT = *PhysReg.second->vt_begin();
4714
4714
47154715 // This is a explicit reference to a physical register.
47164716 Regs.push_back(PhysReg.first);
47174717
47194719 if (NumRegs != 1) {
47204720 TargetRegisterClass::iterator I = PhysReg.second->begin();
47214721 for (; *I != PhysReg.first; ++I)
4722 assert(I != PhysReg.second->end() && "Didn't find reg!");
4723
4722 assert(I != PhysReg.second->end() && "Didn't find reg!");
4723
47244724 // Already added the first reg.
47254725 --NumRegs; ++I;
47264726 for (; NumRegs; --NumRegs, ++I) {
47334733 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
47344734 return;
47354735 }
4736
4736
47374737 // Otherwise, if this was a reference to an LLVM register class, create vregs
47384738 // for this reference.
47394739 std::vector RegClassRegs;
47404740 const TargetRegisterClass *RC = PhysReg.second;
47414741 if (RC) {
4742 // If this is a tied register, our regalloc doesn't know how to maintain
4742 // If this is a tied register, our regalloc doesn't know how to maintain
47434743 // the constraint, so we have to pick a register to pin the input/output to.
47444744 // If it isn't a matched constraint, go ahead and create vreg and let the
47454745 // regalloc do its thing.
47524752 MachineRegisterInfo &RegInfo = MF.getRegInfo();
47534753 for (; NumRegs; --NumRegs)
47544754 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4755
4755
47564756 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
47574757 return;
47584758 }
4759
4759
47604760 // Otherwise, we can't allocate it. Let the code below figure out how to
47614761 // maintain these constraints.
47624762 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4763
4763
47644764 } else {
47654765 // This is a reference to a register class that doesn't directly correspond
47664766 // to an LLVM register class. Allocate NumRegs consecutive, available,
47684768 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
47694769 OpInfo.ConstraintVT);
47704770 }
4771
4771
47724772 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
47734773 unsigned NumAllocated = 0;
47744774 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
47804780 NumAllocated = 0;
47814781 continue;
47824782 }
4783
4783
47844784 // Check to see if this register is allocatable (i.e. don't give out the
47854785 // stack pointer).
47864786 if (RC == 0) {
47914791 continue;
47924792 }
47934793 }
4794
4794
47954795 // Okay, this register is good, we can use it.
47964796 ++NumAllocated;
47974797
48024802 // Mark all of the allocated registers used.
48034803 for (unsigned i = RegStart; i != RegEnd; ++i)
48044804 Regs.push_back(RegClassRegs[i]);
4805
4806 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4805
4806 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
48074807 OpInfo.ConstraintVT);
48084808 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
48094809 return;
48104810 }
48114811 }
4812
4812
48134813 // Otherwise, we couldn't allocate enough registers for this.
48144814 }
48154815
48374837
48384838 /// ConstraintOperands - Information about all of the constraints.
48394839 std::vector ConstraintOperands;
4840
4840
48414841 SDValue Chain = getRoot();
48424842 SDValue Flag;
4843
4843
48444844 std::set OutputRegs, InputRegs;
48454845
48464846 // Do a prepass over the constraints, canonicalizing them, and building up the
48494849 ConstraintInfos = IA->ParseConstraints();
48504850
48514851 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
4852
4852
48534853 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
48544854 unsigned ResNo = 0; // ResNo - The result number of the next output.
48554855 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
48564856 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
48574857 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4858
4858
48594859 MVT OpVT = MVT::Other;
48604860
48614861 // Compute the value type for each operand.
48664866 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
48674867 break;
48684868 }
4869
4869
48704870 // The return value of the call is this value. As such, there is no
48714871 // corresponding argument.
48724872 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
48944894 } else {
48954895 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
48964896 }
4897
4897
48984898 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
48994899 }
4900
4900
49014901 OpInfo.ConstraintVT = OpVT;
49024902 }
4903
4903
49044904 // Second pass over the constraints: compute which constraint option to use
49054905 // and assign registers to constraints that want a specific physreg.
49064906 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
49074907 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4908
4908
49094909 // If this is an output operand with a matching input operand, look up the
49104910 // matching input. If their types mismatch, e.g. one is an integer, the
49114911 // other is floating point, or their sizes are different, flag it as an
49244924 Input.ConstraintVT = OpInfo.ConstraintVT;
49254925 }
49264926 }
4927
4927
49284928 // Compute the constraint code and ConstraintType to use.
49294929 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
49304930
49344934 !OpInfo.isIndirect) {
49354935 assert(OpInfo.Type == InlineAsm::isInput &&
49364936 "Can only indirectify direct input operands!");
4937
4937
49384938 // Memory operands really want the address of the value. If we don't have
49394939 // an indirect input, put it in the constpool if we can, otherwise spill
49404940 // it to a stack slot.
4941
4941
49424942 // If the operand is a float, integer, or vector constant, spill to a
49434943 // constant pool entry to get its address.
49444944 Value *OpVal = OpInfo.CallOperandVal;
49584958 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
49594959 OpInfo.CallOperand = StackSlot;
49604960 }
4961
4961
49624962 // There is no longer a Value* corresponding to this operand.
49634963 OpInfo.CallOperandVal = 0;
49644964 // It is now an indirect operand.
49654965 OpInfo.isIndirect = true;
49664966 }
4967
4967
49684968 // If this constraint is for a specific register, allocate it before
49694969 // anything else.
49704970 if (OpInfo.ConstraintType == TargetLowering::C_Register)
49714971 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
49724972 }
49734973 ConstraintInfos.clear();
4974
4975
4974
4975
49764976 // Second pass - Loop over all of the operands, assigning virtual or physregs
49774977 // to register class operands.
49784978 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
49794979 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4980
4980
49814981 // C_Register operands have already been allocated, Other/Memory don't need
49824982 // to be.
49834983 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
49844984 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
4985 }
4986
4985 }
4986
49874987 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
49884988 std::vector AsmNodeOperands;
49894989 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
49904990 AsmNodeOperands.push_back(
49914991 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4992
4993
4992
4993
49944994 // Loop over all of the inputs, copying the operand values into the
49954995 // appropriate registers and processing the output regs.
49964996 RegsForValue RetValRegs;
4997
4997
49984998 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
49994999 std::vector > IndirectStoresToEmit;
5000
5000
50015001 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
50025002 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
50035003
50375037 // Concatenate this output onto the outputs list.
50385038 RetValRegs.append(OpInfo.AssignedRegs);
50395039 }
5040
5040
50415041 // Add information to the INLINEASM node to know that this register is
50425042 // set.
50435043 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
50485048 }
50495049 case InlineAsm::isInput: {
50505050 SDValue InOperandVal = OpInfo.CallOperand;
5051
5051
50525052 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
50535053 // If this is required to match an output register we have already set,
50545054 // just use its register.
50555055 unsigned OperandNo = OpInfo.getMatchedOperand();
5056
5056
50575057 // Scan until we find the definition we already emitted of this operand.
50585058 // When we find it, create a RegsForValue operand.
50595059 unsigned CurOp = 2; // The first operand.
50605060 for (; OperandNo; --OperandNo) {
50615061 // Advance to the next operand.
5062 unsigned NumOps =
5062 unsigned NumOps =
50635063 cast(AsmNodeOperands[CurOp])->getZExtValue();
50645064 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
50655065 (NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
50685068 CurOp += (NumOps>>3)+1;
50695069 }
50705070
5071 unsigned NumOps =
5071 unsigned NumOps =
50725072 cast(AsmNodeOperands[CurOp])->getZExtValue();
5073 if ((NumOps & 7) == 2 /*REGDEF*/
5073 if ((NumOps & 7) == 2 /*REGDEF*/
50745074 || (NumOps & 7) == 6 /* EARLYCLOBBER REGDEF */) {
50755075 // Add NumOps>>3 registers to MatchedRegs.
50765076 RegsForValue MatchedRegs;
50825082 cast(AsmNodeOperands[++CurOp])->getReg();
50835083 MatchedRegs.Regs.push_back(Reg);
50845084 }
5085
5086 // Use the produced MatchedRegs object to
5085
5086 // Use the produced MatchedRegs object to
50875087 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
50885088 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
50895089 break;
50905090 } else {
50915091 assert(((NumOps & 7) == 4) && "Unknown matching constraint!");
5092 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
5092 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
50935093 // Add information to the INLINEASM node to know about this input.
50945094 AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps,
50955095 TLI.getPointerTy()));
50975097 break;
50985098 }
50995099 }
5100
5100
51015101 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5102 assert(!OpInfo.isIndirect &&
5102 assert(!OpInfo.isIndirect &&
51035103 "Don't know how to handle indirect other inputs yet!");
5104
5104
51055105 std::vector Ops;
51065106 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
51075107 hasMemory, Ops, DAG);
51105110 << OpInfo.ConstraintCode << "'!\n";
51115111 exit(1);
51125112 }
5113
5113
51145114 // Add information to the INLINEASM node to know about this input.
51155115 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5116 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5116 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
51175117 TLI.getPointerTy()));
51185118 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
51195119 break;
51215121 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
51225122 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
51235123 "Memory operands expect pointer values");
5124
5124
51255125 // Add information to the INLINEASM node to know about this input.
51265126 unsigned ResOpType = 4/*MEM*/ | (1<<3);
51275127 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
51295129 AsmNodeOperands.push_back(InOperandVal);
51305130 break;
51315131 }
5132
5132
51335133 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
51345134 OpInfo.ConstraintType == TargetLowering::C_Register) &&
51355135 "Unknown constraint type!");
5136 assert(!OpInfo.isIndirect &&
5136 assert(!OpInfo.isIndirect &&
51375137 "Don't know how to handle indirect register inputs yet!");
51385138
51395139 // Copy the input into the appropriate registers.
51445144 }
51455145
51465146 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
5147
5147
51485148 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/,
51495149 DAG, AsmNodeOperands);
51505150 break;
51595159 }
51605160 }
51615161 }
5162
5162
51635163 // Finish up input operands.
51645164 AsmNodeOperands[0] = Chain;
51655165 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5166
5167 Chain = DAG.getNode(ISD::INLINEASM,
5166
5167 Chain = DAG.getNode(ISD::INLINEASM,
51685168 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
51695169 &AsmNodeOperands[0], AsmNodeOperands.size());
51705170 Flag = Chain.getValue(1);
51735173 // and set it as the value of the call.
51745174 if (!RetValRegs.Regs.empty()) {
51755175 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
5176
5176
51775177 // FIXME: Why don't we do this for inline asms with MRVs?
51785178 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
51795179 MVT ResultType = TLI.getValueType(CS.getType());
5180
5180
51815181 // If any of the results of the inline asm is a vector, it may have the
51825182 // wrong width/num elts. This can happen for register classes that can
51835183 // contain multiple different value types. The preg or vreg allocated may
51865186 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
51875187 Val = DAG.getNode(ISD::BIT_CONVERT, ResultType, Val);
51885188
5189 } else if (ResultType != Val.getValueType() &&
5189 } else if (ResultType != Val.getValueType() &&
51905190 ResultType.isInteger() && Val.getValueType().isInteger()) {
51915191 // If a result value was tied to an input value, the computed result may
51925192 // have a wider width than the expected result. Extract the relevant
51935193 // portion.
51945194 Val = DAG.getNode(ISD::TRUNCATE, ResultType, Val);
51955195 }
5196
5196
51975197 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
51985198 }
51995199
52005200 setValue(CS.getInstruction(), Val);
52015201 }
5202
5202
52035203 std::vector > StoresToEmit;
5204
5204
52055205 // Process indirect outputs, first output all of the flagged copies out of
52065206 // physregs.
52075207 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
52105210 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
52115211 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
52125212 }
5213
5213
52145214 // Emit the non-flagged stores from the physregs.
52155215 SmallVector OutChains;
52165216 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
52475247
52485248 std::pair Result =
52495249 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5250 CallingConv::C, PerformTailCallOpt,
5250 CallingConv::C, PerformTailCallOpt,
52515251 DAG.getExternalSymbol("malloc", IntPtr),
52525252 Args, DAG);
52535253 setValue(&I, Result.first); // Pointers always fit in registers
52695269 }
52705270
52715271 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5272 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
5273 getValue(I.getOperand(1)),
5272 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
5273 getValue(I.getOperand(1)),
52745274 DAG.getSrcValue(I.getOperand(1))));
52755275 }
52765276
52845284
52855285 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
52865286 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
5287 getValue(I.getOperand(1)),
5287 getValue(I.getOperand(1)),
52885288 DAG.getSrcValue(I.getOperand(1))));
52895289 }
52905290
52915291 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5292 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
5293 getValue(I.getOperand(1)),
5292 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
5293 getValue(I.getOperand(1)),
52945294 getValue(I.getOperand(2)),
52955295 DAG.getSrcValue(I.getOperand(1)),
52965296 DAG.getSrcValue(I.getOperand(2))));
52985298
52995299 /// TargetLowering::LowerArguments - This is the default LowerArguments
53005300 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5301 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5301 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
53025302 /// integrated into SDISel.
53035303 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
53045304 SmallVectorImpl &ArgValues) {
53645364 }
53655365
53665366 RetVals.push_back(MVT::Other);
5367
5367
53685368 // Create the node.
53695369 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
53705370 DAG.getVTList(&RetVals[0], RetVals.size()),
53715371 &Ops[0], Ops.size()).getNode();
5372
5372
53735373 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
53745374 // allows exposing the loads that may be part of the argument access to the
53755375 // first DAGCombiner pass.
53765376 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5377
5377
53785378 // The number of results should match up, except that the lowered one may have
53795379 // an extra flag result.
53805380 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
53895389 }
53905390
53915391 Result = TmpRes.getNode();
5392
5392
53935393 unsigned NumArgRegs = Result->getNumValues() - 1;
53945394 DAG.setRoot(SDValue(Result, NumArgRegs));
53955395
53965396 // Set up the return result vector.
53975397 unsigned i = 0;
53985398 unsigned Idx = 1;
5399 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5399 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
54005400 ++I, ++Idx) {
54015401 SmallVector ValueVTs;
54025402 ComputeValueVTs(*this, I->getType(), ValueVTs);
54415441 SmallVector Ops;
54425442 Ops.push_back(Chain); // Op#0 - Chain
54435443 Ops.push_back(Callee);
5444
5444
54455445 // Handle all of the outgoing arguments.
54465446 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
54475447 SmallVector ValueVTs;
55065506 }
55075507 }
55085508 }
5509
5509
55105510 // Figure out the result value types. We start by making a list of
55115511 // the potentially illegal return value types.
55125512 SmallVector LoweredRetTys;
55215521 for (unsigned i = 0; i != NumRegs; ++i)
55225522 LoweredRetTys.push_back(RegisterVT);
55235523 }
5524
5524
55255525 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5526
5526
55275527 // Create the CALL node.
55285528 SDValue Res = DAG.getCall(CallingConv, isVarArg, isTailCall, isInreg,
55295529 DAG.getVTList(&LoweredRetTys[0],
56365636 BasicBlock *SuccBB = TI->getSuccessor(succ);
56375637 if (!isa(SuccBB->begin())) continue;
56385638 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5639
5639
56405640 // If this terminator has multiple identical successors (common for
56415641 // switches), only handle each succ once.
56425642 if (!SuccsHandled.insert(SuccMBB)) continue;
5643
5643
56445644 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
56455645 PHINode *PN;
56465646
57075707 BasicBlock *SuccBB = TI->getSuccessor(succ);
57085708 if (!isa(SuccBB->begin())) continue;
57095709 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5710
5710
57115711 // If this terminator has multiple identical successors (common for
57125712 // switches), only handle each succ once.
57135713 if (!SuccsHandled.insert(SuccMBB)) continue;
5714
5714
57155715 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
57165716 PHINode *PN;
57175717
3535 using namespace llvm;
3636
3737 namespace {
38
38
3939 class VISIBILITY_HIDDEN ShadowStackGC : public GCStrategy {
4040 /// RootChain - This is the global linked-list that contains the chain of GC
4141 /// roots.
4242 GlobalVariable *Head;
43
43
4444 /// StackEntryTy - Abstract type of a link in the shadow stack.
45 ///
45 ///
4646 const StructType *StackEntryTy;
47
47
4848 /// Roots - GC roots in the current function. Each is a pair of the
4949 /// intrinsic call and its corresponding alloca.
5050 std::vector > Roots;
51
51
5252 public:
5353 ShadowStackGC();
54
54
5555 bool initializeCustomLowering(Module &M);
5656 bool performCustomLowering(Function &F);
57
57
5858 private:
5959 bool IsNullValue(Value *V);
6060 Constant *GetFrameMap(Function &F);
6767 };
6868
6969 }
70
70
7171 static GCRegistry::Add
7272 X("shadow-stack", "Very portable GC for uncooperative code generators");
73
73
7474 namespace {
7575 /// EscapeEnumerator - This is a little algorithm to find all escape points
7676 /// from a function so that "finally"-style code can be inserted. In addition
7777 /// to finding the existing return and unwind instructions, it also (if
7878 /// necessary) transforms any call instructions into invokes and sends them to
7979 /// a landing pad.
80 ///
80 ///
8181 /// It's wrapped up in a state machine using the same transform C# uses for
8282 /// 'yield return' enumerators, This transform allows it to be non-allocating.
8383 class VISIBILITY_HIDDEN EscapeEnumerator {
8484 Function &F;
8585 const char *CleanupBBName;
86
86
8787 // State.
8888 int State;
8989 Function::iterator StateBB, StateE;
9090 IRBuilder<> Builder;
91
91
9292 public:
9393 EscapeEnumerator(Function &F, const char *N = "cleanup")
9494 : F(F), CleanupBBName(N), State(0) {}
95
95
9696 IRBuilder<> *Next() {
9797 switch (State) {
9898 default:
9999 return 0;
100
100
101101 case 0:
102102 StateBB = F.begin();
103103 StateE = F.end();
104104 State = 1;
105
105
106106 case 1:
107107 // Find all 'return' and 'unwind' instructions.
108108 while (StateBB != StateE) {
109109 BasicBlock *CurBB = StateBB++;
110
110
111111 // Branches and invokes do not escape, only unwind and return do.
112112 TerminatorInst *TI = CurBB->getTerminator();
113113 if (!isa(TI) && !isa(TI))
114114 continue;
115
115
116116 Builder.SetInsertPoint(TI->getParent(), TI);
117117 return &Builder;
118118 }
119
119
120120 State = 2;
121
121
122122 // Find all 'call' instructions.
123123 SmallVector Calls;
124124 for (Function::iterator BB = F.begin(),
129129 if (!CI->getCalledFunction() ||
130130 !CI->getCalledFunction()->getIntrinsicID())
131131 Calls.push_back(CI);
132
132
133133 if (Calls.empty())
134134 return 0;
135
135
136136 // Create a cleanup block.
137137 BasicBlock *CleanupBB = BasicBlock::Create(CleanupBBName, &F);
138138 UnwindInst *UI = new UnwindInst(CleanupBB);
139
139
140140 // Transform the 'call' instructions into 'invoke's branching to the
141141 // cleanup block. Go in reverse order to make prettier BB names.
142142 SmallVector Args;
143143 for (unsigned I = Calls.size(); I != 0; ) {
144144 CallInst *CI = cast(Calls[--I]);
145
145
146146 // Split the basic block containing the function call.
147147 BasicBlock *CallBB = CI->getParent();
148148 BasicBlock *NewBB =
149149 CallBB->splitBasicBlock(CI, CallBB->getName() + ".cont");
150
150
151151 // Remove the unconditional branch inserted at the end of CallBB.
152152 CallBB->getInstList().pop_back();
153153 NewBB->getInstList().remove(CI);
154
154
155155 // Create a new invoke instruction.
156156 Args.clear();
157157 Args.append(CI->op_begin() + 1, CI->op_end());
158
158
159159 InvokeInst *II = InvokeInst::Create(CI->getOperand(0),
160160 NewBB, CleanupBB,
161161 Args.begin(), Args.end(),
165165 CI->replaceAllUsesWith(II);
166166 delete CI;
167167 }
168
168
169169 Builder.SetInsertPoint(UI->getParent(), UI);
170170 return &Builder;
171171 }
184184
185185 Constant *ShadowStackGC::GetFrameMap(Function &F) {
186186 // doInitialization creates the abstract type of this value.
187
187
188188 Type *VoidPtr = PointerType::getUnqual(Type::Int8Ty);
189
189
190190 // Truncate the ShadowStackDescriptor if some metadata is null.
191191 unsigned NumMeta = 0;
192192 SmallVector Metadata;
196196 NumMeta = I + 1;
197197 Metadata.push_back(ConstantExpr::getBitCast(C, VoidPtr));
198198 }
199
199
200200 Constant *BaseElts[] = {
201201 ConstantInt::get(Type::Int32Ty, Roots.size(), false),
202202 ConstantInt::get(Type::Int32Ty, NumMeta, false),
203203 };
204
204
205205 Constant *DescriptorElts[] = {
206206 ConstantStruct::get(BaseElts, 2),
207207 ConstantArray::get(ArrayType::get(VoidPtr, NumMeta),
208208 Metadata.begin(), NumMeta)
209209 };
210
210
211211 Constant *FrameMap = ConstantStruct::get(DescriptorElts, 2);
212
212
213213 std::string TypeName("gc_map.");
214214 TypeName += utostr(NumMeta);
215215 F.getParent()->addTypeName(TypeName, FrameMap->getType());
216
216
217217 // FIXME: Is this actually dangerous as WritingAnLLVMPass.html claims? Seems
218218 // that, short of multithreaded LLVM, it should be safe; all that is
219219 // necessary is that a simple Module::iterator loop not be invalidated.
220220 // Appending to the GlobalVariable list is safe in that sense.
221 //
221 //
222222 // All of the output passes emit globals last. The ExecutionEngine
223223 // explicitly supports adding globals to the module after
224224 // initialization.
225 //
225 //
226226 // Still, if it isn't deemed acceptable, then this transformation needs
227227 // to be a ModulePass (which means it cannot be in the 'llc' pipeline
228228 // (which uses a FunctionPassManager (which segfaults (not asserts) if
231231 GlobalVariable::InternalLinkage,
232232 FrameMap, "__gc_" + F.getName(),
233233 F.getParent());
234
234
235235 Constant *GEPIndices[2] = { ConstantInt::get(Type::Int32Ty, 0),
236236 ConstantInt::get(Type::Int32Ty, 0) };
237237 return ConstantExpr::getGetElementPtr(GV, GEPIndices, 2);
244244 for (size_t I = 0; I != Roots.size(); I++)
245245 EltTys.push_back(Roots[I].second->getAllocatedType());
246246 Type *Ty = StructType::get(EltTys);
247
247
248248 std::string TypeName("gc_stackentry.");
249249 TypeName += F.getName();
250250 F.getParent()->addTypeName(TypeName, Ty);
251
251
252252 return Ty;
253253 }
254254
266266 StructType *FrameMapTy = StructType::get(EltTys);
267267 M.addTypeName("gc_map", FrameMapTy);
268268 PointerType *FrameMapPtrTy = PointerType::getUnqual(FrameMapTy);
269
269
270270 // struct StackEntry {
271271 // ShadowStackEntry *Next; // Caller's stack entry.
272272 // FrameMap *Map; // Pointer to constant FrameMap.
273273 // void *Roots[]; // Stack roots (in-place array, so we pretend).
274274 // };
275275 OpaqueType *RecursiveTy = OpaqueType::get();
276
276
277277 EltTys.clear();
278278 EltTys.push_back(PointerType::getUnqual(RecursiveTy));
279279 EltTys.push_back(FrameMapPtrTy);
280280 PATypeHolder LinkTyH = StructType::get(EltTys);
281
281
282282 RecursiveTy->refineAbstractTypeTo(LinkTyH.get());
283283 StackEntryTy = cast(LinkTyH.get());
284284 const PointerType *StackEntryPtrTy = PointerType::getUnqual(StackEntryTy);
285285 M.addTypeName("gc_stackentry", LinkTyH.get()); // FIXME: Is this safe from
286286 // a FunctionPass?
287
287
288288 // Get the root chain if it already exists.
289289 Head = M.getGlobalVariable("llvm_gc_root_chain");
290290 if (!Head) {
298298 Head->setInitializer(Constant::getNullValue(StackEntryPtrTy));
299299 Head->setLinkage(GlobalValue::LinkOnceLinkage);
300300 }
301
301
302302 return true;
303303 }
304304
312312 // FIXME: Account for original alignment. Could fragment the root array.
313313 // Approach 1: Null initialize empty slots at runtime. Yuck.
314314 // Approach 2: Emit a map of the array instead of just a count.
315
315
316316 assert(Roots.empty() && "Not cleaned up?");
317
317
318318 SmallVector,16> MetaRoots;
319
319
320320 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
321321 for (BasicBlock::iterator II = BB->begin(), E = BB->end(); II != E;)
322322 if (IntrinsicInst *CI = dyn_cast(II++))
329329 else
330330 MetaRoots.push_back(Pair);
331331 }
332
332
333333 // Number roots with metadata (usually empty) at the beginning, so that the
334334 // FrameMap::Meta array can be elided.
335335 Roots.insert(Roots.begin(), MetaRoots.begin(), MetaRoots.end());
342342 ConstantInt::get(Type::Int32Ty, Idx),
343343 ConstantInt::get(Type::Int32Ty, Idx2) };
344344 Value* Val = B.CreateGEP(BasePtr, Indices, Indices + 3, Name);
345
345
346346 assert(isa(Val) && "Unexpected folded constant");
347
347
348348 return dyn_cast(Val);
349349 }
350350
354354 Value *Indices[] = { ConstantInt::get(Type::Int32Ty, 0),
355355 ConstantInt::get(Type::Int32Ty, Idx) };
356356 Value *Val = B.CreateGEP(BasePtr, Indices, Indices + 2, Name);
357
357
358358 assert(isa(Val) && "Unexpected folded constant");
359359
360360 return dyn_cast(Val);
364364 bool ShadowStackGC::performCustomLowering(Function &F) {
365365 // Find calls to llvm.gcroot.
366366 CollectRoots(F);
367
367
368368 // If there are no roots in this function, then there is no need to add a
369369 // stack map entry for it.
370370 if (Roots.empty())
371371 return false;
372
372
373373 // Build the constant map and figure the type of the shadow stack entry.
374374 Value *FrameMap = GetFrameMap(F);
375375 const Type *ConcreteStackEntryTy = GetConcreteStackEntryType(F);
376
376
377377 // Build the shadow stack entry at the very start of the function.
378378 BasicBlock::iterator IP = F.getEntryBlock().begin();
379379 IRBuilder<> AtEntry(IP->getParent(), IP);
380
380
381381 Instruction *StackEntry = AtEntry.CreateAlloca(ConcreteStackEntryTy, 0,
382382 "gc_frame");
383
383
384384 while (isa(IP)) ++IP;
385385 AtEntry.SetInsertPoint(IP->getParent(), IP);
386
386
387387 // Initialize the map pointer and load the current head of the shadow stack.
388388 Instruction *CurrentHead = AtEntry.CreateLoad(Head, "gc_currhead");
389389 Instruction *EntryMapPtr = CreateGEP(AtEntry, StackEntry,0,1,"gc_frame.map");
390390 AtEntry.CreateStore(FrameMap, EntryMapPtr);
391
391
392392 // After all the allocas...
393393 for (unsigned I = 0, E = Roots.size(); I != E; ++I) {
394394 // For each root, find the corresponding slot in the aggregate...
395395 Value *SlotPtr = CreateGEP(AtEntry, StackEntry, 1 + I, "gc_root");
396
396
397397 // And use it in lieu of the alloca.
398398 AllocaInst *OriginalAlloca = Roots[I].second;
399399 SlotPtr->takeName(OriginalAlloca);
400400 OriginalAlloca->replaceAllUsesWith(SlotPtr);
401401 }
402
402
403403 // Move past the original stores inserted by GCStrategy::InitRoots. This isn't
404404 // really necessary (the collector would never see the intermediate state at
405405 // runtime), but it's nicer not to push the half-initialized entry onto the
406406 // shadow stack.
407407 while (isa(IP)) ++IP;
408408 AtEntry.SetInsertPoint(IP->getParent(), IP);
409
409
410410 // Push the entry onto the shadow stack.
411411 Instruction *EntryNextPtr = CreateGEP(AtEntry,StackEntry,0,0,"gc_frame.next");
412412 Instruction *NewHeadVal = CreateGEP(AtEntry,StackEntry, 0, "gc_newhead");
413413 AtEntry.CreateStore(CurrentHead, EntryNextPtr);
414414 AtEntry.CreateStore(NewHeadVal, Head);
415
415
416416 // For each instruction that escapes...
417417 EscapeEnumerator EE(F, "gc_cleanup");
418418 while (IRBuilder<> *AtExit = EE.Next()) {
423423 Value *SavedHead = AtExit->CreateLoad(EntryNextPtr2, "gc_savedhead");
424424 AtExit->CreateStore(SavedHead, Head);
425425 }
426
426
427427 // Delete the original allocas (which are no longer used) and the intrinsic
428428 // calls (which are no longer valid). Doing this last avoids invalidating
429429 // iterators.
431431 Roots[I].first->eraseFromParent();
432432 Roots[I].second->eraseFromParent();
433433 }
434
434
435435 Roots.clear();
436436 return true;
437437 }
2525 MArch("march", cl::desc("Architecture to generate assembly for:"));
2626
2727 static cl::opt
28 MCPU("mcpu",
28 MCPU("mcpu",
2929 cl::desc("Target a specific cpu type (-mcpu=help for details)"),
3030 cl::value_desc("cpu-name"),
3131 cl::init(""));
3232
3333 static cl::list
34 MAttrs("mattr",
34 MAttrs("mattr",
3535 cl::CommaSeparated,
3636 cl::desc("Target specific attributes (-mattr=help for details)"),
3737 cl::value_desc("a1,+a2,-a3,..."));
5252
5353 static cl::opt Force("f", cl::desc("Overwrite output files"));
5454
55 static cl::opt Fast("fast",
55 static cl::opt Fast("fast",
5656 cl::desc("Generate code quickly, potentially sacrificing code quality"));
5757
5858 static cl::opt
6363 MArch("march", cl::desc("Architecture to generate code for:"));
6464
6565 static cl::opt
66 MCPU("mcpu",
66 MCPU("mcpu",
6767 cl::desc("Target a specific cpu type (-mcpu=help for details)"),
6868 cl::value_desc("cpu-name"),
6969 cl::init(""));
7070
7171 static cl::list
72 MAttrs("mattr",
72 MAttrs("mattr",
7373 cl::CommaSeparated,
7474 cl::desc("Target specific attributes (-mattr=help for details)"),
7575 cl::value_desc("a1,+a2,-a3,..."));
133133
134134 return Out;
135135 }
136
136
137137 if (InputFilename == "-") {
138138 OutputFilename = "-";
139139 return &outs();
140140 }
141141
142142 OutputFilename = GetFileNameRoot(InputFilename);
143
143
144144 bool Binary = false;
145145 switch (FileType) {
146146 case TargetMachine::AssemblyFile:
163163 Binary = true;
164164 break;
165165 }
166
166
167167 if (!Force && std::ifstream(OutputFilename.c_str())) {
168168 // If force is not specified, make sure not to overwrite a file!
169169 std::cerr << ProgName << ": error opening '" << OutputFilename
171171 << "Use -f command line argument to force output\n";
172172 return 0;
173173 }
174
174
175175 // Make sure that the Out file gets unlinked from the disk if we get a
176176 // SIGINT
177177 sys::RemoveFileOnSignal(sys::Path(OutputFilename));
178
178
179179 std::string error;
180180 raw_ostream *Out = new raw_fd_ostream(OutputFilename.c_str(), Binary, error);
181181 if (!error.empty()) {
183183 delete Out;
184184 return 0;
185185 }
186
186
187187 return Out;
188188 }
189189
197197 // Load the module to be compiled...
198198 std::string ErrorMessage;
199199 std::auto_ptr M;
200
200
201201 std::auto_ptr Buffer(
202202 MemoryBuffer::getFileOrSTDIN(InputFilename, &ErrorMessage));
203203 if (Buffer.get())
208208 return 1;
209209 }
210210 Module &mod = *M.get();
211
211
212212 // If we are supposed to override the target triple, do so now.
213213 if (!TargetTriple.empty())
214214 mod.setTargetTriple(TargetTriple);
215
215
216216 // Allocate target machine. First, check whether the user has
217217 // explicitly specified an architecture to compile for.
218218 if (MArch == 0) {
235235 Features.AddFeature(MAttrs[i]);
236236 FeaturesStr = Features.getString();
237237 }
238
238
239239 std::auto_ptr target(MArch->CtorFn(mod, FeaturesStr));
240240 assert(target.get() && "Could not allocate target machine!");
241241 TargetMachine &Target = *target.get();
243243 // Figure out where we are going to send the output...
244244 raw_ostream *Out = GetOutputStream(argv[0]);
245245 if (Out == 0) return 1;
246
246
247247 // If this target requires addPassesToEmitWholeFile, do it now. This is
248248 // used by strange things like the C backend.
249249 if (Target.WantsWholeFile()) {
251251 PM.add(new TargetData(*Target.getTargetData()));
252252 if (!NoVerify)
253253 PM.add(createVerifierPass());
254
254
255255 // Ask the target to add backend passes as necessary.
256256 if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, Fast)) {
257257 std::cerr << argv[0] << ": target does not support generation of this"
267267 ExistingModuleProvider Provider(M.release());
268268 FunctionPassManager Passes(&Provider);
269269 Passes.add(new TargetData(*Target.getTargetData()));
270
270
271271 #ifndef NDEBUG
272272 if (!NoVerify)
273273 Passes.add(createVerifierPass());
274274 #endif
275
275
276276 // Ask the target to add backend passes as necessary.
277277 MachineCodeEmitter *MCE = 0;
278278
305305 sys::Path(OutputFilename).eraseFromDisk();
306306 return 1;
307307 }
308
308
309309 Passes.doInitialization();
310
310
311311 // Run our queue of passes all at once now, efficiently.
312312 // TODO: this could lazily stream functions out of the module.
313313 for (Module::iterator I = mod.begin(), E = mod.end(); I != E; ++I)
314314 if (!I->isDeclaration())
315315 Passes.run(*I);
316
316
317317 Passes.doFinalization();
318318 }
319
319
320320 // Delete the ostream if it's not a stdout stream
321321 if (Out != &outs()) delete Out;
322322