llvm.org GIT mirror llvm / 5bd5b28
Merged in revision 1.60. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_16@24160 91177308-0d34-0410-b5e6-96231b3b80d8 John Criswell 13 years ago
1 changed file(s) with 5 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
962962 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT));
963963 }
964964 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
965 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
965 if (N1C && N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
966966 unsigned ExtendBits =
967967 MVT::getSizeInBits(cast(N0.getOperand(1))->getVT());
968 if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0)
968 if (ExtendBits == 64 || (N1C->getValue() & (~0ULL << ExtendBits) == 0))
969969 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
970970 }
971971 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
972 if (N0.getOpcode() == ISD::OR && N1C)
972 if (N1C && N0.getOpcode() == ISD::OR)
973973 if (ConstantSDNode *ORI = dyn_cast(N0.getOperand(1)))
974974 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
975975 return N1;
10301030 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
10311031 }
10321032 // fold (and (sra)) -> (and (srl)) when possible.
1033 if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse())
1033 if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) {
10341034 if (ConstantSDNode *N01C = dyn_cast(N0.getOperand(1))) {
10351035 // If the RHS of the AND has zeros where the sign bits of the SRA will
10361036 // land, turn the SRA into an SRL.
10421042 return SDOperand();
10431043 }
10441044 }
1045
1045 }
10461046 // fold (zext_inreg (extload x)) -> (zextload x)
10471047 if (N0.getOpcode() == ISD::EXTLOAD) {
10481048 MVT::ValueType EVT = cast(N0.getOperand(3))->getVT();