llvm.org GIT mirror llvm / 5bbbb37
Conservatively handle multiple MMOs in MIsNeedChainEdge MIsNeedChainEdge, which is used by -enable-aa-sched-mi (AA in misched), had an llvm_unreachable when -enable-aa-sched-mi is enabled and we reach an instruction with multiple MMOs. Instead, return a conservative answer. This allows testing -enable-aa-sched-mi on x86. Also, this moves the check above the isUnsafeMemoryObject checks. isUnsafeMemoryObject is currently correct only for instructions with one MMO (as noted in the comment in isUnsafeMemoryObject): // We purposefully do no check for hasOneMemOperand() here // in hope to trigger an assert downstream in order to // finish implementation. The problem with this is that, had the candidate edge passed the "!MIa->mayStore() && !MIb->mayStore()" check, the hoped-for assert would never happen (which could, in theory, lead to incorrect behavior if one of these secondary MMOs was volatile, for example). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198795 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 6 years ago
2 changed file(s) with 41 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
511511 if (MIa == MIb)
512512 return false;
513513
514 // FIXME: Need to handle multiple memory operands to support all targets.
515 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
516 return true;
517
514518 if (isUnsafeMemoryObject(MIa, MFI) || isUnsafeMemoryObject(MIb, MFI))
515519 return true;
516520
525529
526530 MachineMemOperand *MMOa = *MIa->memoperands_begin();
527531 MachineMemOperand *MMOb = *MIb->memoperands_begin();
528
529 // FIXME: Need to handle multiple memory operands to support all targets.
530 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
531 llvm_unreachable("Multiple memory operands.");
532532
533533 // The following interface to AA is fashioned after DAGCombiner::isAlias
534534 // and operates with MachineMemOperand offset with some important
0 ; RUN: llc -enable-misched -enable-aa-sched-mi < %s
1
2 ; This generates a decw instruction, which has two MMOs, and an alias SU edge
3 ; query involving that instruction. Make sure this does not crash.
4
5 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
6 target triple = "x86_64-unknown-linux-gnu"
7
8 %s1 = type { i16, i16, i32 }
9 %c1 = type { %s1*, %u1, i16, i8 }
10 %u1 = type { i64 }
11
12 declare zeroext i1 @bar(i64*, i32) #5
13
14 define i32 @foo() #0 align 2 {
15 entry:
16 %temp_rhs = alloca %c1, align 8
17 br i1 undef, label %if.else56, label %cond.end.i
18
19 cond.end.i:
20 %significand.i18.i = getelementptr inbounds %c1* %temp_rhs, i64 0, i32 1
21 %exponent.i = getelementptr inbounds %c1* %temp_rhs, i64 0, i32 2
22 %0 = load i16* %exponent.i, align 8
23 %sub.i = add i16 %0, -1
24 store i16 %sub.i, i16* %exponent.i, align 8
25 %parts.i.i = bitcast %u1* %significand.i18.i to i64**
26 %1 = load i64** %parts.i.i, align 8
27 %call5.i = call zeroext i1 @bar(i64* %1, i32 undef) #1
28 unreachable
29
30 if.else56:
31 unreachable
32 }
33
34 attributes #0 = { nounwind uwtable }
35 attributes #1 = { nounwind }
36