llvm.org GIT mirror llvm / 5b9e507
MIRParser: Add support for parsing vreg reg alloc hints Reviewers: qcolombet, MatzeB Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D26573 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286911 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 years ago
4 changed file(s) with 33 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
124124 bool parseStandaloneMBB(MachineBasicBlock *&MBB);
125125 bool parseStandaloneNamedRegister(unsigned &Reg);
126126 bool parseStandaloneVirtualRegister(VRegInfo *&Info);
127 bool parseStandaloneRegister(unsigned &Reg);
127128 bool parseStandaloneStackObject(int &FI);
128129 bool parseStandaloneMDNode(MDNode *&Node);
129130
721722 return error("expected a virtual register");
722723 if (parseVirtualRegister(Info))
723724 return true;
725 lex();
726 if (Token.isNot(MIToken::Eof))
727 return error("expected end of string after the register reference");
728 return false;
729 }
730
731 bool MIParser::parseStandaloneRegister(unsigned &Reg) {
732 lex();
733 if (Token.isNot(MIToken::NamedRegister) &&
734 Token.isNot(MIToken::VirtualRegister))
735 return error("expected either a named or virtual register");
736
737 VRegInfo *Info;
738 if (parseRegister(Reg, Info))
739 return true;
740
724741 lex();
725742 if (Token.isNot(MIToken::Eof))
726743 return error("expected end of string after the register reference");
22292246 return MIParser(PFS, Error, Src).parseStandaloneMBB(MBB);
22302247 }
22312248
2249 bool llvm::parseRegisterReference(PerFunctionMIParsingState &PFS,
2250 unsigned &Reg, StringRef Src,
2251 SMDiagnostic &Error) {
2252 return MIParser(PFS, Error, Src).parseStandaloneRegister(Reg);
2253 }
2254
22322255 bool llvm::parseNamedRegisterReference(PerFunctionMIParsingState &PFS,
22332256 unsigned &Reg, StringRef Src,
22342257 SMDiagnostic &Error) {
9595 MachineBasicBlock *&MBB, StringRef Src,
9696 SMDiagnostic &Error);
9797
98 bool parseRegisterReference(PerFunctionMIParsingState &PFS,
99 unsigned &Reg, StringRef Src,
100 SMDiagnostic &Error);
101
98102 bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg,
99103 StringRef Src, SMDiagnostic &Error);
100104
438438 if (Info.Kind != VRegInfo::NORMAL)
439439 return error(VReg.Class.SourceRange.Start,
440440 Twine("preferred register can only be set for normal vregs"));
441 if (parseNamedRegisterReference(PFS, Info.PreferredReg,
442 VReg.PreferredRegister.Value, Error))
441
442 if (parseRegisterReference(PFS, Info.PreferredReg,
443 VReg.PreferredRegister.Value, Error))
443444 return error(Error, VReg.PreferredRegister.SourceRange);
444445 }
445446 }
None # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
0 # RUN: llc -march=x86-64 -run-pass none -o - %s 2>&1 | FileCheck %s
11
22 --- |
33
1313 tracksRegLiveness: true
1414 registers:
1515 - { id: 0, class: gr32 }
16 # CHECK: [[@LINE+1]]:48: expected a named register
16 # CHECK: - { id: 1, class: gr32, preferred-register: '%0' }
17 # CHECK: - { id: 2, class: gr32, preferred-register: '%edi' }
1718 - { id: 1, class: gr32, preferred-register: '%0' }
1819 - { id: 2, class: gr32, preferred-register: '%edi' }
1920 body: |