llvm.org GIT mirror llvm / 5b9b80e
CodeGen: TII: Take MachineInstr& in predicate API, NFC Change TargetInstrInfo API to take `MachineInstr&` instead of `MachineInstr*` in the functions related to predicated instructions (I'll try to come back later and get some of the rest). All of these functions require non-null parameters already, so references are more clear. As a bonus, this happens to factor away a host of implicit iterator => pointer conversions. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261605 91177308-0d34-0410-b5e6-96231b3b80d8 Duncan P. N. Exon Smith 4 years ago
47 changed file(s) with 405 addition(s) and 425 deletion(s). Raw diff Collapse all Expand all
10091009
10101010
10111011 /// Returns true if the instruction is already predicated.
1012 virtual bool isPredicated(const MachineInstr *MI) const {
1012 virtual bool isPredicated(const MachineInstr &MI) const {
10131013 return false;
10141014 }
10151015
10161016 /// Returns true if the instruction is a
10171017 /// terminator instruction that has not been predicated.
1018 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
1018 virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
10191019
10201020 /// Convert the instruction into a predicated instruction.
10211021 /// It returns true if the operation was successful.
1022 virtual
1023 bool PredicateInstruction(MachineInstr *MI,
1024 ArrayRef Pred) const;
1022 virtual bool PredicateInstruction(MachineInstr &MI,
1023 ArrayRef Pred) const;
10251024
10261025 /// Returns true if the first specified predicate
10271026 /// subsumes the second, e.g. GE subsumes GT.
10341033 /// If the specified instruction defines any predicate
10351034 /// or condition code register(s) used for predication, returns true as well
10361035 /// as the definition predicate(s) by reference.
1037 virtual bool DefinesPredicate(MachineInstr *MI,
1036 virtual bool DefinesPredicate(MachineInstr &MI,
10381037 std::vector &Pred) const {
10391038 return false;
10401039 }
10421041 /// Return true if the specified instruction can be predicated.
10431042 /// By default, this returns true for every instruction with a
10441043 /// PredicateOperand.
1045 virtual bool isPredicable(MachineInstr *MI) const {
1046 return MI->getDesc().isPredicable();
1044 virtual bool isPredicable(MachineInstr &MI) const {
1045 return MI.getDesc().isPredicable();
10471046 }
10481047
10491048 /// Return true if it's safe to move a machine
11771176 const MachineInstr *MI,
11781177 unsigned *PredCost = nullptr) const;
11791178
1180 virtual unsigned getPredicationCost(const MachineInstr *MI) const;
1179 virtual unsigned getPredicationCost(const MachineInstr &MI) const;
11811180
11821181 virtual int getInstrLatency(const InstrItineraryData *ItinData,
11831182 SDNode *Node) const;
367367 // reference either system calls or the register directly. Skip it until we
368368 // can tell user specified registers from compiler-specified.
369369 if (MI->isCall() || MI->hasExtraDefRegAllocReq() ||
370 TII->isPredicated(MI) || MI->isInlineAsm()) {
370 TII->isPredicated(*MI) || MI->isInlineAsm()) {
371371 DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
372372 State->UnionGroups(Reg, 0);
373373 }
443443 // instruction which may not be executed. The second R6 def may or may not
444444 // re-define R6 so it's not safe to change it since the last R6 use cannot be
445445 // changed.
446 bool Special = MI->isCall() ||
447 MI->hasExtraSrcRegAllocReq() ||
448 TII->isPredicated(MI) || MI->isInlineAsm();
446 bool Special = MI->isCall() || MI->hasExtraSrcRegAllocReq() ||
447 TII->isPredicated(*MI) || MI->isInlineAsm();
449448
450449 // Scan the register uses for this instruction and update
451450 // live-ranges, groups and RegRefs.
166166
167167 MachineBasicBlock::iterator FirstTerm = I;
168168 while (I != MBB->end()) {
169 if (!TII->isUnpredicatedTerminator(I))
169 if (!TII->isUnpredicatedTerminator(*I))
170170 return false;
171171 // See if it uses any of the implicitly defined registers.
172172 for (const MachineOperand &MO : I->operands()) {
16221622 SmallSet &Uses,
16231623 SmallSet &Defs) {
16241624 MachineBasicBlock::iterator Loc = MBB->getFirstTerminator();
1625 if (!TII->isUnpredicatedTerminator(Loc))
1625 if (!TII->isUnpredicatedTerminator(*Loc))
16261626 return MBB->end();
16271627
16281628 for (const MachineOperand &MO : Loc->operands()) {
16841684 // Also avoid moving code above predicated instruction since it's hard to
16851685 // reason about register liveness with predicated instruction.
16861686 bool DontMoveAcrossStore = true;
1687 if (!PI->isSafeToMove(nullptr, DontMoveAcrossStore) || TII->isPredicated(PI))
1687 if (!PI->isSafeToMove(nullptr, DontMoveAcrossStore) || TII->isPredicated(*PI))
16881688 return MBB->end();
16891689
16901690
17641764 if (!TIB->isIdenticalTo(FIB, MachineInstr::CheckKillDead))
17651765 break;
17661766
1767 if (TII->isPredicated(TIB))
1767 if (TII->isPredicated(*TIB))
17681768 // Hard to reason about register liveness with predicated instruction.
17691769 break;
17701770
162162 // instruction which may not be executed. The second R6 def may or may not
163163 // re-define R6 so it's not safe to change it since the last R6 use cannot be
164164 // changed.
165 bool Special = MI->isCall() ||
166 MI->hasExtraSrcRegAllocReq() ||
167 TII->isPredicated(MI);
165 bool Special =
166 MI->isCall() || MI->hasExtraSrcRegAllocReq() || TII->isPredicated(*MI);
168167
169168 // Scan the register operands for this instruction and update
170169 // Classes and RegRefs.
240239 // instruction are now dead.
241240 assert(!MI->isKill() && "Attempting to scan a kill instruction");
242241
243 if (!TII->isPredicated(MI)) {
242 if (!TII->isPredicated(*MI)) {
244243 // Predicated defs are modeled as read + write, i.e. similar to two
245244 // address updates.
246245 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
584583 // If MI's defs have a special allocation requirement, don't allow
585584 // any def registers to be changed. Also assume all registers
586585 // defined in a call must not be changed (ABI).
587 if (MI->isCall() || MI->hasExtraDefRegAllocReq() || TII->isPredicated(MI))
586 if (MI->isCall() || MI->hasExtraDefRegAllocReq() || TII->isPredicated(*MI))
588587 // If this instruction's defs have special allocation requirement, don't
589588 // break this anti-dependency.
590589 AntiDepReg = 0;
667667 BBI.ExtraCost = 0;
668668 BBI.ExtraCost2 = 0;
669669 BBI.ClobbersPred = false;
670 for (MachineBasicBlock::iterator I = BBI.BB->begin(), E = BBI.BB->end();
671 I != E; ++I) {
672 if (I->isDebugValue())
670 for (auto &MI : *BBI.BB) {
671 if (MI.isDebugValue())
673672 continue;
674673
675 if (I->isNotDuplicable())
674 if (MI.isNotDuplicable())
676675 BBI.CannotBeCopied = true;
677676
678 bool isPredicated = TII->isPredicated(I);
679 bool isCondBr = BBI.IsBrAnalyzable && I->isConditionalBranch();
677 bool isPredicated = TII->isPredicated(MI);
678 bool isCondBr = BBI.IsBrAnalyzable && MI.isConditionalBranch();
680679
681680 // A conditional branch is not predicable, but it may be eliminated.
682681 if (isCondBr)
684683
685684 if (!isPredicated) {
686685 BBI.NonPredSize++;
687 unsigned ExtraPredCost = TII->getPredicationCost(&*I);
688 unsigned NumCycles = SchedModel.computeInstrLatency(&*I, false);
686 unsigned ExtraPredCost = TII->getPredicationCost(MI);
687 unsigned NumCycles = SchedModel.computeInstrLatency(&MI, false);
689688 if (NumCycles > 1)
690689 BBI.ExtraCost += NumCycles-1;
691690 BBI.ExtraCost2 += ExtraPredCost;
709708 // FIXME: Make use of PredDefs? e.g. ADDC, SUBC sets predicates but are
710709 // still potentially predicable.
711710 std::vector PredDefs;
712 if (TII->DefinesPredicate(I, PredDefs))
711 if (TII->DefinesPredicate(MI, PredDefs))
713712 BBI.ClobbersPred = true;
714713
715 if (!TII->isPredicable(I)) {
714 if (!TII->isPredicable(MI)) {
716715 BBI.IsUnpredicable = true;
717716 return;
718717 }
10101009
10111010 /// Behaves like LiveRegUnits::StepForward() but also adds implicit uses to all
10121011 /// values defined in MI which are not live/used by MI.
1013 static void UpdatePredRedefs(MachineInstr *MI, LivePhysRegs &Redefs) {
1012 static void UpdatePredRedefs(MachineInstr &MI, LivePhysRegs &Redefs) {
10141013 SmallVector, 4> Clobbers;
1015 Redefs.stepForward(*MI, Clobbers);
1014 Redefs.stepForward(MI, Clobbers);
10161015
10171016 // Now add the implicit uses for each of the clobbered values.
10181017 for (auto Reg : Clobbers) {
14901489 if (!BBI2->BB->empty() && (DI2 == BBI2->BB->end())) {
14911490 MachineBasicBlock::iterator BBI1T = BBI1->BB->getFirstTerminator();
14921491 MachineBasicBlock::iterator BBI2T = BBI2->BB->getFirstTerminator();
1493 if ((BBI1T != BBI1->BB->end()) && TII->isPredicated(BBI1T) &&
1494 ((BBI2T != BBI2->BB->end()) && !TII->isPredicated(BBI2T)))
1492 if (BBI1T != BBI1->BB->end() && TII->isPredicated(*BBI1T) &&
1493 BBI2T != BBI2->BB->end() && !TII->isPredicated(*BBI2T))
14951494 --DI2;
14961495 }
14971496
15141513 // (e.g. a predicated return). If that is the case, we cannot merge
15151514 // it with the tail block.
15161515 MachineBasicBlock::const_iterator TI = BBI.BB->getFirstTerminator();
1517 if (TI != BBI.BB->end() && TII->isPredicated(TI))
1516 if (TI != BBI.BB->end() && TII->isPredicated(*TI))
15181517 CanMergeTail = false;
15191518 // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
15201519 // check if there are any other predecessors besides those.
15801579 bool AnyUnpred = false;
15811580 bool MaySpec = LaterRedefs != nullptr;
15821581 for (MachineBasicBlock::iterator I = BBI.BB->begin(); I != E; ++I) {
1583 if (I->isDebugValue() || TII->isPredicated(I))
1582 if (I->isDebugValue() || TII->isPredicated(*I))
15841583 continue;
15851584 // It may be possible not to predicate an instruction if it's the 'true'
15861585 // side of a diamond and the 'false' side may re-define the instruction's
15921591 // If any instruction is predicated, then every instruction after it must
15931592 // be predicated.
15941593 MaySpec = false;
1595 if (!TII->PredicateInstruction(I, Cond)) {
1594 if (!TII->PredicateInstruction(*I, Cond)) {
15961595 #ifndef NDEBUG
15971596 dbgs() << "Unable to predicate " << *I << "!\n";
15981597 #endif
16011600
16021601 // If the predicated instruction now redefines a register as the result of
16031602 // if-conversion, add an implicit kill.
1604 UpdatePredRedefs(I, Redefs);
1603 UpdatePredRedefs(*I, Redefs);
16051604 }
16061605
16071606 BBI.Predicate.append(Cond.begin(), Cond.end());
16211620 bool IgnoreBr) {
16221621 MachineFunction &MF = *ToBBI.BB->getParent();
16231622
1624 for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
1625 E = FromBBI.BB->end(); I != E; ++I) {
1623 for (auto &I : *FromBBI.BB) {
16261624 // Do not copy the end of the block branches.
1627 if (IgnoreBr && I->isBranch())
1625 if (IgnoreBr && I.isBranch())
16281626 break;
16291627
1630 MachineInstr *MI = MF.CloneMachineInstr(I);
1628 MachineInstr *MI = MF.CloneMachineInstr(&I);
16311629 ToBBI.BB->insert(ToBBI.BB->end(), MI);
16321630 ToBBI.NonPredSize++;
1633 unsigned ExtraPredCost = TII->getPredicationCost(&*I);
1634 unsigned NumCycles = SchedModel.computeInstrLatency(&*I, false);
1631 unsigned ExtraPredCost = TII->getPredicationCost(I);
1632 unsigned NumCycles = SchedModel.computeInstrLatency(&I, false);
16351633 if (NumCycles > 1)
16361634 ToBBI.ExtraCost += NumCycles-1;
16371635 ToBBI.ExtraCost2 += ExtraPredCost;
16381636
16391637 if (!TII->isPredicated(I) && !MI->isDebugValue()) {
1640 if (!TII->PredicateInstruction(MI, Cond)) {
1638 if (!TII->PredicateInstruction(*MI, Cond)) {
16411639 #ifndef NDEBUG
1642 dbgs() << "Unable to predicate " << *I << "!\n";
1640 dbgs() << "Unable to predicate " << I << "!\n";
16431641 #endif
16441642 llvm_unreachable(nullptr);
16451643 }
16471645
16481646 // If the predicated instruction now redefines a register as the result of
16491647 // if-conversion, add an implicit kill.
1650 UpdatePredRedefs(MI, Redefs);
1648 UpdatePredRedefs(*MI, Redefs);
16511649
16521650 // Some kill flags may not be correct anymore.
16531651 if (!DontKill.empty())
16941692 ToBBI.BB->splice(ToTI, FromBBI.BB, FromBBI.BB->begin(), FromTI);
16951693
16961694 // If FromBB has non-predicated terminator we should copy it at the end.
1697 if ((FromTI != FromBBI.BB->end()) && !TII->isPredicated(FromTI))
1695 if (FromTI != FromBBI.BB->end() && !TII->isPredicated(*FromTI))
16981696 ToTI = ToBBI.BB->end();
16991697 ToBBI.BB->splice(ToTI, FromBBI.BB, FromTI, FromBBI.BB->end());
17001698
690690 // is possible. The isPredicated check is needed because this code can be
691691 // called during IfConversion, where an instruction which is normally a
692692 // Barrier is predicated and thus no longer an actual control barrier.
693 return empty() || !back().isBarrier() || TII->isPredicated(&back());
693 return empty() || !back().isBarrier() || TII->isPredicated(back());
694694 }
695695
696696 // If there is no branch, control always falls through.
629629 "differs from its CFG successor!", MBB);
630630 }
631631 if (!MBB->empty() && MBB->back().isBarrier() &&
632 !TII->isPredicated(&MBB->back())) {
632 !TII->isPredicated(MBB->back())) {
633633 report("MBB exits via unconditional fall-through but ends with a "
634634 "barrier instruction!", MBB);
635635 }
771771 // Ensure non-terminators don't follow terminators.
772772 // Ignore predicated terminators formed by if conversion.
773773 // FIXME: If conversion shouldn't need to violate this rule.
774 if (MI->isTerminator() && !TII->isPredicated(MI)) {
774 if (MI->isTerminator() && !TII->isPredicated(*MI)) {
775775 if (!FirstTerminator)
776776 FirstTerminator = MI;
777777 } else if (FirstTerminator) {
255255 return true;
256256 }
257257
258 bool
259 TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
260 if (!MI->isTerminator()) return false;
258 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
259 if (!MI.isTerminator()) return false;
261260
262261 // Conditional branch is a special case.
263 if (MI->isBranch() && !MI->isBarrier())
262 if (MI.isBranch() && !MI.isBarrier())
264263 return true;
265 if (!MI->isPredicable())
264 if (!MI.isPredicable())
266265 return true;
267266 return !isPredicated(MI);
268267 }
269268
270269 bool TargetInstrInfo::PredicateInstruction(
271 MachineInstr *MI, ArrayRef Pred) const {
270 MachineInstr &MI, ArrayRef Pred) const {
272271 bool MadeChange = false;
273272
274 assert(!MI->isBundle() &&
273 assert(!MI.isBundle() &&
275274 "TargetInstrInfo::PredicateInstruction() can't handle bundles");
276275
277 const MCInstrDesc &MCID = MI->getDesc();
278 if (!MI->isPredicable())
276 const MCInstrDesc &MCID = MI.getDesc();
277 if (!MI.isPredicable())
279278 return false;
280279
281 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
280 for (unsigned j = 0, i = 0, e = MI.getNumOperands(); i != e; ++i) {
282281 if (MCID.OpInfo[i].isPredicate()) {
283 MachineOperand &MO = MI->getOperand(i);
282 MachineOperand &MO = MI.getOperand(i);
284283 if (MO.isReg()) {
285284 MO.setReg(Pred[j].getReg());
286285 MadeChange = true;
10341033 return 1;
10351034 }
10361035
1037 unsigned TargetInstrInfo::getPredicationCost(const MachineInstr *) const {
1036 unsigned TargetInstrInfo::getPredicationCost(const MachineInstr &) const {
10381037 return 0;
10391038 }
10401039
281281 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
282282 const MachineFunction &MF = *DefMI->getParent()->getParent();
283283 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
284 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
284 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
285285 return computeInstrLatency(DefMI);
286286
287287 // If we have a per operand scheduling model, check if this def is writing
9898 if (I == MBB.end())
9999 return false;
100100
101 if (!isUnpredicatedTerminator(I))
101 if (!isUnpredicatedTerminator(*I))
102102 return false;
103103
104104 // Get the last instruction in the block.
106106
107107 // If there is only one terminator instruction, process it.
108108 unsigned LastOpc = LastInst->getOpcode();
109 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
109 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
110110 if (isUncondBranchOpcode(LastOpc)) {
111111 TBB = LastInst->getOperand(0).getMBB();
112112 return false;
130130 LastInst->eraseFromParent();
131131 LastInst = SecondLastInst;
132132 LastOpc = LastInst->getOpcode();
133 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
133 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
134134 // Return now the only terminator is an unconditional branch.
135135 TBB = LastInst->getOperand(0).getMBB();
136136 return false;
142142 }
143143
144144 // If there are three terminators, we don't know what sort of block this is.
145 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
145 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
146146 return true;
147147
148148 // If the block ends with a B and a Bcc, handle it.
875875 return 2;
876876 }
877877
878 bool
879 R600InstrInfo::isPredicated(const MachineInstr *MI) const {
880 int idx = MI->findFirstPredOperandIdx();
878 bool R600InstrInfo::isPredicated(const MachineInstr &MI) const {
879 int idx = MI.findFirstPredOperandIdx();
881880 if (idx < 0)
882881 return false;
883882
884 unsigned Reg = MI->getOperand(idx).getReg();
883 unsigned Reg = MI.getOperand(idx).getReg();
885884 switch (Reg) {
886885 default: return false;
887886 case AMDGPU::PRED_SEL_ONE:
891890 }
892891 }
893892
894 bool
895 R600InstrInfo::isPredicable(MachineInstr *MI) const {
893 bool R600InstrInfo::isPredicable(MachineInstr &MI) const {
896894 // XXX: KILL* instructions can be predicated, but they must be the last
897895 // instruction in a clause, so this means any instructions after them cannot
898896 // be predicated. Until we have proper support for instruction clauses in the
899897 // backend, we will mark KILL* instructions as unpredicable.
900898
901 if (MI->getOpcode() == AMDGPU::KILLGT) {
899 if (MI.getOpcode() == AMDGPU::KILLGT) {
902900 return false;
903 } else if (MI->getOpcode() == AMDGPU::CF_ALU) {
901 } else if (MI.getOpcode() == AMDGPU::CF_ALU) {
904902 // If the clause start in the middle of MBB then the MBB has more
905903 // than a single clause, unable to predicate several clauses.
906 if (MI->getParent()->begin() != MachineBasicBlock::iterator(MI))
904 if (MI.getParent()->begin() != MachineBasicBlock::iterator(MI))
907905 return false;
908906 // TODO: We don't support KC merging atm
909 if (MI->getOperand(3).getImm() != 0 || MI->getOperand(4).getImm() != 0)
907 if (MI.getOperand(3).getImm() != 0 || MI.getOperand(4).getImm() != 0)
910908 return false;
911909 return true;
912 } else if (isVector(*MI)) {
910 } else if (isVector(MI)) {
913911 return false;
914912 } else {
915913 return AMDGPUInstrInfo::isPredicable(MI);
985983 return false;
986984 }
987985
988 bool
989 R600InstrInfo::DefinesPredicate(MachineInstr *MI,
990 std::vector &Pred) const {
991 return isPredicateSetter(MI->getOpcode());
986 bool R600InstrInfo::DefinesPredicate(MachineInstr &MI,
987 std::vector &Pred) const {
988 return isPredicateSetter(MI.getOpcode());
992989 }
993990
994991
998995 return false;
999996 }
1000997
1001
1002 bool
1003 R600InstrInfo::PredicateInstruction(MachineInstr *MI,
1004 ArrayRef Pred) const {
1005 int PIdx = MI->findFirstPredOperandIdx();
1006
1007 if (MI->getOpcode() == AMDGPU::CF_ALU) {
1008 MI->getOperand(8).setImm(0);
1009 return true;
1010 }
1011
1012 if (MI->getOpcode() == AMDGPU::DOT_4) {
1013 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_X))
998 bool R600InstrInfo::PredicateInstruction(MachineInstr &MI,
999 ArrayRef Pred) const {
1000 int PIdx = MI.findFirstPredOperandIdx();
1001
1002 if (MI.getOpcode() == AMDGPU::CF_ALU) {
1003 MI.getOperand(8).setImm(0);
1004 return true;
1005 }
1006
1007 if (MI.getOpcode() == AMDGPU::DOT_4) {
1008 MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_X))
10141009 .setReg(Pred[2].getReg());
1015 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Y))
1010 MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Y))
10161011 .setReg(Pred[2].getReg());
1017 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Z))
1012 MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Z))
10181013 .setReg(Pred[2].getReg());
1019 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_W))
1014 MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_W))
10201015 .setReg(Pred[2].getReg());
1021 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1016 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
10221017 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
10231018 return true;
10241019 }
10251020
10261021 if (PIdx != -1) {
1027 MachineOperand &PMO = MI->getOperand(PIdx);
1022 MachineOperand &PMO = MI.getOperand(PIdx);
10281023 PMO.setReg(Pred[2].getReg());
1029 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1024 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
10301025 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
10311026 return true;
10321027 }
10341029 return false;
10351030 }
10361031
1037 unsigned int R600InstrInfo::getPredicationCost(const MachineInstr *) const {
1032 unsigned int R600InstrInfo::getPredicationCost(const MachineInstr &) const {
10381033 return 2;
10391034 }
10401035
167167
168168 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
169169
170 bool isPredicated(const MachineInstr *MI) const override;
171
172 bool isPredicable(MachineInstr *MI) const override;
170 bool isPredicated(const MachineInstr &MI) const override;
171
172 bool isPredicable(MachineInstr &MI) const override;
173173
174174 bool
175175 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
186186 unsigned NumFCycles, unsigned ExtraFCycles,
187187 BranchProbability Probability) const override;
188188
189 bool DefinesPredicate(MachineInstr *MI,
190 std::vector &Pred) const override;
189 bool DefinesPredicate(MachineInstr &MI,
190 std::vector &Pred) const override;
191191
192192 bool SubsumesPredicate(ArrayRef Pred1,
193193 ArrayRef Pred2) const override;
195195 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
196196 MachineBasicBlock &FMBB) const override;
197197
198 bool PredicateInstruction(MachineInstr *MI,
198 bool PredicateInstruction(MachineInstr &MI,
199199 ArrayRef Pred) const override;
200200
201 unsigned int getPredicationCost(const MachineInstr *) const override;
201 unsigned int getPredicationCost(const MachineInstr &) const override;
202202
203203 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
204204 const MachineInstr *MI,
8484 if (LastDstChan >= BISlot)
8585 isTrans = true;
8686 LastDstChan = BISlot;
87 if (TII->isPredicated(&*BI))
87 if (TII->isPredicated(*BI))
8888 continue;
8989 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write);
9090 if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0)
288288
289289 // Walk backwards from the end of the basic block until the branch is
290290 // analyzed or we give up.
291 while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) {
291 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
292292
293293 // Flag to be raised on unanalyzeable instructions. This is useful in cases
294294 // where we want to clean up on the end of the basic block before we bail
321321 Cond.push_back(I->getOperand(2));
322322 } else if (I->isReturn()) {
323323 // Returns can't be analyzed, but we should run cleanup.
324 CantAnalyze = !isPredicated(I);
324 CantAnalyze = !isPredicated(*I);
325325 } else {
326326 // We encountered other unrecognized terminator. Bail out immediately.
327327 return true;
329329
330330 // Cleanup code - to be run for unpredicated unconditional branches and
331331 // returns.
332 if (!isPredicated(I) &&
332 if (!isPredicated(*I) &&
333333 (isUncondBranchOpcode(I->getOpcode()) ||
334334 isIndirectBranchOpcode(I->getOpcode()) ||
335335 isJumpTableBranchOpcode(I->getOpcode()) ||
437437 return false;
438438 }
439439
440 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
441 if (MI->isBundle()) {
442 MachineBasicBlock::const_instr_iterator I = MI->getIterator();
443 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
440 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {
441 if (MI.isBundle()) {
442 MachineBasicBlock::const_instr_iterator I = MI.getIterator();
443 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
444444 while (++I != E && I->isInsideBundle()) {
445445 int PIdx = I->findFirstPredOperandIdx();
446446 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
449449 return false;
450450 }
451451
452 int PIdx = MI->findFirstPredOperandIdx();
453 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
454 }
455
456 bool ARMBaseInstrInfo::
457 PredicateInstruction(MachineInstr *MI, ArrayRef Pred) const {
458 unsigned Opc = MI->getOpcode();
452 int PIdx = MI.findFirstPredOperandIdx();
453 return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
454 }
455
456 bool ARMBaseInstrInfo::PredicateInstruction(
457 MachineInstr &MI, ArrayRef Pred) const {
458 unsigned Opc = MI.getOpcode();
459459 if (isUncondBranchOpcode(Opc)) {
460 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
461 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
460 MI.setDesc(get(getMatchingCondBranchOpcode(Opc)));
461 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
462462 .addImm(Pred[0].getImm())
463463 .addReg(Pred[1].getReg());
464464 return true;
465465 }
466466
467 int PIdx = MI->findFirstPredOperandIdx();
467 int PIdx = MI.findFirstPredOperandIdx();
468468 if (PIdx != -1) {
469 MachineOperand &PMO = MI->getOperand(PIdx);
469 MachineOperand &PMO = MI.getOperand(PIdx);
470470 PMO.setImm(Pred[0].getImm());
471 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
471 MI.getOperand(PIdx+1).setReg(Pred[1].getReg());
472472 return true;
473473 }
474474 return false;
500500 }
501501 }
502502
503 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
504 std::vector &Pred) const {
503 bool ARMBaseInstrInfo::DefinesPredicate(
504 MachineInstr &MI, std::vector &Pred) const {
505505 bool Found = false;
506 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
507 const MachineOperand &MO = MI->getOperand(i);
506 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
507 const MachineOperand &MO = MI.getOperand(i);
508508 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
509509 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
510510 Pred.push_back(MO);
554554 /// isPredicable - Return true if the specified instruction can be predicated.
555555 /// By default, this returns true for every instruction with a
556556 /// PredicateOperand.
557 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
558 if (!MI->isPredicable())
557 bool ARMBaseInstrInfo::isPredicable(MachineInstr &MI) const {
558 if (!MI.isPredicable())
559559 return false;
560560
561 if (!isEligibleForITBlock(MI))
561 if (!isEligibleForITBlock(&MI))
562562 return false;
563563
564564 ARMFunctionInfo *AFI =
565 MI->getParent()->getParent()->getInfo();
565 MI.getParent()->getParent()->getInfo();
566566
567567 if (AFI->isThumb2Function()) {
568568 if (getSubtarget().restrictIT())
569 return isV8EligibleForIT(MI);
569 return isV8EligibleForIT(&MI);
570570 } else { // non-Thumb
571 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
571 if ((MI.getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
572572 return false;
573573 }
574574
17171717 CmpMI->getOpcode() == ARM::t2CMPri) {
17181718 unsigned Reg = CmpMI->getOperand(0).getReg();
17191719 unsigned PredReg = 0;
1720 ARMCC::CondCodes P = getInstrPredicate(CmpMI, PredReg);
1720 ARMCC::CondCodes P = getInstrPredicate(*CmpMI, PredReg);
17211721 if (P == ARMCC::AL && CmpMI->getOperand(1).getImm() == 0 &&
17221722 isARMLowRegister(Reg))
17231723 return false;
17721772 /// getInstrPredicate - If instruction is predicated, returns its predicate
17731773 /// condition, otherwise returns AL. It also returns the condition code
17741774 /// register by reference.
1775 ARMCC::CondCodes
1776 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1777 int PIdx = MI->findFirstPredOperandIdx();
1775 ARMCC::CondCodes llvm::getInstrPredicate(const MachineInstr &MI,
1776 unsigned &PredReg) {
1777 int PIdx = MI.findFirstPredOperandIdx();
17781778 if (PIdx == -1) {
17791779 PredReg = 0;
17801780 return ARMCC::AL;
17811781 }
17821782
1783 PredReg = MI->getOperand(PIdx+1).getReg();
1784 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1783 PredReg = MI.getOperand(PIdx+1).getReg();
1784 return (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
17851785 }
17861786
17871787
18051805 case ARM::t2MOVCCr: {
18061806 // MOVCC can be commuted by inverting the condition.
18071807 unsigned PredReg = 0;
1808 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1808 ARMCC::CondCodes CC = getInstrPredicate(*MI, PredReg);
18091809 // MOVCC AL can't be inverted. Shouldn't happen.
18101810 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
18111811 return nullptr;
23942394
23952395 // Masked compares sometimes use the same register as the corresponding 'and'.
23962396 if (CmpMask != ~0) {
2397 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2397 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) {
23982398 MI = nullptr;
23992399 for (MachineRegisterInfo::use_instr_iterator
24002400 UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
24022402 if (UI->getParent() != CmpInstr->getParent()) continue;
24032403 MachineInstr *PotentialAND = &*UI;
24042404 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2405 isPredicated(PotentialAND))
2405 isPredicated(*PotentialAND))
24062406 continue;
24072407 MI = PotentialAND;
24082408 break;
24702470 if (!MI) MI = Sub;
24712471
24722472 // We can't use a predicated instruction - it doesn't always write the flags.
2473 if (isPredicated(MI))
2473 if (isPredicated(*MI))
24742474 return false;
24752475
24762476 switch (MI->getOpcode()) {
26172617 // Toggle the optional operand to CPSR.
26182618 MI->getOperand(5).setReg(ARM::CPSR);
26192619 MI->getOperand(5).setIsDef(true);
2620 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2620 assert(!isPredicated(*MI) && "Can't use flags from predicated instruction");
26212621 CmpInstr->eraseFromParent();
26222622
26232623 // Modify the condition code of operands in OperandsToUpdate.
39453945 return Latency;
39463946 }
39473947
3948 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3949 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3950 MI->isRegSequence() || MI->isImplicitDef())
3948 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {
3949 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
3950 MI.isImplicitDef())
39513951 return 0;
39523952
3953 if (MI->isBundle())
3953 if (MI.isBundle())
39543954 return 0;
39553955
3956 const MCInstrDesc &MCID = MI->getDesc();
3956 const MCInstrDesc &MCID = MI.getDesc();
39573957
39583958 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
39593959 // When predicated, CPSR is an additional source operand for CPSR updating
41514151 if (Subtarget.hasNEON()) {
41524152 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
41534153 // if they are not predicated.
4154 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
4154 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(*MI))
41554155 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
41564156
41574157 // CortexA9 is particularly picky about mixing the two and wants these
41584158 // converted.
4159 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
4159 if (Subtarget.isCortexA9() && !isPredicated(*MI) &&
41604160 (MI->getOpcode() == ARM::VMOVRS || MI->getOpcode() == ARM::VMOVSR ||
41614161 MI->getOpcode() == ARM::VMOVS))
41624162 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
42514251 break;
42524252
42534253 // Zap the predicate operands.
4254 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4254 assert(!isPredicated(*MI) && "Cannot predicate a VORRd");
42554255
42564256 // Make sure we've got NEON instructions.
42574257 assert(Subtarget.hasNEON() && "VORRd requires NEON");
42724272 case ARM::VMOVRS:
42734273 if (Domain != ExeNEON)
42744274 break;
4275 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4275 assert(!isPredicated(*MI) && "Cannot predicate a VGETLN");
42764276
42774277 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
42784278 DstReg = MI->getOperand(0).getReg();
42984298 case ARM::VMOVSR: {
42994299 if (Domain != ExeNEON)
43004300 break;
4301 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4301 assert(!isPredicated(*MI) && "Cannot predicate a VSETLN");
43024302
43034303 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
43044304 DstReg = MI->getOperand(0).getReg();
134134 ReverseBranchCondition(SmallVectorImpl &Cond) const override;
135135
136136 // Predication support.
137 bool isPredicated(const MachineInstr *MI) const override;
138
139 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
140 int PIdx = MI->findFirstPredOperandIdx();
141 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
137 bool isPredicated(const MachineInstr &MI) const override;
138
139 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
140 int PIdx = MI.findFirstPredOperandIdx();
141 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
142142 : ARMCC::AL;
143143 }
144144
145 bool PredicateInstruction(MachineInstr *MI,
146 ArrayRef Pred) const override;
145 bool PredicateInstruction(MachineInstr &MI,
146 ArrayRef Pred) const override;
147147
148148 bool SubsumesPredicate(ArrayRef Pred1,
149149 ArrayRef Pred2) const override;
150150
151 bool DefinesPredicate(MachineInstr *MI,
151 bool DefinesPredicate(MachineInstr &MI,
152152 std::vector &Pred) const override;
153153
154 bool isPredicable(MachineInstr *MI) const override;
154 bool isPredicable(MachineInstr &MI) const override;
155155
156156 /// GetInstSize - Returns the size of the specified MachineInstr.
157157 ///
326326 const MCInstrDesc &UseMCID,
327327 unsigned UseIdx, unsigned UseAlign) const;
328328
329 unsigned getPredicationCost(const MachineInstr *MI) const override;
329 unsigned getPredicationCost(const MachineInstr &MI) const override;
330330
331331 unsigned getInstrLatency(const InstrItineraryData *ItinData,
332332 const MachineInstr *MI,
446446 /// getInstrPredicate - If instruction is predicated, returns its predicate
447447 /// condition, otherwise returns AL. It also returns the condition code
448448 /// register by reference.
449 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
449 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
450450
451451 unsigned getMatchingCondBranchOpcode(unsigned Opc);
452452
14621462 // Avoid splitting an IT block.
14631463 if (LastIT) {
14641464 unsigned PredReg = 0;
1465 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
1465 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
14661466 if (CC != ARMCC::AL)
14671467 MI = LastIT;
14681468 }
14691469
14701470 // We really must not split an IT block.
14711471 DEBUG(unsigned PredReg;
1472 assert(!isThumb || getITInstrPredicate(MI, PredReg) == ARMCC::AL));
1472 assert(!isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL));
14731473
14741474 NewMBB = splitBlockBeforeInstr(MI);
14751475 }
19151915
19161916 NewOpc = 0;
19171917 unsigned PredReg = 0;
1918 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg);
1918 ARMCC::CondCodes Pred = getInstrPredicate(*Br.MI, PredReg);
19191919 if (Pred == ARMCC::EQ)
19201920 NewOpc = ARM::tCBZ;
19211921 else if (Pred == ARMCC::NE)
19331933 --CmpMI;
19341934 if (CmpMI->getOpcode() == ARM::tCMPi8) {
19351935 unsigned Reg = CmpMI->getOperand(0).getReg();
1936 Pred = getInstrPredicate(CmpMI, PredReg);
1936 Pred = getInstrPredicate(*CmpMI, PredReg);
19371937 if (Pred == ARMCC::AL &&
19381938 CmpMI->getOperand(1).getImm() == 0 &&
19391939 isARMLowRegister(Reg)) {
650650 MachineInstr &MI = *MBBI;
651651 unsigned Opcode = MI.getOpcode();
652652 unsigned PredReg = 0;
653 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
653 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
654654 unsigned DstReg = MI.getOperand(0).getReg();
655655 bool DstIsDead = MI.getOperand(0).isDead();
656656 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
839839 unsigned Base = getLoadStoreBaseOp(*First).getReg();
840840 bool BaseKill = LatestMI->killsRegister(Base);
841841 unsigned PredReg = 0;
842 ARMCC::CondCodes Pred = getInstrPredicate(First, PredReg);
842 ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);
843843 DebugLoc DL = First->getDebugLoc();
844844 MachineInstr *Merged = nullptr;
845845 if (Cand.CanMergeToLSDouble)
11011101 unsigned MIPredReg;
11021102 if (MI.getOperand(0).getReg() != Reg ||
11031103 MI.getOperand(1).getReg() != Reg ||
1104 getInstrPredicate(&MI, MIPredReg) != Pred ||
1104 getInstrPredicate(MI, MIPredReg) != Pred ||
11051105 MIPredReg != PredReg)
11061106 return 0;
11071107
11681168 unsigned Base = BaseOP.getReg();
11691169 bool BaseKill = BaseOP.isKill();
11701170 unsigned PredReg = 0;
1171 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
1171 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
11721172 unsigned Opcode = MI->getOpcode();
11731173 DebugLoc DL = MI->getDebugLoc();
11741174
12901290 return false;
12911291
12921292 unsigned PredReg = 0;
1293 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
1293 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
12941294 int Bytes = getLSMultipleTransferSize(MI);
12951295 MachineBasicBlock &MBB = *MI->getParent();
12961296 MachineBasicBlock::iterator MBBI(MI);
13871387 return false;
13881388
13891389 unsigned PredReg;
1390 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
1390 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
13911391 MachineBasicBlock::iterator MBBI(MI);
13921392 MachineBasicBlock &MBB = *MI.getParent();
13931393 int Offset;
15481548 bool OffUndef = isT2 ? false : MI->getOperand(3).isUndef();
15491549 int OffImm = getMemoryOpOffset(MI);
15501550 unsigned PredReg = 0;
1551 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
1551 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
15521552
15531553 if (OddRegNum > EvenRegNum && OffImm == 0) {
15541554 // Ascending register numbers and no offset. It's safe to change it to a
16541654 unsigned Reg = MO.getReg();
16551655 unsigned Base = getLoadStoreBaseOp(*MBBI).getReg();
16561656 unsigned PredReg = 0;
1657 ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
1657 ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg);
16581658 int Offset = getMemoryOpOffset(MBBI);
16591659 if (CurrBase == 0) {
16601660 // Start of a new chain.
20552055 if (FirstReg == SecondReg)
20562056 return false;
20572057 BaseReg = Op0->getOperand(1).getReg();
2058 Pred = getInstrPredicate(Op0, PredReg);
2058 Pred = getInstrPredicate(*Op0, PredReg);
20592059 dl = Op0->getDebugLoc();
20602060 return true;
20612061 }
22492249 if (!isMemoryOp(*MI))
22502250 continue;
22512251 unsigned PredReg = 0;
2252 if (getInstrPredicate(MI, PredReg) != ARMCC::AL)
2252 if (getInstrPredicate(*MI, PredReg) != ARMCC::AL)
22532253 continue;
22542254
22552255 int Opc = MI->getOpcode();
9393 (void)TII;
9494 }]>;
9595
96 def IsPredicatedPred : SchedPredicate<[{TII->isPredicated(MI)}]>;
96 def IsPredicatedPred : SchedPredicate<[{TII->isPredicated(*MI)}]>;
9797
9898 //===----------------------------------------------------------------------===//
9999 // Instruction Itinerary classes used for ARM
164164 ++I;
165165 if (I != E) {
166166 unsigned NPredReg = 0;
167 ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg);
167 ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg);
168168 if (NCC == CC || NCC == OCC)
169169 return true;
170170 }
181181 MachineInstr *MI = &*MBBI;
182182 DebugLoc dl = MI->getDebugLoc();
183183 unsigned PredReg = 0;
184 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
184 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
185185 if (CC == ARMCC::AL) {
186186 ++MBBI;
187187 continue;
221221 MI = NMI;
222222
223223 unsigned NPredReg = 0;
224 ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg);
224 ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg);
225225 if (NCC == CC || NCC == OCC) {
226226 Mask |= (NCC & 1) << Pos;
227227 // Add implicit use of ITSTATE.
5757 // If the first instruction of Tail is predicated, we may have to update
5858 // the IT instruction.
5959 unsigned PredReg = 0;
60 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
60 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg);
6161 MachineBasicBlock::iterator MBBI = Tail;
6262 if (CC != ARMCC::AL)
6363 // Expecting at least the t2IT instruction before it.
105105 }
106106
107107 unsigned PredReg = 0;
108 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
108 return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL;
109109 }
110110
111111 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
458458 Offset += MI.getOperand(FrameRegIdx+1).getImm();
459459
460460 unsigned PredReg;
461 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
461 if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL) {
462462 // Turn it into a move.
463463 MI.setDesc(TII.get(ARM::tMOVr));
464464 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
626626 return Offset == 0;
627627 }
628628
629 ARMCC::CondCodes
630 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
631 unsigned Opc = MI->getOpcode();
629 ARMCC::CondCodes llvm::getITInstrPredicate(const MachineInstr &MI,
630 unsigned &PredReg) {
631 unsigned Opc = MI.getOpcode();
632632 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
633633 return ARMCC::AL;
634634 return getInstrPredicate(MI, PredReg);
6969 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
7070 /// to llvm::getInstrPredicate except it returns AL for conditional branch
7171 /// instructions which are "predicated", but are not in IT blocks.
72 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
73
74
72 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
7573 }
7674
7775 #endif
596596 case ARM::t2ADDSri:
597597 case ARM::t2ADDSrr: {
598598 unsigned PredReg = 0;
599 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
599 if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) {
600600 switch (Opc) {
601601 default: break;
602602 case ARM::t2ADDSri: {
701701 // Check if it's possible / necessary to transfer the predicate.
702702 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2);
703703 unsigned PredReg = 0;
704 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
704 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
705705 bool SkipPred = false;
706706 if (Pred != ARMCC::AL) {
707707 if (!NewMCID.isPredicable())
797797 // Check if it's possible / necessary to transfer the predicate.
798798 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1);
799799 unsigned PredReg = 0;
800 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
800 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
801801 bool SkipPred = false;
802802 if (Pred != ARMCC::AL) {
803803 if (!NewMCID.isPredicable())
8989
9090 // Working from the bottom, when we see a non-terminator
9191 // instruction, we're done.
92 if (!isUnpredicatedTerminator(I))
92 if (!isUnpredicatedTerminator(*I))
9393 break;
9494
9595 // A terminator that isn't a branch can't easily be handled
936936
937937 bool HexagonEvaluator::evaluateLoad(const MachineInstr *MI,
938938 const CellMapType &Inputs, CellMapType &Outputs) const {
939 if (TII.isPredicated(MI))
939 if (TII.isPredicated(*MI))
940940 return false;
941941 assert(MI->mayLoad() && "A load that mayn't?");
942942 unsigned Opc = MI->getOpcode();
444444 }
445445 MachineInstr *Def1 = MRI->getVRegDef(RO1.getReg());
446446 MachineInstr *Def3 = MRI->getVRegDef(RO3.getReg());
447 if (!TII->isPredicable(Def1) || !TII->isPredicable(Def3))
447 if (!TII->isPredicable(*Def1) || !TII->isPredicable(*Def3))
448448 Cost++;
449449 }
450450 return Cost;
420420 DEBUG(dbgs() << "adding liveness info for instr\n " << MX << " " << *MI);
421421
422422 MX = MX.getRegSlot();
423 bool Predicated = HII->isPredicated(MI);
423 bool Predicated = HII->isPredicated(*MI);
424424 MachineBasicBlock *MB = MI->getParent();
425425
426426 // Strip all implicit uses from predicated instructions. They will be
747747
748748
749749 bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) {
750 if (HII->isPredicated(MI) || !HII->isPredicable(MI))
750 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI))
751751 return false;
752752 if (MI->hasUnmodeledSideEffects() || MI->mayStore())
753753 return false;
783783 MachineInstr *MI = &*I;
784784 // Check if this instruction can be ignored, i.e. if it is predicated
785785 // on the complementary condition.
786 if (PredValid && HII->isPredicated(MI)) {
787 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(MI)))
786 if (PredValid && HII->isPredicated(*MI)) {
787 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI)))
788788 continue;
789789 }
790790
944944 MachineInstr *MI = &*I;
945945 // Do not touch instructions that are not predicated, or are predicated
946946 // on the opposite condition.
947 if (!HII->isPredicated(MI))
948 continue;
949 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(MI)))
947 if (!HII->isPredicated(*MI))
948 continue;
949 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI)))
950950 continue;
951951
952952 for (auto &Op : MI->operands()) {
10131013 // By default assume that the instruction executes on the same condition
10141014 // as TfrI (Exec_Then), and also on the opposite one (Exec_Else).
10151015 unsigned Exec = Exec_Then | Exec_Else;
1016 if (PredValid && HII->isPredicated(MI) && MI->readsRegister(PredR))
1017 Exec = (Cond == HII->isPredicatedTrue(MI)) ? Exec_Then : Exec_Else;
1016 if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR))
1017 Exec = (Cond == HII->isPredicatedTrue(*MI)) ? Exec_Then : Exec_Else;
10181018
10191019 for (auto &Op : MI->operands()) {
10201020 if (!Op.isReg())
11181118
11191119
11201120 void HexagonExpandCondsets::removeImplicitUses(MachineBasicBlock &B) {
1121 for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) {
1122 MachineInstr *MI = &*I;
1121 for (MachineInstr &MI : B)
11231122 if (HII->isPredicated(MI))
1124 removeImplicitUses(MI);
1125 }
1123 removeImplicitUses(&MI);
11261124 }
11271125
11281126
12891287 if (S1.isReg()) {
12901288 RegisterRef RS = S1;
12911289 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, true);
1292 if (!RDef || !HII->isPredicable(RDef))
1290 if (!RDef || !HII->isPredicable(*RDef))
12931291 Done = coalesceRegisters(RD, RegisterRef(S1));
12941292 }
12951293 if (!Done && S2.isReg()) {
12961294 RegisterRef RS = S2;
12971295 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, false);
1298 if (!RDef || !HII->isPredicable(RDef))
1296 if (!RDef || !HII->isPredicable(*RDef))
12991297 Done = coalesceRegisters(RD, RegisterRef(S2));
13001298 }
13011299 Changed |= Done;
17711771
17721772 for (auto &In : B) {
17731773 int LFI, SFI;
1774 bool Load = HII.isLoadFromStackSlot(&In, LFI) && !HII.isPredicated(&In);
1775 bool Store = HII.isStoreToStackSlot(&In, SFI) && !HII.isPredicated(&In);
1774 bool Load = HII.isLoadFromStackSlot(&In, LFI) && !HII.isPredicated(In);
1775 bool Store = HII.isStoreToStackSlot(&In, SFI) && !HII.isPredicated(In);
17761776 if (Load && Store) {
17771777 // If it's both a load and a store, then we won't handle it.
17781778 BadFIs.insert(LFI);
423423 return false;
424424 --I;
425425 }
426 if (!isUnpredicatedTerminator(&*I))
426 if (!isUnpredicatedTerminator(*I))
427427 return false;
428428
429429 // Get the last instruction in the block.
431431 MachineInstr *SecondLastInst = nullptr;
432432 // Find one more terminator if present.
433433 for (;;) {
434 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(&*I)) {
434 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
435435 if (!SecondLastInst)
436436 SecondLastInst = &*I;
437437 else
584584 MachineBasicBlock *NewTBB, *NewFBB;
585585 SmallVector Cond;
586586 MachineInstr *Term = MBB.getFirstTerminator();
587 if (Term != MBB.end() && isPredicated(Term) &&
587 if (Term != MBB.end() && isPredicated(*Term) &&
588588 !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, false)) {
589589 MachineBasicBlock *NextBB = &*++MBB.getIterator();
590590 if (NewTBB == NextBB) {
12101210 // if (!p0.new) R1 = add(R2, R3)
12111211 // Note: New-value stores are not included here as in the current
12121212 // implementation, we don't need to check their predicate sense.
1213 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
1214 const uint64_t F = MI->getDesc().TSFlags;
1213 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {
1214 const uint64_t F = MI.getDesc().TSFlags;
12151215 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
12161216 }
12171217
1218
1219 bool HexagonInstrInfo::PredicateInstruction(MachineInstr *MI,
1220 ArrayRef Cond) const {
1218 bool HexagonInstrInfo::PredicateInstruction(
1219 MachineInstr &MI, ArrayRef Cond) const {
12211220 if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
12221221 isEndLoopN(Cond[0].getImm())) {
1223 DEBUG(dbgs() << "\nCannot predicate:"; MI->dump(););
1224 return false;
1225 }
1226 int Opc = MI->getOpcode();
1222 DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1223 return false;
1224 }
1225 int Opc = MI.getOpcode();
12271226 assert (isPredicable(MI) && "Expected predicable instruction");
12281227 bool invertJump = predOpcodeHasNot(Cond);
12291228
12321231 // plicated manipulations with the operands (handling tied operands,
12331232 // etc.), build a new temporary instruction, then overwrite MI with it.
12341233
1235 MachineBasicBlock &B = *MI->getParent();
1236 DebugLoc DL = MI->getDebugLoc();
1234 MachineBasicBlock &B = *MI.getParent();
1235 DebugLoc DL = MI.getDebugLoc();
12371236 unsigned PredOpc = getCondOpcode(Opc, invertJump);
12381237 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1239 unsigned NOp = 0, NumOps = MI->getNumOperands();
1238 unsigned NOp = 0, NumOps = MI.getNumOperands();
12401239 while (NOp < NumOps) {
1241 MachineOperand &Op = MI->getOperand(NOp);
1240 MachineOperand &Op = MI.getOperand(NOp);
12421241 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
12431242 break;
12441243 T.addOperand(Op);
12511250 assert(GotPredReg);
12521251 T.addReg(PredReg, PredRegFlags);
12531252 while (NOp < NumOps)
1254 T.addOperand(MI->getOperand(NOp++));
1255
1256 MI->setDesc(get(PredOpc));
1257 while (unsigned n = MI->getNumOperands())
1258 MI->RemoveOperand(n-1);
1253 T.addOperand(MI.getOperand(NOp++));
1254
1255 MI.setDesc(get(PredOpc));
1256 while (unsigned n = MI.getNumOperands())
1257 MI.RemoveOperand(n-1);
12591258 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1260 MI->addOperand(T->getOperand(i));
1259 MI.addOperand(T->getOperand(i));
12611260
12621261 MachineBasicBlock::instr_iterator TI = T->getIterator();
12631262 B.erase(TI);
12741273 return false;
12751274 }
12761275
1277
1278 bool HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1279 std::vector &Pred) const {
1276 bool HexagonInstrInfo::DefinesPredicate(
1277 MachineInstr &MI, std::vector &Pred) const {
12801278 auto &HRI = getRegisterInfo();
1281 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1282 MachineOperand MO = MI->getOperand(oper);
1279 for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1280 MachineOperand MO = MI.getOperand(oper);
12831281 if (MO.isReg() && MO.isDef()) {
12841282 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
12851283 if (RC == &Hexagon::PredRegsRegClass) {
12911289 return false;
12921290 }
12931291
1294 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
1295 bool isPred = MI->getDesc().isPredicable();
1292 bool HexagonInstrInfo::isPredicable(MachineInstr &MI) const {
1293 bool isPred = MI.getDesc().isPredicable();
12961294
12971295 if (!isPred)
12981296 return false;
12991297
1300 const int Opc = MI->getOpcode();
1301 int NumOperands = MI->getNumOperands();
1298 const int Opc = MI.getOpcode();
1299 int NumOperands = MI.getNumOperands();
13021300
13031301 // Keep a flag for upto 4 operands in the instructions, to indicate if
13041302 // that operand has been constant extended.
13071305 NumOperands = 4;
13081306
13091307 for (int i = 0; i < NumOperands; i++)
1310 OpCExtended[i] = (isOperandExtended(MI, i) && isConstExtended(MI));
1308 OpCExtended[i] = (isOperandExtended(&MI, i) && isConstExtended(&MI));
13111309
13121310 switch(Opc) {
13131311 case Hexagon::A2_tfrsi:
1314 return (isOperandExtended(MI, 1) && isConstExtended(MI)) ||
1315 isInt<12>(MI->getOperand(1).getImm());
1312 return (isOperandExtended(&MI, 1) && isConstExtended(&MI)) ||
1313 isInt<12>(MI.getOperand(1).getImm());
13161314
13171315 case Hexagon::S2_storerd_io:
1318 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
1316 return isShiftedUInt<6,3>(MI.getOperand(1).getImm());
13191317
13201318 case Hexagon::S2_storeri_io:
13211319 case Hexagon::S2_storerinew_io:
1322 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
1320 return isShiftedUInt<6,2>(MI.getOperand(1).getImm());
13231321
13241322 case Hexagon::S2_storerh_io:
13251323 case Hexagon::S2_storerhnew_io:
1326 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
1324 return isShiftedUInt<6,1>(MI.getOperand(1).getImm());
13271325
13281326 case Hexagon::S2_storerb_io:
13291327 case Hexagon::S2_storerbnew_io:
1330 return isUInt<6>(MI->getOperand(1).getImm());
1328 return isUInt<6>(MI.getOperand(1).getImm());
13311329
13321330 case Hexagon::L2_loadrd_io:
1333 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
1331 return isShiftedUInt<6,3>(MI.getOperand(2).getImm());
13341332
13351333 case Hexagon::L2_loadri_io:
1336 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
1334 return isShiftedUInt<6,2>(MI.getOperand(2).getImm());
13371335
13381336 case Hexagon::L2_loadrh_io:
13391337 case Hexagon::L2_loadruh_io:
1340 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
1338 return isShiftedUInt<6,1>(MI.getOperand(2).getImm());
13411339
13421340 case Hexagon::L2_loadrb_io:
13431341 case Hexagon::L2_loadrub_io:
1344 return isUInt<6>(MI->getOperand(2).getImm());
1342 return isUInt<6>(MI.getOperand(2).getImm());
13451343
13461344 case Hexagon::L2_loadrd_pi:
1347 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
1345 return isShiftedInt<4,3>(MI.getOperand(3).getImm());
13481346
13491347 case Hexagon::L2_loadri_pi:
1350 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
1348 return isShiftedInt<4,2>(MI.getOperand(3).getImm());
13511349
13521350 case Hexagon::L2_loadrh_pi:
13531351 case Hexagon::L2_loadruh_pi:
1354 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
1352 return isShiftedInt<4,1>(MI.getOperand(3).getImm());
13551353
13561354 case Hexagon::L2_loadrb_pi:
13571355 case Hexagon::L2_loadrub_pi:
1358 return isInt<4>(MI->getOperand(3).getImm());
1356 return isInt<4>(MI.getOperand(3).getImm());
13591357
13601358 case Hexagon::S4_storeirb_io:
13611359 case Hexagon::S4_storeirh_io:
13621360 case Hexagon::S4_storeiri_io:
1363 return (OpCExtended[1] || isUInt<6>(MI->getOperand(1).getImm())) &&
1364 (OpCExtended[2] || isInt<6>(MI->getOperand(2).getImm()));
1361 return (OpCExtended[1] || isUInt<6>(MI.getOperand(1).getImm())) &&
1362 (OpCExtended[2] || isInt<6>(MI.getOperand(2).getImm()));
13651363
13661364 case Hexagon::A2_addi:
1367 return isInt<8>(MI->getOperand(2).getImm());
1365 return isInt<8>(MI.getOperand(2).getImm());
13681366
13691367 case Hexagon::A2_aslh:
13701368 case Hexagon::A2_asrh:
16611659
16621660
16631661 bool HexagonInstrInfo::isCondInst(const MachineInstr *MI) const {
1664 return (MI->isBranch() && isPredicated(MI)) ||
1662 return (MI->isBranch() && isPredicated(*MI)) ||
16651663 isConditionalTransfer(MI) ||
16661664 isConditionalALU32(MI) ||
16671665 isConditionalLoad(MI) ||
16681666 // Predicated stores which don't have a .new on any operands.
1669 (MI->mayStore() && isPredicated(MI) && !isNewValueStore(MI) &&
1670 !isPredicatedNew(MI));
1667 (MI->mayStore() && isPredicated(*MI) && !isNewValueStore(MI) &&
1668 !isPredicatedNew(*MI));
16711669 }
16721670
16731671
17321730 // FIXME - Function name and it's functionality don't match.
17331731 // It should be renamed to hasPredNewOpcode()
17341732 bool HexagonInstrInfo::isConditionalLoad(const MachineInstr* MI) const {
1735 if (!MI->getDesc().mayLoad() || !isPredicated(MI))
1733 if (!MI->getDesc().mayLoad() || !isPredicated(*MI))
17361734 return false;
17371735
17381736 int PNewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
19381936 // Returns true, if any one of the operands is a dot new
19391937 // insn, whether it is predicated dot new or register dot new.
19401938 bool HexagonInstrInfo::isDotNewInst(const MachineInstr* MI) const {
1941 if (isNewValueInst(MI) ||
1942 (isPredicated(MI) && isPredicatedNew(MI)))
1939 if (isNewValueInst(MI) || (isPredicated(*MI) && isPredicatedNew(*MI)))
19431940 return true;
19441941
19451942 return false;
23042301 }
23052302
23062303
2307 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
2308 const uint64_t F = MI->getDesc().TSFlags;
2304 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {
2305 const uint64_t F = MI.getDesc().TSFlags;
23092306 assert(isPredicated(MI));
23102307 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
23112308 }
23182315 }
23192316
23202317
2321 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
2322 const uint64_t F = MI->getDesc().TSFlags;
2318 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {
2319 const uint64_t F = MI.getDesc().TSFlags;
23232320 return !((F >> HexagonII::PredicatedFalsePos) &
23242321 HexagonII::PredicatedFalseMask);
23252322 }
30833080 } else
30843081 return false;
30853082
3086 if (isPredicated(MI)) {
3083 if (isPredicated(*MI)) {
30873084 BasePos++;
30883085 OffsetPos++;
30893086 }
31373134 return Jumpers;
31383135 --I;
31393136 }
3140 if (!isUnpredicatedTerminator(&*I))
3137 if (!isUnpredicatedTerminator(*I))
31413138 return Jumpers;
31423139
31433140 // Get the last instruction in the block.
31463143 MachineInstr *SecondLastInst = nullptr;
31473144 // Find one more terminator if present.
31483145 do {
3149 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(&*I)) {
3146 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
31503147 if (!SecondLastInst) {
31513148 SecondLastInst = &*I;
31523149 Jumpers.push_back(SecondLastInst);
41054102 --TargetPos;
41064103 assert((TargetPos >= 0) && MI->getOperand(TargetPos).isMBB());
41074104 MI->getOperand(TargetPos).setMBB(NewTarget);
4108 if (EnableBranchPrediction && isPredicatedNew(MI)) {
4105 if (EnableBranchPrediction && isPredicatedNew(*MI)) {
41094106 NewOpcode = reversePrediction(NewOpcode);
41104107 }
41114108 MI->setDesc(get(NewOpcode));
182182 MachineBasicBlock::iterator MI) const override;
183183
184184 /// Returns true if the instruction is already predicated.
185 bool isPredicated(const MachineInstr *MI) const override;
185 bool isPredicated(const MachineInstr &MI) const override;
186186
187187 /// Convert the instruction into a predicated instruction.
188188 /// It returns true if the operation was successful.
189 bool PredicateInstruction(MachineInstr *MI,
189 bool PredicateInstruction(MachineInstr &MI,
190190 ArrayRef Cond) const override;
191191
192192 /// Returns true if the first specified predicate
197197 /// If the specified instruction defines any predicate
198198 /// or condition code register(s) used for predication, returns true as well
199199 /// as the definition predicate(s) by reference.
200 bool DefinesPredicate(MachineInstr *MI,
200 bool DefinesPredicate(MachineInstr &MI,
201201 std::vector &Pred) const override;
202202
203203 /// Return true if the specified instruction can be predicated.
204204 /// By default, this returns true for every instruction with a
205205 /// PredicateOperand.
206 bool isPredicable(MachineInstr *MI) const override;
206 bool isPredicable(MachineInstr &MI) const override;
207207
208208 /// Test if the given instruction should be considered a scheduling boundary.
209209 /// This primarily includes labels and terminators.
300300 bool isNewValueStore(unsigned Opcode) const;
301301 bool isOperandExtended(const MachineInstr *MI, unsigned OperandNum) const;
302302 bool isPostIncrement(const MachineInstr* MI) const;
303 bool isPredicatedNew(const MachineInstr *MI) const;
303 bool isPredicatedNew(const MachineInstr &MI) const;
304304 bool isPredicatedNew(unsigned Opcode) const;
305 bool isPredicatedTrue(const MachineInstr *MI) const;
305 bool isPredicatedTrue(const MachineInstr &MI) const;
306306 bool isPredicatedTrue(unsigned Opcode) const;
307307 bool isPredicated(unsigned Opcode) const;
308308 bool isPredicateLate(unsigned Opcode) const;
115115 MachineFunction &MF) {
116116
117117 // Predicated instruction can not be feeder to NVJ.
118 if (QII->isPredicated(II))
118 if (QII->isPredicated(*II))
119119 return false;
120120
121121 // Bail out if feederReg is a paired register (double regs in
242242 // Look for Predicated instructions.
243243 if (!DisablePNotP) {
244244 bool Done = false;
245 if (QII->isPredicated(MI)) {
245 if (QII->isPredicated(*MI)) {
246246 MachineOperand &Op0 = MI->getOperand(0);
247247 unsigned Reg0 = Op0.getReg();
248248 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
435435
436436 /// Returns true if an instruction is predicated on p0 and false if it's
437437 /// predicated on !p0.
438 static PredicateKind getPredicateSense(const MachineInstr *MI,
438 static PredicateKind getPredicateSense(const MachineInstr &MI,
439439 const HexagonInstrInfo *HII) {
440440 if (!HII->isPredicated(MI))
441441 return PK_Unknown;
569569
570570 // If the source that feeds the store is predicated, new value store must
571571 // also be predicated.
572 if (HII->isPredicated(PacketMI)) {
573 if (!HII->isPredicated(MI))
572 if (HII->isPredicated(*PacketMI)) {
573 if (!HII->isPredicated(*MI))
574574 return false;
575575
576576 // Check to make sure that they both will have their predicates
612612 // 3) Both new-value register producer and user should have same predicate
613613 // sense, i.e, either both should be negated or both should be non-negated.
614614 if (predRegNumDst != predRegNumSrc ||
615 HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
616 getPredicateSense(MI, HII) != getPredicateSense(PacketMI, HII))
615 HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
616 getPredicateSense(*MI, HII) != getPredicateSense(*PacketMI, HII))
617617 return false;
618618 }
619619
792792
793793 for (auto I : CurrentPacketMIs) {
794794 // We only care for dependencies to predicated instructions
795 if (!HII->isPredicated(I))
795 if (!HII->isPredicated(*I))
796796 continue;
797797
798798 // Scheduling Unit for current insn in the packet
816816
817817
818818 /// Gets the predicate register of a predicated instruction.
819 static unsigned getPredicatedRegister(MachineInstr *MI,
819 static unsigned getPredicatedRegister(MachineInstr &MI,
820820 const HexagonInstrInfo *QII) {
821821 /// We use the following rule: The first predicate register that is a use is
822822 /// the predicate register of a predicated instruction.
823823 assert(QII->isPredicated(MI) && "Must be predicated instruction");
824824
825 for (auto &Op : MI->operands()) {
825 for (auto &Op : MI.operands()) {
826826 if (Op.isReg() && Op.getReg() && Op.isUse() &&
827827 Hexagon::PredRegsRegClass.contains(Op.getReg()))
828828 return Op.getReg();
834834
835835 // Given two predicated instructions, this function detects whether
836836 // the predicates are complements.
837 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr *MI1,
838 MachineInstr *MI2) {
837 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1,
838 MachineInstr &MI2) {
839839 // If we don't know the predicate sense of the instructions bail out early, we
840840 // need it later.
841841 if (getPredicateSense(MI1, HII) == PK_Unknown ||
843843 return false;
844844
845845 // Scheduling unit for candidate.
846 SUnit *SU = MIToSUnit[MI1];
846 SUnit *SU = MIToSUnit[&MI1];
847847
848848 // One corner case deals with the following scenario:
849849 // Trying to add
897897 Hexagon::PredRegsRegClass.contains(PReg1) &&
898898 Hexagon::PredRegsRegClass.contains(PReg2) &&
899899 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
900 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);
900 HII->isDotNewInst(&MI1) == HII->isDotNewInst(&MI2);
901901 }
902902
903903 // Initialize packetizer flags.
10441044 // defining the same (dead) register.
10451045 if (I->isCall() || J->isCall())
10461046 return false;
1047 if (HII->isPredicated(I) || HII->isPredicated(J))
1047 if (HII->isPredicated(*I) || HII->isPredicated(*J))
10481048 return false;
10491049
10501050 BitVector DeadDefs(Hexagon::NUM_TARGET_REGS);
10841084 auto isBadForLoopN = [this] (const MachineInstr *MI) -> bool {
10851085 if (MI->isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
10861086 return true;
1087 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
1087 if (HII->isPredicated(*MI) && HII->isPredicatedNew(*MI) && HII->isJumpR(MI))
10881088 return true;
10891089 return false;
10901090 };
12741274
12751275 // For predicated instructions, if the predicates are complements then
12761276 // there can be no dependence.
1277 if (HII->isPredicated(I) && HII->isPredicated(J) &&
1278 arePredicatesComplements(I, J)) {
1277 if (HII->isPredicated(*I) && HII->isPredicated(*J) &&
1278 arePredicatesComplements(*I, *J)) {
12791279 // Not always safe to do this translation.
12801280 // DAG Builder attempts to reduce dependence edges using transitive
12811281 // nature of dependencies. Here is an example:
9292 bool canPromoteToNewValueStore(const MachineInstr* MI,
9393 const MachineInstr* PacketMI, unsigned DepReg);
9494 bool demoteToDotOld(MachineInstr* MI);
95 bool arePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2);
95 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
9696 bool restrictingDepExistInPacket(MachineInstr*, unsigned);
9797 bool isNewifiable(const MachineInstr *MI);
9898 bool isCurifiable(MachineInstr* MI);
673673 // unchanged across this def.
674674 bool TargetOperandInfo::isPreserving(const MachineInstr &In, unsigned OpNum)
675675 const {
676 return TII.isPredicated(&In);
676 return TII.isPredicated(In);
677677 }
678678
679679 // Check if the definition of RR produces an unspecified value.
11781178 ImpUses.insert({R, 0});
11791179
11801180 bool IsCall = In.isCall(), IsReturn = In.isReturn();
1181 bool IsPredicated = TII.isPredicated(&In);
1181 bool IsPredicated = TII.isPredicated(In);
11821182 unsigned NumOps = In.getNumOperands();
11831183
11841184 // Avoid duplicate implicit defs. This will not detect cases of implicit
155155 return false;
156156 }
157157
158 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
159 if (!MI->isTerminator()) return false;
158 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
159 if (!MI.isTerminator())
160 return false;
160161
161162 // Conditional branch is a special case.
162 if (MI->isBranch() && !MI->isBarrier())
163 if (MI.isBranch() && !MI.isBarrier())
163164 return true;
164 if (!MI->isPredicable())
165 if (!MI.isPredicable())
165166 return true;
166167 return !isPredicated(MI);
167168 }
181182
182183 // Working from the bottom, when we see a non-terminator
183184 // instruction, we're done.
184 if (!isUnpredicatedTerminator(I))
185 if (!isUnpredicatedTerminator(*I))
185186 break;
186187
187188 // A terminator that isn't a branch can't easily be handled
7373 // Branch folding goodness
7474 bool
7575 ReverseBranchCondition(SmallVectorImpl &Cond) const override;
76 bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
76 bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
7777 bool AnalyzeBranch(MachineBasicBlock &MBB,
7878 MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
7979 SmallVectorImpl &Cond,
183183 while (I != REnd && I->isDebugValue())
184184 ++I;
185185
186 if (I == REnd || !isUnpredicatedTerminator(&*I)) {
186 if (I == REnd || !isUnpredicatedTerminator(*I)) {
187187 // This block ends with no branches (it just falls through to its succ).
188188 // Leave TBB/FBB null.
189189 TBB = FBB = nullptr;
207207 SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
208208
209209 // Not an analyzable branch (must be an indirect jump).
210 if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
210 if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
211211 return BT_None;
212212 }
213213
226226
227227 // If we reached here, there are two branches.
228228 // If there are three terminators, we don't know what sort of block this is.
229 if (++I != REnd && isUnpredicatedTerminator(&*I))
229 if (++I != REnd && isUnpredicatedTerminator(*I))
230230 return BT_None;
231231
232232 BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
149149 SmallVectorImpl &Cond, bool AllowModify) const {
150150 // If the block has no terminators, it just falls into the block after it.
151151 MachineBasicBlock::iterator I = MBB.end();
152 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
152 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I))
153153 return false;
154154
155155 // Get the last instruction in the block.
156156 MachineInstr *LastInst = I;
157157
158158 // If there is only one terminator instruction, process it.
159 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
159 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
160160 if (LastInst->getOpcode() == NVPTX::GOTO) {
161161 TBB = LastInst->getOperand(0).getMBB();
162162 return false;
174174 MachineInstr *SecondLastInst = I;
175175
176176 // If there are three terminators, we don't know what sort of block this is.
177 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
177 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
178178 return true;
179179
180180 // If the block ends with NVPTX::GOTO and NVPTX:CBranch, handle it.
452452 if (I == MBB.end())
453453 return false;
454454
455 if (!isUnpredicatedTerminator(I))
455 if (!isUnpredicatedTerminator(*I))
456456 return false;
457457
458458 // Get the last instruction in the block.
459459 MachineInstr *LastInst = I;
460460
461461 // If there is only one terminator instruction, process it.
462 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
462 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
463463 if (LastInst->getOpcode() == PPC::B) {
464464 if (!LastInst->getOperand(0).isMBB())
465465 return true;
521521 MachineInstr *SecondLastInst = I;
522522
523523 // If there are three terminators, we don't know what sort of block this is.
524 if (SecondLastInst && I != MBB.begin() &&
525 isUnpredicatedTerminator(--I))
524 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
526525 return true;
527526
528527 // If the block ends with PPC::B and PPC:BCC, handle it.
12981297 }
12991298
13001299
1301 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
1300 bool PPCInstrInfo::isPredicated(const MachineInstr &MI) const {
13021301 // The predicated branches are identified by their type, not really by the
13031302 // explicit presence of a predicate. Furthermore, some of them can be
13041303 // predicated more than once. Because if conversion won't try to predicate
13091308 return false;
13101309 }
13111310
1312 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1313 if (!MI->isTerminator())
1311 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
1312 if (!MI.isTerminator())
13141313 return false;
13151314
13161315 // Conditional branch is a special case.
1317 if (MI->isBranch() && !MI->isBarrier())
1316 if (MI.isBranch() && !MI.isBarrier())
13181317 return true;
13191318
13201319 return !isPredicated(MI);
13211320 }
13221321
1323 bool PPCInstrInfo::PredicateInstruction(MachineInstr *MI,
1322 bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI,
13241323 ArrayRef Pred) const {
1325 unsigned OpC = MI->getOpcode();
1324 unsigned OpC = MI.getOpcode();
13261325 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
13271326 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
13281327 bool isPPC64 = Subtarget.isPPC64();
1329 MI->setDesc(get(Pred[0].getImm() ?
1330 (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
1331 (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1328 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1329 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
13321330 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1333 MI->setDesc(get(PPC::BCLR));
1334 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1335 .addReg(Pred[1].getReg());
1331 MI.setDesc(get(PPC::BCLR));
1332 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1333 .addReg(Pred[1].getReg());
13361334 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1337 MI->setDesc(get(PPC::BCLRn));
1338 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1339 .addReg(Pred[1].getReg());
1335 MI.setDesc(get(PPC::BCLRn));
1336 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1337 .addReg(Pred[1].getReg());
13401338 } else {
1341 MI->setDesc(get(PPC::BCCLR));
1342 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1343 .addImm(Pred[0].getImm())
1344 .addReg(Pred[1].getReg());
1339 MI.setDesc(get(PPC::BCCLR));
1340 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1341 .addImm(Pred[0].getImm())
1342 .addReg(Pred[1].getReg());
13451343 }
13461344
13471345 return true;
13481346 } else if (OpC == PPC::B) {
13491347 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
13501348 bool isPPC64 = Subtarget.isPPC64();
1351 MI->setDesc(get(Pred[0].getImm() ?
1352 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1353 (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1349 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1350 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
13541351 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1355 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1356 MI->RemoveOperand(0);
1357
1358 MI->setDesc(get(PPC::BC));
1359 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1360 .addReg(Pred[1].getReg())
1361 .addMBB(MBB);
1352 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1353 MI.RemoveOperand(0);
1354
1355 MI.setDesc(get(PPC::BC));
1356 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1357 .addReg(Pred[1].getReg())
1358 .addMBB(MBB);
13621359 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1363 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1364 MI->RemoveOperand(0);
1365
1366 MI->setDesc(get(PPC::BCn));
1367 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1368 .addReg(Pred[1].getReg())
1369 .addMBB(MBB);
1360 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1361 MI.RemoveOperand(0);
1362
1363 MI.setDesc(get(PPC::BCn));
1364 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1365 .addReg(Pred[1].getReg())
1366 .addMBB(MBB);
13701367 } else {
1371 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1372 MI->RemoveOperand(0);
1373
1374 MI->setDesc(get(PPC::BCC));
1375 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1376 .addImm(Pred[0].getImm())
1377 .addReg(Pred[1].getReg())
1378 .addMBB(MBB);
1368 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1369 MI.RemoveOperand(0);
1370
1371 MI.setDesc(get(PPC::BCC));
1372 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1373 .addImm(Pred[0].getImm())
1374 .addReg(Pred[1].getReg())
1375 .addMBB(MBB);
13791376 }
13801377
13811378 return true;
13881385 bool isPPC64 = Subtarget.isPPC64();
13891386
13901387 if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1391 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
1392 (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1393 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1394 .addReg(Pred[1].getReg());
1388 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1389 : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1390 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1391 .addReg(Pred[1].getReg());
13951392 return true;
13961393 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1397 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) :
1398 (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1399 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1400 .addReg(Pred[1].getReg());
1394 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1395 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1396 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1397 .addReg(Pred[1].getReg());
14011398 return true;
14021399 }
14031400
1404 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) :
1405 (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1406 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1407 .addImm(Pred[0].getImm())
1408 .addReg(Pred[1].getReg());
1401 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1402 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1403 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1404 .addImm(Pred[0].getImm())
1405 .addReg(Pred[1].getReg());
14091406 return true;
14101407 }
14111408
14431440 return false;
14441441 }
14451442
1446 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
1443 bool PPCInstrInfo::DefinesPredicate(MachineInstr &MI,
14471444 std::vector &Pred) const {
14481445 // Note: At the present time, the contents of Pred from this function is
14491446 // unused by IfConversion. This implementation follows ARM by pushing the
14561453 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
14571454
14581455 bool Found = false;
1459 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1460 const MachineOperand &MO = MI->getOperand(i);
1456 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1457 const MachineOperand &MO = MI.getOperand(i);
14611458 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
14621459 const TargetRegisterClass *RC = RCs[c];
14631460 if (MO.isReg()) {
14791476 return Found;
14801477 }
14811478
1482 bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
1483 unsigned OpC = MI->getOpcode();
1479 bool PPCInstrInfo::isPredicable(MachineInstr &MI) const {
1480 unsigned OpC = MI.getOpcode();
14841481 switch (OpC) {
14851482 default:
14861483 return false;
229229 }
230230
231231 // Predication support.
232 bool isPredicated(const MachineInstr *MI) const override;
233
234 bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
235
236 bool PredicateInstruction(MachineInstr *MI,
232 bool isPredicated(const MachineInstr &MI) const override;
233
234 bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
235
236 bool PredicateInstruction(MachineInstr &MI,
237237 ArrayRef Pred) const override;
238238
239239 bool SubsumesPredicate(ArrayRef Pred1,
240240 ArrayRef Pred2) const override;
241241
242 bool DefinesPredicate(MachineInstr *MI,
242 bool DefinesPredicate(MachineInstr &MI,
243243 std::vector &Pred) const override;
244244
245 bool isPredicable(MachineInstr *MI) const override;
245 bool isPredicable(MachineInstr &MI) const override;
246246
247247 // Comparison optimization.
248248
147147 if (I == MBB.end())
148148 return false;
149149
150 if (!isUnpredicatedTerminator(I))
150 if (!isUnpredicatedTerminator(*I))
151151 return false;
152152
153153 // Get the last instruction in the block.
155155 unsigned LastOpc = LastInst->getOpcode();
156156
157157 // If there is only one terminator instruction, process it.
158 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
158 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
159159 if (isUncondBranchOpcode(LastOpc)) {
160160 TBB = LastInst->getOperand(0).getMBB();
161161 return false;
179179 LastInst->eraseFromParent();
180180 LastInst = SecondLastInst;
181181 LastOpc = LastInst->getOpcode();
182 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
182 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
183183 // Return now the only terminator is an unconditional branch.
184184 TBB = LastInst->getOperand(0).getMBB();
185185 return false;
191191 }
192192
193193 // If there are three terminators, we don't know what sort of block this is.
194 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
194 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
195195 return true;
196196
197197 // If the block ends with a B and a Bcc, handle it.
260260
261261 // Working from the bottom, when we see a non-terminator instruction, we're
262262 // done.
263 if (!isUnpredicatedTerminator(I))
263 if (!isUnpredicatedTerminator(*I))
264264 break;
265265
266266 // A terminator that isn't a branch can't easily be handled by this
505505 }
506506 }
507507
508 bool SystemZInstrInfo::isPredicable(MachineInstr *MI) const {
509 unsigned Opcode = MI->getOpcode();
508 bool SystemZInstrInfo::isPredicable(MachineInstr &MI) const {
509 unsigned Opcode = MI.getOpcode();
510510 return STI.hasLoadStoreOnCond() && getConditionalMove(Opcode);
511511 }
512512
528528 return false;
529529 }
530530
531 bool SystemZInstrInfo::
532 PredicateInstruction(MachineInstr *MI, ArrayRef Pred) const {
531 bool SystemZInstrInfo::PredicateInstruction(
532 MachineInstr &MI, ArrayRef Pred) const {
533533 assert(Pred.size() == 2 && "Invalid condition");
534534 unsigned CCValid = Pred[0].getImm();
535535 unsigned CCMask = Pred[1].getImm();
536536 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
537 unsigned Opcode = MI->getOpcode();
537 unsigned Opcode = MI.getOpcode();
538538 if (STI.hasLoadStoreOnCond()) {
539539 if (unsigned CondOpcode = getConditionalMove(Opcode)) {
540 MI->setDesc(get(CondOpcode));
541 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
542 .addImm(CCValid).addImm(CCMask)
543 .addReg(SystemZ::CC, RegState::Implicit);
540 MI.setDesc(get(CondOpcode));
541 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
542 .addImm(CCValid)
543 .addImm(CCMask)
544 .addReg(SystemZ::CC, RegState::Implicit);
544545 return true;
545546 }
546547 }
155155 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
156156 unsigned SrcReg2, int Mask, int Value,
157157 const MachineRegisterInfo *MRI) const override;
158 bool isPredicable(MachineInstr *MI) const override;
158 bool isPredicable(MachineInstr &MI) const override;
159159 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
160160 unsigned ExtraPredCycles,
161161 BranchProbability Probability) const override;
164164 MachineBasicBlock &FMBB,
165165 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
166166 BranchProbability Probability) const override;
167 bool PredicateInstruction(MachineInstr *MI,
167 bool PredicateInstruction(MachineInstr &MI,
168168 ArrayRef Pred) const override;
169169 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
170170 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
39023902 }
39033903 }
39043904
3905 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
3906 if (!MI->isTerminator()) return false;
3905 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
3906 if (!MI.isTerminator()) return false;
39073907
39083908 // Conditional branch is a special case.
3909 if (MI->isBranch() && !MI->isBarrier())
3909 if (MI.isBranch() && !MI.isBarrier())
39103910 return true;
3911 if (!MI->isPredicable())
3911 if (!MI.isPredicable())
39123912 return true;
39133913 return !isPredicated(MI);
39143914 }
39293929
39303930 // Working from the bottom, when we see a non-terminator instruction, we're
39313931 // done.
3932 if (!isUnpredicatedTerminator(I))
3932 if (!isUnpredicatedTerminator(*I))
39333933 break;
39343934
39353935 // A terminator that isn't a branch can't easily be handled by this
304304 unsigned SrcOpIdx2) const;
305305
306306 // Branch analysis.
307 bool isUnpredicatedTerminator(const MachineInstr* MI) const override;
307 bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
308308 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
309309 MachineBasicBlock *&FBB,
310310 SmallVectorImpl &Cond,
199199 if (I == MBB.end())
200200 return false;
201201
202 if (!isUnpredicatedTerminator(I))
202 if (!isUnpredicatedTerminator(*I))
203203 return false;
204204
205205 // Get the last instruction in the block.
206206 MachineInstr *LastInst = I;
207207
208208 // If there is only one terminator instruction, process it.
209 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
209 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
210210 if (IsBRU(LastInst->getOpcode())) {
211211 TBB = LastInst->getOperand(0).getMBB();
212212 return false;
229229 MachineInstr *SecondLastInst = I;
230230
231231 // If there are three terminators, we don't know what sort of block this is.
232 if (SecondLastInst && I != MBB.begin() &&
233 isUnpredicatedTerminator(--I))
232 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
234233 return true;
235234
236235 unsigned SecondLastOpc = SecondLastInst->getOpcode();