llvm.org GIT mirror llvm / 5b8e04c
Always let value types influence register classes. When creating a virtual register for a def, the value type should be used to pick the register class. If we only use the register class constraint on the instruction, we might pick a too large register class. Some registers can store values of different sizes. For example, the x86 xmm registers can hold f32, f64, and 128-bit vectors. The three different value sizes are represented by register classes with identical register sets: FR32, FR64, and VR128. These register classes have different spill slot sizes, so it is important to use the right one. The register class constraint on an instruction doesn't necessarily care about the size of the value its defining. The value type determines that. This fixes a problem where InstrEmitter was picking 32-bit register classes for 64-bit values on SPARC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199187 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 6 years ago
2 changed file(s) with 38 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
219219 unsigned VRBase = 0;
220220 const TargetRegisterClass *RC =
221221 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
222 // If the register class is unknown for the given definition, then try to
223 // infer one from the value type.
224 if (!RC && i < NumResults)
225 RC = TLI->getRegClassFor(Node->getSimpleValueType(i));
222 // Always let the value type influence the used register class. The
223 // constraints on the instruction may be too lax to represent the value
224 // type correctly. For example, a 64-bit float (X86::FR64) can't live in
225 // the 32-bit float super-class (X86::FR32).
226 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
227 const TargetRegisterClass *VTRC =
228 TLI->getRegClassFor(Node->getSimpleValueType(i));
229 if (RC)
230 VTRC = TRI->getCommonSubClass(RC, VTRC);
231 if (VTRC)
232 RC = VTRC;
233 }
234
226235 if (II.OpInfo[i].isOptionalDef()) {
227236 // Optional def must be a physical register.
228237 unsigned NumResults = CountResults(Node);
0 ; RUN: llc < %s -verify-machineinstrs | FileCheck %s
1 target datalayout = "E-m:e-i64:64-n32:64-S128"
2 target triple = "sparcv9"
3
4 ; CHECK-LABEL: spill4
5 ; This function spills two values: %p and the materialized large constant.
6 ; Both must use 8-byte spill and fill instructions.
7 ; CHECK: stx %{{..}}, [%fp+
8 ; CHECK: stx %{{..}}, [%fp+
9 ; CHECK: ldx [%fp+
10 ; CHECK: ldx [%fp+
11 define void @spill4(i64* nocapture %p) {
12 entry:
13 %val0 = load i64* %p
14 %cmp0 = icmp ult i64 %val0, 385672958347594845
15 %cm80 = zext i1 %cmp0 to i64
16 store i64 %cm80, i64* %p, align 8
17 tail call void asm sideeffect "", "~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{g2},~{g3},~{g4},~{g5},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o7}"()
18 %arrayidx1 = getelementptr inbounds i64* %p, i64 1
19 %val = load i64* %arrayidx1
20 %cmp = icmp ult i64 %val, 385672958347594845
21 %cm8 = select i1 %cmp, i64 10, i64 20
22 store i64 %cm8, i64* %arrayidx1, align 8
23 ret void
24 }