llvm.org GIT mirror llvm / 5b85c47
Merge r100559 from mainline to fix PR6696. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_27@100851 91177308-0d34-0410-b5e6-96231b3b80d8 Tanya Lattner 10 years ago
5 changed file(s) with 84 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
6565 ///
6666 FunctionPass *createEmitX86CodeToMemory();
6767
68 /// createX86MaxStackAlignmentHeuristicPass - This function returns a pass
69 /// which determines whether the frame pointer register should be
70 /// reserved in case dynamic stack alignment is later required.
71 ///
72 FunctionPass *createX86MaxStackAlignmentHeuristicPass();
73
6874 extern Target TheX86_32Target, TheX86_64Target;
6975
7076 } // End llvm namespace
5151 /// relocation models.
5252 unsigned GlobalBaseReg;
5353
54 /// ReserveFP - whether the function should reserve the frame pointer
55 /// when allocating, even if there may not actually be a frame pointer used.
56 bool ReserveFP;
57
5458 public:
5559 X86MachineFunctionInfo() : ForceFramePointer(false),
5660 CalleeSavedFrameSize(0),
6771 ReturnAddrIndex(0),
6872 TailCallReturnAddrDelta(0),
6973 SRetReturnReg(0),
70 GlobalBaseReg(0) {}
74 GlobalBaseReg(0),
75 ReserveFP(false) {}
7176
7277 bool getForceFramePointer() const { return ForceFramePointer;}
7378 void setForceFramePointer(bool forceFP) { ForceFramePointer = forceFP; }
8994
9095 unsigned getGlobalBaseReg() const { return GlobalBaseReg; }
9196 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
97
98 bool getReserveFP() const { return ReserveFP; }
99 void setReserveFP(bool reserveFP) { ReserveFP = reserveFP; }
92100 };
93101
94102 } // End llvm namespace
14881488 }
14891489
14901490 #include "X86GenRegisterInfo.inc"
1491
1492 namespace {
1493 struct MSAH : public MachineFunctionPass {
1494 static char ID;
1495 MSAH() : MachineFunctionPass(&ID) {}
1496
1497 virtual bool runOnMachineFunction(MachineFunction &MF) {
1498 const X86TargetMachine *TM =
1499 static_cast(&MF.getTarget());
1500 const X86RegisterInfo *X86RI = TM->getRegisterInfo();
1501 MachineRegisterInfo &RI = MF.getRegInfo();
1502 X86MachineFunctionInfo *FuncInfo = MF.getInfo();
1503 unsigned StackAlignment = X86RI->getStackAlignment();
1504
1505 // Be over-conservative: scan over all vreg defs and find whether vector
1506 // registers are used. If yes, there is a possibility that vector register
1507 // will be spilled and thus require dynamic stack realignment.
1508 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1509 RegNum < RI.getLastVirtReg(); ++RegNum)
1510 if (RI.getRegClass(RegNum)->getAlignment() > StackAlignment) {
1511 FuncInfo->setReserveFP(true);
1512 return true;
1513 }
1514
1515 // Nothing to do
1516 return false;
1517 }
1518
1519 virtual const char *getPassName() const {
1520 return "X86 Maximal Stack Alignment Check";
1521 }
1522
1523 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1524 AU.setPreservesCFG();
1525 MachineFunctionPass::getAnalysisUsage(AU);
1526 }
1527 };
1528
1529 char MSAH::ID = 0;
1530 }
1531
1532 FunctionPass*
1533 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }
351351 const TargetMachine &TM = MF.getTarget();
352352 const TargetRegisterInfo *RI = TM.getRegisterInfo();
353353 const X86Subtarget &Subtarget = TM.getSubtarget();
354 const X86MachineFunctionInfo *MFI = MF.getInfo();
354355 // Does the function dedicate RBP / EBP to being a frame ptr?
355356 if (!Subtarget.is64Bit())
356357 // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
357358 return begin() + 8;
358 else if (RI->hasFP(MF))
359 else if (RI->hasFP(MF) || MFI->getReserveFP())
359360 // If so, don't allocate SPL or BPL.
360361 return array_endof(X86_GR8_AO_64) - 1;
361362 else
395396 const TargetMachine &TM = MF.getTarget();
396397 const TargetRegisterInfo *RI = TM.getRegisterInfo();
397398 const X86Subtarget &Subtarget = TM.getSubtarget();
399 const X86MachineFunctionInfo *MFI = MF.getInfo();
398400 if (Subtarget.is64Bit()) {
399401 // Does the function dedicate RBP to being a frame ptr?
400 if (RI->hasFP(MF))
402 if (RI->hasFP(MF) || MFI->getReserveFP())
401403 // If so, don't allocate SP or BP.
402404 return array_endof(X86_GR16_AO_64) - 1;
403405 else
405407 return array_endof(X86_GR16_AO_64);
406408 } else {
407409 // Does the function dedicate EBP to being a frame ptr?
408 if (RI->hasFP(MF))
410 if (RI->hasFP(MF) || MFI->getReserveFP())
409411 // If so, don't allocate SP or BP.
410412 return begin() + 6;
411413 else
446448 const TargetMachine &TM = MF.getTarget();
447449 const TargetRegisterInfo *RI = TM.getRegisterInfo();
448450 const X86Subtarget &Subtarget = TM.getSubtarget();
451 const X86MachineFunctionInfo *MFI = MF.getInfo();
449452 if (Subtarget.is64Bit()) {
450453 // Does the function dedicate RBP to being a frame ptr?
451 if (RI->hasFP(MF))
454 if (RI->hasFP(MF) || MFI->getReserveFP())
452455 // If so, don't allocate ESP or EBP.
453456 return array_endof(X86_GR32_AO_64) - 1;
454457 else
456459 return array_endof(X86_GR32_AO_64);
457460 } else {
458461 // Does the function dedicate EBP to being a frame ptr?
459 if (RI->hasFP(MF))
462 if (RI->hasFP(MF) || MFI->getReserveFP())
460463 // If so, don't allocate ESP or EBP.
461464 return begin() + 6;
462465 else
483486 const TargetMachine &TM = MF.getTarget();
484487 const TargetRegisterInfo *RI = TM.getRegisterInfo();
485488 const X86Subtarget &Subtarget = TM.getSubtarget();
489 const X86MachineFunctionInfo *MFI = MF.getInfo();
486490 if (!Subtarget.is64Bit())
487491 return begin(); // None of these are allocatable in 32-bit.
488 if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
492 // Does the function dedicate RBP to being a frame ptr?
493 if (RI->hasFP(MF) || MFI->getReserveFP())
489494 return end()-3; // If so, don't allocate RIP, RSP or RBP
490495 else
491496 return end()-2; // If not, just don't allocate RIP or RSP
581586 GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
582587 const TargetMachine &TM = MF.getTarget();
583588 const TargetRegisterInfo *RI = TM.getRegisterInfo();
589 const X86MachineFunctionInfo *MFI = MF.getInfo();
584590 // Does the function dedicate RBP / EBP to being a frame ptr?
585 if (RI->hasFP(MF))
591 if (RI->hasFP(MF) || MFI->getReserveFP())
586592 // If so, don't allocate SP or BP.
587593 return end() - 2;
588594 else
603609 GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
604610 const TargetMachine &TM = MF.getTarget();
605611 const TargetRegisterInfo *RI = TM.getRegisterInfo();
612 const X86MachineFunctionInfo *MFI = MF.getInfo();
606613 // Does the function dedicate RBP / EBP to being a frame ptr?
607 if (RI->hasFP(MF))
614 if (RI->hasFP(MF) || MFI->getReserveFP())
608615 // If so, don't allocate ESP or EBP.
609616 return end() - 2;
610617 else
625632 GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
626633 const TargetMachine &TM = MF.getTarget();
627634 const TargetRegisterInfo *RI = TM.getRegisterInfo();
635 const X86MachineFunctionInfo *MFI = MF.getInfo();
628636 // Does the function dedicate RBP to being a frame ptr?
629 if (RI->hasFP(MF))
637 if (RI->hasFP(MF) || MFI->getReserveFP())
630638 // If so, don't allocate RIP, RSP or RBP.
631639 return end() - 3;
632640 else
667675 const TargetMachine &TM = MF.getTarget();
668676 const TargetRegisterInfo *RI = TM.getRegisterInfo();
669677 const X86Subtarget &Subtarget = TM.getSubtarget();
678 const X86MachineFunctionInfo *MFI = MF.getInfo();
670679 if (Subtarget.is64Bit()) {
671680 // Does the function dedicate RBP to being a frame ptr?
672 if (RI->hasFP(MF))
681 if (RI->hasFP(MF) || MFI->getReserveFP())
673682 // If so, don't allocate EBP.
674683 return array_endof(X86_GR32_NOSP_AO_64) - 1;
675684 else
677686 return array_endof(X86_GR32_NOSP_AO_64);
678687 } else {
679688 // Does the function dedicate EBP to being a frame ptr?
680 if (RI->hasFP(MF))
689 if (RI->hasFP(MF) || MFI->getReserveFP())
681690 // If so, don't allocate EBP.
682691 return begin() + 6;
683692 else
702711 const TargetMachine &TM = MF.getTarget();
703712 const TargetRegisterInfo *RI = TM.getRegisterInfo();
704713 const X86Subtarget &Subtarget = TM.getSubtarget();
714 const X86MachineFunctionInfo *MFI = MF.getInfo();
705715 if (!Subtarget.is64Bit())
706716 return begin(); // None of these are allocatable in 32-bit.
707 if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
717 // Does the function dedicate RBP to being a frame ptr?
718 if (RI->hasFP(MF) || MFI->getReserveFP())
708719 return end()-1; // If so, don't allocate RBP
709720 else
710721 return end(); // If not, any reg in this class is ok.
725736 {
726737 const TargetMachine &TM = MF.getTarget();
727738 const TargetRegisterInfo *RI = TM.getRegisterInfo();
739 const X86MachineFunctionInfo *MFI = MF.getInfo();
728740 // Does the function dedicate RBP to being a frame ptr?
729 if (RI->hasFP(MF))
741 if (RI->hasFP(MF) || MFI->getReserveFP())
730742 // If so, don't allocate RBP.
731743 return end() - 1;
732744 else
159159
160160 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
161161 CodeGenOpt::Level OptLevel) {
162 PM.add(createX86MaxStackAlignmentHeuristicPass());
162163 return false; // -print-machineinstr shouldn't print after this.
163164 }
164165