llvm.org GIT mirror llvm / 5b56cc8
Rename ExpandISelPseudo->FinalizeISel, delay register reservation This allows targets to make more decisions about reserved registers after isel. For example, now it should be certain there are calls or stack objects in the frame or not, which could have been introduced by legalization. Patch by Matthias Braun git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363757 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault a month ago
103 changed file(s) with 235 addition(s) and 200 deletion(s). Raw diff Collapse all Expand all
344344 /// pointer or stack pointer index addressing.
345345 extern char &LocalStackSlotAllocationID;
346346
347 /// ExpandISelPseudos - This pass expands pseudo-instructions.
348 extern char &ExpandISelPseudosID;
347 /// This pass expands pseudo-instructions, reserves registers and adjusts
348 /// machine frame information.
349 extern char &FinalizeISelID;
349350
350351 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
351352 extern char &UnpackMachineBundlesID;
136136 void initializeEdgeBundlesPass(PassRegistry&);
137137 void initializeEliminateAvailableExternallyLegacyPassPass(PassRegistry&);
138138 void initializeEntryExitInstrumenterPass(PassRegistry&);
139 void initializeExpandISelPseudosPass(PassRegistry&);
140139 void initializeExpandMemCmpPassPass(PassRegistry&);
141140 void initializeExpandPostRAPass(PassRegistry&);
142141 void initializeExpandReductionsPass(PassRegistry&);
143142 void initializeMakeGuardsExplicitLegacyPassPass(PassRegistry&);
144143 void initializeExternalAAWrapperPassPass(PassRegistry&);
145144 void initializeFEntryInserterPass(PassRegistry&);
145 void initializeFinalizeISelPass(PassRegistry&);
146146 void initializeFinalizeMachineBundlesPass(PassRegistry&);
147147 void initializeFlattenCFGPassPass(PassRegistry&);
148148 void initializeFloat2IntLegacyPassPass(PassRegistry&);
2020 EarlyIfConversion.cpp
2121 EdgeBundles.cpp
2222 ExecutionDomainFix.cpp
23 ExpandISelPseudos.cpp
2423 ExpandMemCmp.cpp
2524 ExpandPostRAPseudos.cpp
2625 ExpandReductions.cpp
2726 FaultMaps.cpp
2827 FEntryInserter.cpp
28 FinalizeISel.cpp
2929 FuncletLayout.cpp
3030 GCMetadata.cpp
3131 GCMetadataPrinter.cpp
2929 initializeEarlyIfConverterPass(Registry);
3030 initializeEarlyMachineLICMPass(Registry);
3131 initializeEarlyTailDuplicatePass(Registry);
32 initializeExpandISelPseudosPass(Registry);
3332 initializeExpandMemCmpPassPass(Registry);
3433 initializeExpandPostRAPass(Registry);
3534 initializeFEntryInserterPass(Registry);
35 initializeFinalizeISelPass(Registry);
3636 initializeFinalizeMachineBundlesPass(Registry);
3737 initializeFuncletLayoutPass(Registry);
3838 initializeGCMachineCodeAnalysisPass(Registry);
+0
-73
lib/CodeGen/ExpandISelPseudos.cpp less more
None //===-- llvm/CodeGen/ExpandISelPseudos.cpp ----------------------*- C++ -*-===//
1 //
2 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
3 // See https://llvm.org/LICENSE.txt for license information.
4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5 //
6 //===----------------------------------------------------------------------===//
7 //
8 // Expand Pseudo-instructions produced by ISel. These are usually to allow
9 // the expansion to contain control flow, such as a conditional move
10 // implemented with a conditional branch and a phi, or an atomic operation
11 // implemented with a loop.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/TargetLowering.h"
19 #include "llvm/CodeGen/TargetSubtargetInfo.h"
20 #include "llvm/Support/Debug.h"
21 using namespace llvm;
22
23 #define DEBUG_TYPE "expand-isel-pseudos"
24
25 namespace {
26 class ExpandISelPseudos : public MachineFunctionPass {
27 public:
28 static char ID; // Pass identification, replacement for typeid
29 ExpandISelPseudos() : MachineFunctionPass(ID) {}
30
31 private:
32 bool runOnMachineFunction(MachineFunction &MF) override;
33
34 void getAnalysisUsage(AnalysisUsage &AU) const override {
35 MachineFunctionPass::getAnalysisUsage(AU);
36 }
37 };
38 } // end anonymous namespace
39
40 char ExpandISelPseudos::ID = 0;
41 char &llvm::ExpandISelPseudosID = ExpandISelPseudos::ID;
42 INITIALIZE_PASS(ExpandISelPseudos, DEBUG_TYPE,
43 "Expand ISel Pseudo-instructions", false, false)
44
45 bool ExpandISelPseudos::runOnMachineFunction(MachineFunction &MF) {
46 bool Changed = false;
47 const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
48
49 // Iterate through each instruction in the function, looking for pseudos.
50 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
51 MachineBasicBlock *MBB = &*I;
52 for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end();
53 MBBI != MBBE; ) {
54 MachineInstr &MI = *MBBI++;
55
56 // If MI is a pseudo, expand it.
57 if (MI.usesCustomInsertionHook()) {
58 Changed = true;
59 MachineBasicBlock *NewMBB = TLI->EmitInstrWithCustomInserter(MI, MBB);
60 // The expansion may involve new basic blocks.
61 if (NewMBB != MBB) {
62 MBB = NewMBB;
63 I = NewMBB->getIterator();
64 MBBI = NewMBB->begin();
65 MBBE = NewMBB->end();
66 }
67 }
68 }
69 }
70
71 return Changed;
72 }
0 //===-- llvm/CodeGen/FinalizeISel.cpp ---------------------------*- C++ -*-===//
1 //
2 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
3 // See https://llvm.org/LICENSE.txt for license information.
4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5 //
6 //===----------------------------------------------------------------------===//
7 //
8 /// This pass expands Pseudo-instructions produced by ISel, fixes register
9 /// reservations and may do machine frame information adjustments.
10 /// The pseudo instructions are used to allow the expansion to contain control
11 /// flow, such as a conditional move implemented with a conditional branch and a
12 /// phi, or an atomic operation implemented with a loop.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/CodeGen/TargetLowering.h"
20 #include "llvm/CodeGen/TargetSubtargetInfo.h"
21 #include "llvm/Support/Debug.h"
22 using namespace llvm;
23
24 #define DEBUG_TYPE "finalize-isel"
25
26 namespace {
27 class FinalizeISel : public MachineFunctionPass {
28 public:
29 static char ID; // Pass identification, replacement for typeid
30 FinalizeISel() : MachineFunctionPass(ID) {}
31
32 private:
33 bool runOnMachineFunction(MachineFunction &MF) override;
34
35 void getAnalysisUsage(AnalysisUsage &AU) const override {
36 MachineFunctionPass::getAnalysisUsage(AU);
37 }
38 };
39 } // end anonymous namespace
40
41 char FinalizeISel::ID = 0;
42 char &llvm::FinalizeISelID = FinalizeISel::ID;
43 INITIALIZE_PASS(FinalizeISel, DEBUG_TYPE,
44 "Finalize ISel and expand pseudo-instructions", false, false)
45
46 bool FinalizeISel::runOnMachineFunction(MachineFunction &MF) {
47 bool Changed = false;
48 const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
49
50 // Iterate through each instruction in the function, looking for pseudos.
51 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
52 MachineBasicBlock *MBB = &*I;
53 for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end();
54 MBBI != MBBE; ) {
55 MachineInstr &MI = *MBBI++;
56
57 // If MI is a pseudo, expand it.
58 if (MI.usesCustomInsertionHook()) {
59 Changed = true;
60 MachineBasicBlock *NewMBB = TLI->EmitInstrWithCustomInserter(MI, MBB);
61 // The expansion may involve new basic blocks.
62 if (NewMBB != MBB) {
63 MBB = NewMBB;
64 I = NewMBB->getIterator();
65 MBBI = NewMBB->begin();
66 MBBE = NewMBB->end();
67 }
68 }
69 }
70 }
71
72 TLI->finalizeLowering(MF);
73
74 return Changed;
75 }
217217
218218 bool isAllocatable(unsigned Reg) const {
219219 return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
220 !regsReserved.test(Reg);
220 !regsReserved.test(Reg);
221221 }
222222
223223 // Analysis information if available
85368536 /// avoid constant materialization and register allocation.
85378537 ///
85388538 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
8539 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
8539 /// generate addess computation nodes, and so FinalizeISel can convert the
85408540 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
85418541 /// address materialization and register allocation, but may also be required
85428542 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
655655 // Determine if floating point is used for msvc
656656 computeUsesMSVCFloatingPoint(TM.getTargetTriple(), Fn, MF->getMMI());
657657
658 // Replace forward-declared registers with the registers containing
659 // the desired value.
660 for (DenseMap::iterator
661 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
662 I != E; ++I) {
663 unsigned From = I->first;
664 unsigned To = I->second;
665 // If To is also scheduled to be replaced, find what its ultimate
666 // replacement is.
667 while (true) {
668 DenseMap::iterator J = FuncInfo->RegFixups.find(To);
669 if (J == E) break;
670 To = J->second;
671 }
672 // Make sure the new register has a sufficiently constrained register class.
673 if (TargetRegisterInfo::isVirtualRegister(From) &&
674 TargetRegisterInfo::isVirtualRegister(To))
675 MRI.constrainRegClass(To, MRI.getRegClass(From));
676 // Replace it.
677
678
679 // Replacing one register with another won't touch the kill flags.
680 // We need to conservatively clear the kill flags as a kill on the old
681 // register might dominate existing uses of the new register.
682 if (!MRI.use_empty(To))
683 MRI.clearKillFlags(From);
684 MRI.replaceRegWith(From, To);
685 }
686
658687 TLI->finalizeLowering(*MF);
659688
660689 // Release function-specific state. SDB and CurDAG are already cleared
814814 } else if (addInstSelector())
815815 return true;
816816
817 // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
818 // FinalizeISel.
819 addPass(&FinalizeISelID);
820
821 // Print the instruction selected machine code...
822 printAndVerify("After Instruction Selection");
823
817824 return false;
818825 }
819826
873880 }
874881 }
875882
876 // Print the instruction selected machine code...
877 printAndVerify("After Instruction Selection");
878
879 // Expand pseudo-instructions emitted by ISel.
880 addPass(&ExpandISelPseudosID);
881
882883 // Add passes that optimize machine instructions in SSA form.
883884 if (getOptLevel() != CodeGenOpt::None) {
884885 addMachineSSAOptimization();
751751 }
752752
753753 bool AMDGPUPassConfig::addInstSelector() {
754 addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
754 // Defer the verifier until FinalizeISel.
755 addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
755756 return false;
756757 }
757758
2338423384 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2338523385 MFI.setHasCopyImplyingStackAdjustment(true);
2338623386 // Don't do anything here, we will expand these intrinsics out later
23387 // during ExpandISelPseudos in EmitInstrWithCustomInserter.
23387 // during FinalizeISel in EmitInstrWithCustomInserter.
2338823388 return SDValue();
2338923389 }
2339023390 case Intrinsic::x86_lwpins32:
2424 ; DISABLED-NOT: IRTranslator
2525
2626 ; DISABLED: AArch64 Instruction Selection
27 ; DISABLED: Expand ISel Pseudo-instructions
27 ; DISABLED: Finalize ISel and expand pseudo-instructions
2828
2929 ; FASTISEL: Enabling fast-isel
3030 ; NOFASTISEL-NOT: Enabling fast-isel
6161 ; DISABLED-NOT: IRTranslator
6262
6363 ; DISABLED: AArch64 Instruction Selection
64 ; DISABLED: Expand ISel Pseudo-instructions
64 ; DISABLED: Finalize ISel and expand pseudo-instructions
6565
6666 define void @empty() {
6767 ret void
4141 ; CHECK-NEXT: InstructionSelect
4242 ; CHECK-NEXT: ResetMachineFunction
4343 ; CHECK-NEXT: AArch64 Instruction Selection
44 ; CHECK-NEXT: Expand ISel Pseudo-instructions
44 ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
4545 ; CHECK-NEXT: Local Stack Slot Allocation
4646 ; CHECK-NEXT: Eliminate PHI nodes for register allocation
4747 ; CHECK-NEXT: Two-Address instruction pass
7575 ; CHECK-NEXT: AArch64 Instruction Selection
7676 ; CHECK-NEXT: MachineDominator Tree Construction
7777 ; CHECK-NEXT: AArch64 Local Dynamic TLS Access Clean-up
78 ; CHECK-NEXT: Expand ISel Pseudo-instructions
78 ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
7979 ; CHECK-NEXT: Early Tail Duplication
8080 ; CHECK-NEXT: Optimize machine instruction PHIs
8181 ; CHECK-NEXT: Slot index numbering
None ; RUN: llc -mtriple=arm64-apple-ios -mcpu=apple-latest -stop-before=expand-isel-pseudos -o - 2>&1 < %s | FileCheck %s
0 ; RUN: llc -mtriple=arm64-apple-ios -mcpu=apple-latest -stop-before=finalize-isel -o - 2>&1 < %s | FileCheck %s
11
22 ; CHECK-LABEL: @dummy
33 ; CHECK: "target-cpu"="apple-latest"
0 ; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
1 ; RUN: llc %s -O0 -fast-isel -fast-isel-abort=1 -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t
1 ; RUN: llc %s -O0 -fast-isel -fast-isel-abort=1 -mtriple=arm64-apple-darwin -print-after=finalize-isel -o /dev/null 2> %t
22 ; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA
33
44 ; CHECK-SSA-LABEL: Machine code for function t1
None ; RUN: llc -o - %s -fast-isel -stop-before=expand-isel-pseudos | FileCheck %s
0 ; RUN: llc -o - %s -fast-isel -stop-before=finalize-isel | FileCheck %s
11 ; Make sure fast-isel produces DBG_VALUE instructions even if no debug printer
22 ; is scheduled because of -stop-before.
33 target triple="aarch64--"
None ; RUN: llc -mtriple=arm64--- -stop-after=expand-isel-pseudos -o - %s | FileCheck %s
0 ; RUN: llc -mtriple=arm64--- -stop-after=finalize-isel -o - %s | FileCheck %s
11
22 ; Check that we ignore the zeroext attribute on the return type of the tail
33 ; call, since the return value is unused. This happens during CodeGenPrepare in
None ; RUN: llc -o - %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after expand-isel-pseudos | FileCheck %s
0 ; RUN: llc -o - %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after finalize-isel | FileCheck %s
11 ; This test verifies that the instruction selection will add the implicit
22 ; register operands in the correct order when modifying the opcode of an
33 ; instruction to V_ADD_I32_e32.
None ; RUN: llc -O0 -mtriple armv7-- -stop-before=expand-isel-pseudos < %s
1 ; RUN: llc -O0 -mtriple armv7-- -stop-before=expand-isel-pseudos -global-isel < %s
0 ; RUN: llc -O0 -mtriple armv7-- -stop-before=finalize-isel < %s
1 ; RUN: llc -O0 -mtriple armv7-- -stop-before=finalize-isel -global-isel < %s
22
33 ; CHECK: PKHBT
44
5757 ; CHECK-NEXT: Natural Loop Information
5858 ; CHECK-NEXT: Branch Probability Analysis
5959 ; CHECK-NEXT: ARM Instruction Selection
60 ; CHECK-NEXT: Expand ISel Pseudo-instructions
60 ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
6161 ; CHECK-NEXT: Early Tail Duplication
6262 ; CHECK-NEXT: Optimize machine instruction PHIs
6363 ; CHECK-NEXT: Slot index numbering
None ; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-DIV
0 ; RUN: llc -mtriple thumbv7--windows-itanium -print-after=finalize-isel -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-DIV
11
22 ; int f(int n, int d) {
33 ; if (n / d)
3939 ; CHECK-DIV-DAG: successors: %bb.3
4040 ; CHECK-DIV-DAG: %bb.3
4141
42 ; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD
42 ; RUN: llc -mtriple thumbv7--windows-itanium -print-after=finalize-isel -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD
4343
4444 ; int r;
4545 ; int g(int l, int m) {
7373 ; CHECK-MOD-DAG: successors: %bb.2
7474 ; CHECK-MOD-DAG: %bb.2
7575
76 ; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG
76 ; RUN: llc -mtriple thumbv7--windows-itanium -print-after=finalize-isel -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG
7777 ; RUN: llc -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-CFG-ASM
7878
7979 ; unsigned c;
None ; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o /dev/null %s -print-machineinstrs=expand-isel-pseudos 2>&1 | FileCheck %s
0 ; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o /dev/null %s -print-after=finalize-isel 2>&1 | FileCheck %s
11
22 declare arm_aapcs_vfpcc void @g(i8*) local_unnamed_addr
33
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=armv7-unknown-linux < %s -stop-before=expand-isel-pseudos | FileCheck --check-prefix=BEFORE-EXPAND %s
1 ; RUN: llc -mtriple=armv7-unknown-linux < %s -stop-before=finalize-isel | FileCheck --check-prefix=BEFORE-EXPAND %s
22 ; RUN: llc -mtriple=armv7-unknown-linux < %s | FileCheck --check-prefix=ASSEMBLY %s
33
44 ; Check COPY_STRUCT_BYVAL_I32 has CPSR as operand.
None ; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s
0 ; RUN: llc < %s -print-after=finalize-isel -o /dev/null 2>&1 | FileCheck %s
11
22 ; Hexagon runs passes that renumber the basic blocks, causing this test
33 ; to fail.
None ; RUN: llc -march=hexagon -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 < %s | FileCheck %s
0 ; RUN: llc -march=hexagon -print-after=finalize-isel -o /dev/null 2>&1 < %s | FileCheck %s
11 ; REQUIRES: asserts
22
33 ; CHECK: J2_call @f1
11 # RUN: -verify-machineinstrs %s -o - | FileCheck %s
22 #
33 # RUN: llc -mtriple aarch64-- -global-isel=true -global-isel-abort=2 \
4 # RUN: -start-after=regbankselect -stop-before=expand-isel-pseudos \
4 # RUN: -start-after=regbankselect -stop-before=finalize-isel \
55 # RUN: -simplify-mir -verify-machineinstrs %s -o - 2>&1 \
66 # RUN: | FileCheck %s --check-prefix=FALLBACK
77
None ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after expand-isel-pseudos -o %t.mir %s
0 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after finalize-isel -o %t.mir %s
11 ; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s
22
33 ; Test that SIMachineFunctionInfo can be round trip serialized through
None # RUN: llc -run-pass expand-isel-pseudos -run-pass peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE
1 # RUN: llc -run-pass expand-isel-pseudos,peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE
2 # RUN: llc -run-pass peephole-opt -run-pass expand-isel-pseudos -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO
3 # RUN: llc -run-pass peephole-opt,expand-isel-pseudos -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO
0 # RUN: llc -run-pass finalize-isel -run-pass peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE
1 # RUN: llc -run-pass finalize-isel,peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE
2 # RUN: llc -run-pass peephole-opt -run-pass finalize-isel -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO
3 # RUN: llc -run-pass peephole-opt,finalize-isel -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO
44 # REQUIRES: asserts
55
66 # This test ensures that the command line accepts
77 # several run passes on the same command line and
88 # actually create the proper pipeline for it.
9 # PSEUDO_PEEPHOLE: -expand-isel-pseudos
9 # PSEUDO_PEEPHOLE: -finalize-isel
1010 # PSEUDO_PEEPHOLE-SAME: {{(-machineverifier )?}}-peephole-opt
11 # PEEPHOLE_PSEUDO: -peephole-opt {{(-machineverifier )?}}-expand-isel-pseudos
11 # PEEPHOLE_PSEUDO: -peephole-opt {{(-machineverifier )?}}-finalize-isel
1212
1313 # Make sure there are no other passes happening after what we asked.
1414 # CHECK-NEXT: --- |
0 ; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \
11 ; RUN: -mcpu=mips32 -mattr=+fpxx \
2 ; RUN: -stop-after=expand-isel-pseudos | \
2 ; RUN: -stop-after=finalize-isel | \
33 ; RUN: FileCheck %s -check-prefix=FPXX-IMPLICIT-SP
44
55 ; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \
66 ; RUN: -mcpu=mips32r6 -mattr=+fp64,+nooddspreg \
7 ; RUN: -stop-after=expand-isel-pseudos | \
7 ; RUN: -stop-after=finalize-isel | \
88 ; RUN: FileCheck %s -check-prefix=FP64-IMPLICIT-SP
99
1010 ; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \
1111 ; RUN: -mcpu=mips32r2 -mattr=+fpxx \
12 ; RUN: -stop-after=expand-isel-pseudos | \
12 ; RUN: -stop-after=finalize-isel | \
1313 ; RUN: FileCheck %s -check-prefix=NO-IMPLICIT-SP
1414
1515 define double @foo2(i32 signext %v1, double %d1) {
0 # RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \
1 # RUN: -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
1 # RUN: -start-after=finalize-isel -stop-after=finalize-isel \
22 # RUN: -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \
33 # RUN: | FileCheck %s
44
0 # RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \
1 # RUN: -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
1 # RUN: -start-after=finalize-isel -stop-after=finalize-isel \
22 # RUN: -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \
33 # RUN: | FileCheck %s
44
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Position operand is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Size operand is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Position + Size is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Position operand is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Size operand is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Position + Size is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Position operand is out of range!
None # RUN: llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK-NOT: Size operand is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Size operand is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Position + Size is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Position operand is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Size operand is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Position + Size is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Position operand is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Size operand is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Position + Size is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Position operand is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Size operand is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Position + Size is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Position operand is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Size operand is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Position + Size is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Position operand is out of range!
None # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
0 # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
11 # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
22
33 # CHECK: Size operand is out of range!
None # RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=expand-isel-pseudos \
0 # RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=finalize-isel \
11 # RUN: -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s
22
33 --- |
None ; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips -stop-after=expand-isel-pseudos < %s | FileCheck %s
0 ; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips -stop-after=finalize-isel < %s | FileCheck %s
11
22 ; CHECK: JAL_MM
33 ; CHECK-NOT: JALR16_MM
None # RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \
1 # RUN: -stop-after=expand-isel-pseudos -relocation-model=pic -mxgot \
0 # RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \
1 # RUN: -stop-after=finalize-isel -relocation-model=pic -mxgot \
22 # RUN: -o /dev/null %s
33
44 # A simple test to show that we can parse the target specific flags: gpoff-hi,
None # RUN: llc -march=mips -start-before=expand-isel-pseudos \
1 # RUN: -stop-after=expand-isel-pseudos -relocation-model=pic \
0 # RUN: llc -march=mips -start-before=finalize-isel \
1 # RUN: -stop-after=finalize-isel -relocation-model=pic \
22 # RUN: -o /dev/null %s
33
44 # A simple test to show that we can parse the target specific flags: got-call,
None # RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \
1 # RUN: -stop-after=expand-isel-pseudos -relocation-model=pic \
0 # RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \
1 # RUN: -stop-after=finalize-isel -relocation-model=pic \
22 # RUN: -o /dev/null %s
33
44 # A simple test to show that we can parse the target specific flags: gpoff-hi,
None # RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \
1 # RUN: -stop-after=expand-isel-pseudos -relocation-model=static -o /dev/null %s
0 # RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \
1 # RUN: -stop-after=finalize-isel -relocation-model=static -o /dev/null %s
22
33 # A simple test to show that we can parse the target specific flags: highest,
44 # higher, hi, lo, tprel-lo, tprel-hi, gpoff-hi, gpoff-lo, gottprel.
None # RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=expand-isel-pseudos \
0 # RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=finalize-isel \
11 # RUN: -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s
22
33 # Test that MIPS unaligned load/store instructions can be mapped to their
0 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 ; RUN: llc -march=mips -mcpu=mips32r2 -stop-before=expand-isel-pseudos < %s | FileCheck %s --check-prefix=MIPS
2 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=expand-isel-pseudos < %s | FileCheck %s --check-prefix=MICROMIPS
1 ; RUN: llc -march=mips -mcpu=mips32r2 -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MIPS
2 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MICROMIPS
33
44 ; Test that the correct ISA version of the unaligned memory operations is
55 ; selected up front.
None ; RUN: llc < %s -stop-before=expand-isel-pseudos -o - | FileCheck %s
0 ; RUN: llc < %s -stop-before=finalize-isel -o - | FileCheck %s
11
22 source_filename = "foo.c"
33 target datalayout = "E-m:e-p:32:32-i64:64-n32"
11 ; not be placed betwen two compare and load-on-condition instructions.
22 ;
33 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -pre-RA-sched=list-ilp \
4 ; RUN: -print-after=expand-isel-pseudos 2>&1 | FileCheck %s
4 ; RUN: -print-after=finalize-isel 2>&1 | FileCheck %s
55 ;
66 ; CHECK-LABEL: bb.0.bb:
77 ; CHECK: CLI
11 # the presence of DEBUG_VALUE machine instructions.
22 #
33 # RUN: llc %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z13 \
4 # RUN: -start-before=expand-isel-pseudos -o - 2>&1 | FileCheck %s
4 # RUN: -start-before=finalize-isel -o - 2>&1 | FileCheck %s
55 #
66 # CHECK-LABEL: %bb.1:
77 # CHECK: ldr
None ; RUN: llc < %s -mtriple=x86_64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -print-after=finalize-isel -o /dev/null 2>&1 | FileCheck %s
11
22 ;; Make sure a transformation in SelectionDAGBuilder that converts "or + br" to
33 ;; two branches correctly updates the branch probability.
3737 ; CHECK-NEXT: Module Verifier
3838 ; CHECK-NEXT: X86 DAG->DAG Instruction Selection
3939 ; CHECK-NEXT: X86 PIC Global Base Reg Initialization
40 ; CHECK-NEXT: Expand ISel Pseudo-instructions
40 ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
4141 ; CHECK-NEXT: Local Stack Slot Allocation
4242 ; CHECK-NEXT: X86 speculative load hardening
4343 ; CHECK-NEXT: MachineDominator Tree Construction
6666 ; CHECK-NEXT: MachineDominator Tree Construction
6767 ; CHECK-NEXT: Local Dynamic TLS Access Clean-up
6868 ; CHECK-NEXT: X86 PIC Global Base Reg Initialization
69 ; CHECK-NEXT: Expand ISel Pseudo-instructions
69 ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
7070 ; CHECK-NEXT: X86 Domain Reassignment Pass
7171 ; CHECK-NEXT: Early Tail Duplication
7272 ; CHECK-NEXT: Optimize machine instruction PHIs
None ; RUN: llc -print-machineinstrs=expand-isel-pseudos %s -o /dev/null 2>&1 | FileCheck %s
0 ; RUN: llc -print-after=finalize-isel %s -o /dev/null 2>&1 | FileCheck %s
11
22 ; Check if the edge weight to the catchpad is calculated correctly.
33
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-apple-darwin10 -stop-after=expand-isel-pseudos | FileCheck %s
1 ; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-apple-darwin10 -stop-after=finalize-isel | FileCheck %s
22
33 ; Make sure we output the right kill flag for the xor conversion.
44
None ; RUN: llc -mtriple=x86_64-apple-unknown -stop-before=expand-isel-pseudos %s -o - -simplify-mir | FileCheck %s
0 ; RUN: llc -mtriple=x86_64-apple-unknown -stop-before=finalize-isel %s -o - -simplify-mir | FileCheck %s
11 ; The byval argument of the function will be allocated a fixed stack slot. Test
22 ; that we serialize the fixed slot correctly.
33
None ; RUN: llc -stop-after expand-isel-pseudos < %s 2>&1 | FileCheck %s
0 ; RUN: llc -stop-after finalize-isel < %s 2>&1 | FileCheck %s
11
22 target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
33 target triple = "i386-unknown-linux-gnu"
None ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f -stop-after=expand-isel-pseudos | FileCheck %s
0 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f -stop-after=finalize-isel | FileCheck %s
11
22 ; CHECK: %[[REG1:.*]]:vr512_0_15 = COPY %1
33 ; CHECK: %[[REG2:.*]]:vr512_0_15 = COPY %2
None ; RUN: llc < %s -mtriple=i686 -stop-after=expand-isel-pseudos | FileCheck %s
0 ; RUN: llc < %s -mtriple=i686 -stop-after=finalize-isel | FileCheck %s
11
22 ; CHECK: INLINEASM &"", 1, 12, implicit-def early-clobber $df, 12, implicit-def early-clobber $fpsw, 12, implicit-def early-clobber $eflags
33 define void @foo() {
None ; RUN: llc %s -start-after=codegenprepare -stop-after=expand-isel-pseudos -o - | FileCheck %s
0 ; RUN: llc %s -start-after=codegenprepare -stop-after=finalize-isel -o - | FileCheck %s
11
22 ; PR39896: When code such as %conv below is dropped by SelectionDAG for having
33 ; no users, don't just drop the dbg.value record associated with it. Instead,
None # RUN: llc -mtriple=x86_64-- -run-pass=expand-isel-pseudos -verify-machineinstrs -o - %s | FileCheck %s
0 # RUN: llc -mtriple=x86_64-- -run-pass=finalize-isel -verify-machineinstrs -o - %s | FileCheck %s
11 # Check that we're not copying the kill flags with the operands from the pseudo
22 # instruction.
33 --- |
None ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2,fma -stop-after=expand-isel-pseudos 2>&1 | FileCheck %s
0 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2,fma -stop-after=finalize-isel 2>&1 | FileCheck %s
11
22 declare float @llvm.sqrt.f32(float) #0
33
None ; RUN: llc -mtriple=x86_64-apple-darwin -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-SELDAG
1 ; RUN: llc -mtriple=x86_64-apple-darwin -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-IR
2 ; RUN: llc -mtriple=i386-pc-windows-msvc -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-SELDAG
3 ; RUN: llc -mtriple=i386-pc-windows-msvc -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-IR
0 ; RUN: llc -mtriple=x86_64-apple-darwin -print-after=finalize-isel -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-SELDAG
1 ; RUN: llc -mtriple=x86_64-apple-darwin -print-after=finalize-isel -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-IR
2 ; RUN: llc -mtriple=i386-pc-windows-msvc -print-after=finalize-isel -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-SELDAG
3 ; RUN: llc -mtriple=i386-pc-windows-msvc -print-after=finalize-isel -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-IR
44
55 ; DARWIN-SELDAG: # Machine code for function test_branch_weights:
66 ; DARWIN-SELDAG: successors: %bb.[[SUCCESS:[0-9]+]](0x7ffff800), %bb.[[FAILURE:[0-9]+]]
None ; RUN: llc -mtriple=x86_64-- -print-machineinstrs=expand-isel-pseudos %s -o /dev/null 2>&1 | FileCheck %s
0 ; RUN: llc -mtriple=x86_64-- -print-after=finalize-isel %s -o /dev/null 2>&1 | FileCheck %s
11
22 declare void @foo(i32)
33
275275 ; CHECK: successors: %bb.8(0x20000001), %bb.9(0x5fffffff)
276276 }
277277
278 !1 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10}
279 !2 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10}
280 !3 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10}
278 !1 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10}
279 !2 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10}
280 !3 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10}
0 ; RUN: llc -mtriple=i686-pc-gnu-linux < %s | FileCheck %s
1 ; RUN: llc -mtriple=i686-pc-gnu-linux -print-machineinstrs=expand-isel-pseudos %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=CHECK-JT-PROB
1 ; RUN: llc -mtriple=i686-pc-gnu-linux -print-after=finalize-isel %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=CHECK-JT-PROB
22
33
44 ; An unreachable default destination is ignored and no compare and branch
None ; RUN: llc -mtriple=x86_64-linux-gnu -stop-after=expand-isel-pseudos < %s | FileCheck %s
0 ; RUN: llc -mtriple=x86_64-linux-gnu -stop-after=finalize-isel < %s | FileCheck %s
11
22 define i32 @foo(i32 %n) !prof !1 {
33 entry:
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ;RUN: llc < %s -mtriple=i686 -mattr=sse4.1 -stop-after=expand-isel-pseudos 2>&1 | FileCheck %s
1 ;RUN: llc < %s -mtriple=i686 -mattr=sse4.1 -stop-after=finalize-isel 2>&1 | FileCheck %s
22
33 ; This test makes sure we discard pointer info when we combine a vector load
44 ; and a variable extractelement into a scalar load using an index. There's also
0 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=core-avx2 -stop-after expand-isel-pseudos -o - %s | FileCheck %s
1 ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=core-avx2 -stop-after finalize-isel -o - %s | FileCheck %s
22
33 declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)
44 declare <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)
None ; RUN: llc -stop-after=expand-isel-pseudos < %s | FileCheck %s
0 ; RUN: llc -stop-after=finalize-isel < %s | FileCheck %s
11 ;
22 ; Make sure that when the entry block of IR below is lowered, an instruction
33 ; that implictly defines $eflags has a same debug location with the icmp
None ; RUN: llc -mtriple=armv4t-unknown-unknown -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - %s | FileCheck %s
0 ; RUN: llc -mtriple=armv4t-unknown-unknown -start-after=codegenprepare -stop-before=finalize-isel -o - %s | FileCheck %s
11
22 ; Verify that a stack-referencing DBG_VALUE is emitted for p5 at the start of
33 ; the function.
0 ; FIXME: Fix machine verifier issues and remove -verify-machineinstrs=0. PR39452.
1 ; RUN: llc -stop-before=expand-isel-pseudos -pre-RA-sched=linearize -verify-machineinstrs=0 < %s | FileCheck %s
1 ; RUN: llc -stop-before=finalize-isel -pre-RA-sched=linearize -verify-machineinstrs=0 < %s | FileCheck %s
22 source_filename = "linear-dbg-value.ll"
33
44 ; Function Attrs: nounwind readonly uwtable
None ; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before=expand-isel-pseudos %s -o - | FileCheck %s
0 ; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before=finalize-isel %s -o - | FileCheck %s
11
22 ; Test the movement of dbg.values of arguments. SelectionDAG tries to be
33 ; helpful and places DBG_VALUEs of Arguments at the start of functions.
None ; RUN: llc -start-after=codegenprepare -stop-before=expand-isel-pseudos < %s -o - | FileCheck %s
0 ; RUN: llc -start-after=codegenprepare -stop-before=finalize-isel < %s -o - | FileCheck %s
11
22 ; Test that stack frame dbg.values are lowered to DBG_VALUEs, in blocks that
33 ; are local to the alloca, and elsewhere. Differs from dbg-value-frame-index.ll
None ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - %s | FileCheck %s
0 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=finalize-isel -o - %s | FileCheck %s
11
22 ; Input to this test looked like this and was compiled using: clang -g -O1 -mllvm -stop-after=codegenprepare -S
33 ;
None ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - %s | FileCheck %s
0 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=finalize-isel -o - %s | FileCheck %s
11
22 ; Test case was generated from the following C code,
33 ; using: clang -g -O1 -S -emit-llvm s.c -o s.ll
None ; RUN: llc -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - < %s | FileCheck %s
0 ; RUN: llc -start-after=codegenprepare -stop-before=finalize-isel -o - < %s | FileCheck %s
11 ; Test for correct placement of DBG_VALUE, which in PR40427 is placed before
22 ; the load instruction it refers to. The circumstance replicated here is where
33 ; two instructions in a row, trunc and add, begin with no-op Copy{To,From}Reg
0 ; Test dwarf codegen for DILocalVariable of a byval function argument that
11 ; points to neither an argument nor an alloca. This kind of IR is generated by
22 ; SafeStack for unsafe byval arguments.
3 ; RUN: llc -mtriple=x86_64-unknown-unknown -stop-after expand-isel-pseudos %s -o - | FileCheck %s
3 ; RUN: llc -mtriple=x86_64-unknown-unknown -stop-after finalize-isel %s -o - | FileCheck %s
44
55 ; This was built by compiling the following source with SafeStack and
66 ; simplifying the result a little.
None ; RUN: llc %s -stop-before expand-isel-pseudos -o - | FileCheck %s
0 ; RUN: llc %s -stop-before finalize-isel -o - | FileCheck %s
11
22 ;--------------------------------------------------------------------
33 ; This test case is basically generated from the following C code.
None ; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s
0 ; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s
11
22 ; This test case was generated from the following debug.c program,
33 ; using: clang debug.c -g -O1 -S -o dbg_value_phi_isel1.ll -emit-llvm
None ; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s
0 ; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s
11
22 ; This test case is a modified version of dbg_value_phi_isel1.ll
33 ; where the llvm.dbg.value nodes in for.body has been moved.
None ; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s
0 ; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s
11
22 ; This test case was generated from the following phi-split.c program,
33 ; using: clang phi-split.c -g -O1 -S -o - --target=i386 -emit-llvm
None ; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s
0 ; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s
11
22 ; This is a reproducer based on the test case from PR37321.
33
None ; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s
0 ; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s
11
22 ; Test that dbg.values of an SSA variable that's not used in a basic block,
33 ; is converted to a DBG_VALUE in that same basic block. We know that %1 is
None ; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before expand-isel-pseudos %s -o - | FileCheck %s
0 ; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before finalize-isel %s -o - | FileCheck %s
11
22 ; Test that the dbg.value for %baz, which doesn't exist in the 'next' bb,
33 ; can be salvaged back to the underlying argument vreg.