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Possible JT improvements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33733 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
1 changed file(s) with 43 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
1515 and cmp instructions can use high registers. Also, we can use them as
1616 temporaries to spill values into.
1717
18 * In thumb mode, short, byte, and bool preferred alignments are currently set
19 to 4 to accommodate ISA restriction (i.e. add sp, #imm, imm must be multiple
20 of 4).
21
22 //===---------------------------------------------------------------------===//
23
24 Potential jumptable improvements:
25
1826 * If we know function size is less than (1 << 16) * 2 bytes, we can use 16-bit
1927 jumptable entries (e.g. (L1 - L2) >> 1). Or even smaller entries if the
2028 function is even smaller. This also applies to ARM.
2129
22 * In thumb mode, short, byte, and bool preferred alignments are currently set
23 to 4 to accommodate ISA restriction (i.e. add sp, #imm, imm must be multiple
24 of 4).
30 * Thumb jumptable codegen can improve given some help from the assembler. This
31 is what we generate right now:
32
33 .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
34 LPCRELL0:
35 mov r1, #PCRELV0
36 add r1, pc
37 ldr r0, [r0, r1]
38 cpy pc, r0
39 .align 2
40 LJTI1_0_0:
41 .long LBB1_3
42 ...
43
44 Note there is another pc relative add that we can take advantage of.
45 add r1, pc, #imm_8 * 4
46
47 We should be able to generate:
48
49 LPCRELL0:
50 add r1, LJTI1_0_0
51 ldr r0, [r0, r1]
52 cpy pc, r0
53 .align 2
54 LJTI1_0_0:
55 .long LBB1_3
56
57 if the assembler can translate the add to:
58 add r1, pc, #((LJTI1_0_0-(LPCRELL0+4))&0xfffffffc)
59
60 Note the assembler also does something similar to constpool load:
61 LPCRELL0:
62 ldr r0, LCPI1_0
63 =>
64 ldr r0, pc, #((LCPI1_0-(LPCRELL0+4))&0xfffffffc)