llvm.org GIT mirror llvm / 5adfba2
whitespace git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130046 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Trick 9 years ago
2 changed file(s) with 8 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
8787 MEMBARRIER_MCR, // Memory barrier (MCR)
8888
8989 PRELOAD, // Preload
90
90
9191 VCEQ, // Vector compare equal.
9292 VCEQZ, // Vector compare equal to zero.
9393 VCGE, // Vector compare greater than or equal.
172172
173173 // Bit-field insert
174174 BFI,
175
175
176176 // Vector OR with immediate
177177 VORRIMM,
178178 // Vector AND with NOT of immediate
407407 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
408408 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
409409 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
410 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
410 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
411411 const ARMSubtarget *ST) const;
412412
413413 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
485485 unsigned BinOpcode) const;
486486
487487 };
488
488
489489 enum NEONModImmType {
490490 VMOVModImm,
491491 VMVNModImm,
492492 OtherModImm
493493 };
494
495
494
495
496496 namespace ARM {
497497 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
498498 }
3838 ; CHECK: f5
3939 ; CHECK: subs r0, #2
4040 ; CHECK: adc r1, r1, #-1448498775
41 %tmp = sub i64 %a, 6221254862626095106
41 %tmp = sub i64 %a, 6221254862626095106
4242 ret i64 %tmp
4343 }
4444
4747 ; CHECK: f6
4848 ; CHECK: subs r0, #2
4949 ; CHECK: sbc r1, r1, #66846720
50 %tmp = sub i64 %a, 287104476244869122
50 %tmp = sub i64 %a, 287104476244869122
5151 ret i64 %tmp
5252 }
5353