llvm.org GIT mirror llvm / 5ac981f
Merging r332103: ------------------------------------------------------------------------ r332103 | gberry | 2018-05-11 09:25:06 -0700 (Fri, 11 May 2018) | 24 lines [AArch64] Fix performPostLD1Combine to check for constant lane index. Summary: performPostLD1Combine in AArch64ISelLowering looks for vector insert_vector_elt of a loaded value which it can optimize into a single LD1LANE instruction. The code checking for the pattern was not checking if the lane index was a constant which could cause two problems: - an assert when lowering the LD1LANE ISD node since it assumes an constant operand - an assert in isel if the lane index value depends on the post-incremented base register Both of these issues are avoided by simply checking that the lane index is a constant. Fixes bug 35822. Reviewers: t.p.northover, javed.absar Subscribers: rengolin, kristof.beyls, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D46591 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@332158 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 years ago
2 changed file(s) with 32 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
96369636 if (LD->getOpcode() != ISD::LOAD)
96379637 return SDValue();
96389638
9639 // The vector lane must be a constant in the LD1LANE opcode.
9640 SDValue Lane;
9641 if (IsLaneOp) {
9642 Lane = N->getOperand(2);
9643 auto *LaneC = dyn_cast(Lane);
9644 if (!LaneC || LaneC->getZExtValue() >= VT.getVectorNumElements())
9645 return SDValue();
9646 }
9647
96399648 LoadSDNode *LoadSDN = cast(LD);
96409649 EVT MemVT = LoadSDN->getMemoryVT();
96419650 // Check if memory operand is the same type as the vector element.
96929701 Ops.push_back(LD->getOperand(0)); // Chain
96939702 if (IsLaneOp) {
96949703 Ops.push_back(Vector); // The vector to be inserted
9695 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
9704 Ops.push_back(Lane); // The lane to be inserted in the vector
96969705 }
96979706 Ops.push_back(Addr);
96989707 Ops.push_back(Inc);
2727 ret void
2828 }
2929
30 ; Avoid an assert/bad codegen in LD1LANEPOST lowering by not forming
31 ; LD1LANEPOST ISD nodes with a non-constant lane index.
32 define <4 x i32> @f2(i32 *%p, <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2, i32 %idx) {
33 %L0 = load i32, i32* %p
34 %p1 = getelementptr i32, i32* %p, i64 1
35 %L1 = load i32, i32* %p1
36 %v = select <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2
37 %vret = insertelement <4 x i32> %v, i32 %L0, i32 %idx
38 store i32 %L1, i32 *%p
39 ret <4 x i32> %vret
40 }
41
42 ; Check that a cycle is avoided during isel between the LD1LANEPOST instruction and the load of %L1.
43 define <4 x i32> @f3(i32 *%p, <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2) {
44 %L0 = load i32, i32* %p
45 %p1 = getelementptr i32, i32* %p, i64 1
46 %L1 = load i32, i32* %p1
47 %v = select <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2
48 %vret = insertelement <4 x i32> %v, i32 %L0, i32 %L1
49 ret <4 x i32> %vret
50 }
51
3052 ; Function Attrs: nounwind readnone
3153 declare i64 @llvm.objectsize.i64.p0i8(i8*, i1) #1
3254