llvm.org GIT mirror llvm / 5aa0834
[AArch64][SVE2] Asm: add integer pairwise arithmetic instructions Summary: Patch adds support for the following instructions: ADDP, SMAXP, UMAXP, SMINP, UMINP The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62128 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361229 91177308-0d34-0410-b5e6-96231b3b80d8 Cullen Rhodes 6 months ago
11 changed file(s) with 487 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
11261126 defm SADALP_ZPmZ : sve2_int_sadd_long_accum_pairwise<0, "sadalp">;
11271127 defm UADALP_ZPmZ : sve2_int_sadd_long_accum_pairwise<1, "uadalp">;
11281128
1129 // SVE2 integer pairwise arithmetic
1130 defm ADDP_ZPmZ : sve2_int_arith_pred<0b100011, "addp">;
1131 defm SMAXP_ZPmZ : sve2_int_arith_pred<0b101001, "smaxp">;
1132 defm UMAXP_ZPmZ : sve2_int_arith_pred<0b101011, "umaxp">;
1133 defm SMINP_ZPmZ : sve2_int_arith_pred<0b101101, "sminp">;
1134 defm UMINP_ZPmZ : sve2_int_arith_pred<0b101111, "uminp">;
1135
11291136 // SVE2 integer multiply long
11301137 defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">;
11311138 defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">;
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
1
2 // --------------------------------------------------------------------------//
3 // Source and Destination Registers must match
4
5 addp z0.b, p0/m, z1.b, z2.b
6 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
7 // CHECK-NEXT: addp z0.b, p0/m, z1.b, z2.b
8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9
10
11 // --------------------------------------------------------------------------//
12 // Element sizes must match
13
14 addp z0.b, p0/m, z0.d, z1.d
15 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
16 // CHECK-NEXT: addp z0.b, p0/m, z0.d, z1.d
17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18
19 addp z0.b, p0/m, z0.b, z1.h
20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
21 // CHECK-NEXT: addp z0.b, p0/m, z0.b, z1.h
22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24
25 // --------------------------------------------------------------------------//
26 // Invalid predicate
27
28 addp z0.b, p0/z, z0.b, z1.b
29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30 // CHECK-NEXT: addp z0.b, p0/z, z0.b, z1.b
31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32
33 addp z0.b, p8/m, z0.b, z1.b
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
35 // CHECK-NEXT: addp z0.b, p8/m, z0.b, z1.b
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
1 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
2 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
3 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
7 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
8
9 addp z0.b, p0/m, z0.b, z1.b
10 // CHECK-INST: addp z0.b, p0/m, z0.b, z1.b
11 // CHECK-ENCODING: [0x20,0xa0,0x11,0x44]
12 // CHECK-ERROR: instruction requires: sve2
13 // CHECK-UNKNOWN: 20 a0 11 44
14
15 addp z0.h, p0/m, z0.h, z1.h
16 // CHECK-INST: addp z0.h, p0/m, z0.h, z1.h
17 // CHECK-ENCODING: [0x20,0xa0,0x51,0x44]
18 // CHECK-ERROR: instruction requires: sve2
19 // CHECK-UNKNOWN: 20 a0 51 44
20
21 addp z29.s, p7/m, z29.s, z30.s
22 // CHECK-INST: addp z29.s, p7/m, z29.s, z30.s
23 // CHECK-ENCODING: [0xdd,0xbf,0x91,0x44]
24 // CHECK-ERROR: instruction requires: sve2
25 // CHECK-UNKNOWN: dd bf 91 44
26
27 addp z31.d, p7/m, z31.d, z30.d
28 // CHECK-INST: addp z31.d, p7/m, z31.d, z30.d
29 // CHECK-ENCODING: [0xdf,0xbf,0xd1,0x44]
30 // CHECK-ERROR: instruction requires: sve2
31 // CHECK-UNKNOWN: df bf d1 44
32
33 // --------------------------------------------------------------------------//
34 // Test compatibility with MOVPRFX instruction.
35
36 movprfx z31.d, p0/z, z6.d
37 // CHECK-INST: movprfx z31.d, p0/z, z6.d
38 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
39 // CHECK-ERROR: instruction requires: sve
40 // CHECK-UNKNOWN: df 20 d0 04
41
42 addp z31.d, p0/m, z31.d, z30.d
43 // CHECK-INST: addp z31.d, p0/m, z31.d, z30.d
44 // CHECK-ENCODING: [0xdf,0xa3,0xd1,0x44]
45 // CHECK-ERROR: instruction requires: sve2
46 // CHECK-UNKNOWN: df a3 d1 44
47
48 movprfx z31, z6
49 // CHECK-INST: movprfx z31, z6
50 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
51 // CHECK-ERROR: instruction requires: sve
52 // CHECK-UNKNOWN: df bc 20 04
53
54 addp z31.d, p7/m, z31.d, z30.d
55 // CHECK-INST: addp z31.d, p7/m, z31.d, z30.d
56 // CHECK-ENCODING: [0xdf,0xbf,0xd1,0x44]
57 // CHECK-ERROR: instruction requires: sve2
58 // CHECK-UNKNOWN: df bf d1 44
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
1
2 // --------------------------------------------------------------------------//
3 // Source and Destination Registers must match
4
5 smaxp z0.b, p0/m, z1.b, z2.b
6 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
7 // CHECK-NEXT: smaxp z0.b, p0/m, z1.b, z2.b
8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9
10
11 // --------------------------------------------------------------------------//
12 // Element sizes must match
13
14 smaxp z0.b, p0/m, z0.d, z1.d
15 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
16 // CHECK-NEXT: smaxp z0.b, p0/m, z0.d, z1.d
17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18
19 smaxp z0.b, p0/m, z0.b, z1.h
20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
21 // CHECK-NEXT: smaxp z0.b, p0/m, z0.b, z1.h
22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24
25 // --------------------------------------------------------------------------//
26 // Invalid predicate
27
28 smaxp z0.b, p0/z, z0.b, z1.b
29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30 // CHECK-NEXT: smaxp z0.b, p0/z, z0.b, z1.b
31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32
33 smaxp z0.b, p8/m, z0.b, z1.b
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
35 // CHECK-NEXT: smaxp z0.b, p8/m, z0.b, z1.b
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
1 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
2 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
3 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
7 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
8
9 smaxp z0.b, p0/m, z0.b, z1.b
10 // CHECK-INST: smaxp z0.b, p0/m, z0.b, z1.b
11 // CHECK-ENCODING: [0x20,0xa0,0x14,0x44]
12 // CHECK-ERROR: instruction requires: sve2
13 // CHECK-UNKNOWN: 20 a0 14 44
14
15 smaxp z0.h, p0/m, z0.h, z1.h
16 // CHECK-INST: smaxp z0.h, p0/m, z0.h, z1.h
17 // CHECK-ENCODING: [0x20,0xa0,0x54,0x44]
18 // CHECK-ERROR: instruction requires: sve2
19 // CHECK-UNKNOWN: 20 a0 54 44
20
21 smaxp z29.s, p7/m, z29.s, z30.s
22 // CHECK-INST: smaxp z29.s, p7/m, z29.s, z30.s
23 // CHECK-ENCODING: [0xdd,0xbf,0x94,0x44]
24 // CHECK-ERROR: instruction requires: sve2
25 // CHECK-UNKNOWN: dd bf 94 44
26
27 smaxp z31.d, p7/m, z31.d, z30.d
28 // CHECK-INST: smaxp z31.d, p7/m, z31.d, z30.d
29 // CHECK-ENCODING: [0xdf,0xbf,0xd4,0x44]
30 // CHECK-ERROR: instruction requires: sve2
31 // CHECK-UNKNOWN: df bf d4 44
32
33 // --------------------------------------------------------------------------//
34 // Test compatibility with MOVPRFX instruction.
35
36 movprfx z31.d, p0/z, z6.d
37 // CHECK-INST: movprfx z31.d, p0/z, z6.d
38 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
39 // CHECK-ERROR: instruction requires: sve
40 // CHECK-UNKNOWN: df 20 d0 04
41
42 smaxp z31.d, p0/m, z31.d, z30.d
43 // CHECK-INST: smaxp z31.d, p0/m, z31.d, z30.d
44 // CHECK-ENCODING: [0xdf,0xa3,0xd4,0x44]
45 // CHECK-ERROR: instruction requires: sve2
46 // CHECK-UNKNOWN: df a3 d4 44
47
48 movprfx z31, z6
49 // CHECK-INST: movprfx z31, z6
50 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
51 // CHECK-ERROR: instruction requires: sve
52 // CHECK-UNKNOWN: df bc 20 04
53
54 smaxp z31.d, p7/m, z31.d, z30.d
55 // CHECK-INST: smaxp z31.d, p7/m, z31.d, z30.d
56 // CHECK-ENCODING: [0xdf,0xbf,0xd4,0x44]
57 // CHECK-ERROR: instruction requires: sve2
58 // CHECK-UNKNOWN: df bf d4 44
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
1
2 // --------------------------------------------------------------------------//
3 // Source and Destination Registers must match
4
5 sminp z0.b, p0/m, z1.b, z2.b
6 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
7 // CHECK-NEXT: sminp z0.b, p0/m, z1.b, z2.b
8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9
10
11 // --------------------------------------------------------------------------//
12 // Element sizes must match
13
14 sminp z0.b, p0/m, z0.d, z1.d
15 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
16 // CHECK-NEXT: sminp z0.b, p0/m, z0.d, z1.d
17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18
19 sminp z0.b, p0/m, z0.b, z1.h
20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
21 // CHECK-NEXT: sminp z0.b, p0/m, z0.b, z1.h
22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24
25 // --------------------------------------------------------------------------//
26 // Invalid predicate
27
28 sminp z0.b, p0/z, z0.b, z1.b
29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30 // CHECK-NEXT: sminp z0.b, p0/z, z0.b, z1.b
31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32
33 sminp z0.b, p8/m, z0.b, z1.b
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
35 // CHECK-NEXT: sminp z0.b, p8/m, z0.b, z1.b
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
1 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
2 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
3 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
7 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
8
9 sminp z0.b, p0/m, z0.b, z1.b
10 // CHECK-INST: sminp z0.b, p0/m, z0.b, z1.b
11 // CHECK-ENCODING: [0x20,0xa0,0x16,0x44]
12 // CHECK-ERROR: instruction requires: sve2
13 // CHECK-UNKNOWN: 20 a0 16 44
14
15 sminp z0.h, p0/m, z0.h, z1.h
16 // CHECK-INST: sminp z0.h, p0/m, z0.h, z1.h
17 // CHECK-ENCODING: [0x20,0xa0,0x56,0x44]
18 // CHECK-ERROR: instruction requires: sve2
19 // CHECK-UNKNOWN: 20 a0 56 44
20
21 sminp z29.s, p7/m, z29.s, z30.s
22 // CHECK-INST: sminp z29.s, p7/m, z29.s, z30.s
23 // CHECK-ENCODING: [0xdd,0xbf,0x96,0x44]
24 // CHECK-ERROR: instruction requires: sve2
25 // CHECK-UNKNOWN: dd bf 96 44
26
27 sminp z31.d, p7/m, z31.d, z30.d
28 // CHECK-INST: sminp z31.d, p7/m, z31.d, z30.d
29 // CHECK-ENCODING: [0xdf,0xbf,0xd6,0x44]
30 // CHECK-ERROR: instruction requires: sve2
31 // CHECK-UNKNOWN: df bf d6 44
32
33 // --------------------------------------------------------------------------//
34 // Test compatibility with MOVPRFX instruction.
35
36 movprfx z31.d, p0/z, z6.d
37 // CHECK-INST: movprfx z31.d, p0/z, z6.d
38 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
39 // CHECK-ERROR: instruction requires: sve
40 // CHECK-UNKNOWN: df 20 d0 04
41
42 sminp z31.d, p0/m, z31.d, z30.d
43 // CHECK-INST: sminp z31.d, p0/m, z31.d, z30.d
44 // CHECK-ENCODING: [0xdf,0xa3,0xd6,0x44]
45 // CHECK-ERROR: instruction requires: sve2
46 // CHECK-UNKNOWN: df a3 d6 44
47
48 movprfx z31, z6
49 // CHECK-INST: movprfx z31, z6
50 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
51 // CHECK-ERROR: instruction requires: sve
52 // CHECK-UNKNOWN: df bc 20 04
53
54 sminp z31.d, p7/m, z31.d, z30.d
55 // CHECK-INST: sminp z31.d, p7/m, z31.d, z30.d
56 // CHECK-ENCODING: [0xdf,0xbf,0xd6,0x44]
57 // CHECK-ERROR: instruction requires: sve2
58 // CHECK-UNKNOWN: df bf d6 44
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
1
2 // --------------------------------------------------------------------------//
3 // Source and Destination Registers must match
4
5 umaxp z0.b, p0/m, z1.b, z2.b
6 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
7 // CHECK-NEXT: umaxp z0.b, p0/m, z1.b, z2.b
8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9
10
11 // --------------------------------------------------------------------------//
12 // Element sizes must match
13
14 umaxp z0.b, p0/m, z0.d, z1.d
15 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
16 // CHECK-NEXT: umaxp z0.b, p0/m, z0.d, z1.d
17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18
19 umaxp z0.b, p0/m, z0.b, z1.h
20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
21 // CHECK-NEXT: umaxp z0.b, p0/m, z0.b, z1.h
22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24
25 // --------------------------------------------------------------------------//
26 // Invalid predicate
27
28 umaxp z0.b, p0/z, z0.b, z1.b
29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30 // CHECK-NEXT: umaxp z0.b, p0/z, z0.b, z1.b
31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32
33 umaxp z0.b, p8/m, z0.b, z1.b
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
35 // CHECK-NEXT: umaxp z0.b, p8/m, z0.b, z1.b
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
1 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
2 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
3 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
7 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
8
9 umaxp z0.b, p0/m, z0.b, z1.b
10 // CHECK-INST: umaxp z0.b, p0/m, z0.b, z1.b
11 // CHECK-ENCODING: [0x20,0xa0,0x15,0x44]
12 // CHECK-ERROR: instruction requires: sve2
13 // CHECK-UNKNOWN: 20 a0 15 44
14
15 umaxp z0.h, p0/m, z0.h, z1.h
16 // CHECK-INST: umaxp z0.h, p0/m, z0.h, z1.h
17 // CHECK-ENCODING: [0x20,0xa0,0x55,0x44]
18 // CHECK-ERROR: instruction requires: sve2
19 // CHECK-UNKNOWN: 20 a0 55 44
20
21 umaxp z29.s, p7/m, z29.s, z30.s
22 // CHECK-INST: umaxp z29.s, p7/m, z29.s, z30.s
23 // CHECK-ENCODING: [0xdd,0xbf,0x95,0x44]
24 // CHECK-ERROR: instruction requires: sve2
25 // CHECK-UNKNOWN: dd bf 95 44
26
27 umaxp z31.d, p7/m, z31.d, z30.d
28 // CHECK-INST: umaxp z31.d, p7/m, z31.d, z30.d
29 // CHECK-ENCODING: [0xdf,0xbf,0xd5,0x44]
30 // CHECK-ERROR: instruction requires: sve2
31 // CHECK-UNKNOWN: df bf d5 44
32
33 // --------------------------------------------------------------------------//
34 // Test compatibility with MOVPRFX instruction.
35
36 movprfx z31.d, p0/z, z6.d
37 // CHECK-INST: movprfx z31.d, p0/z, z6.d
38 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
39 // CHECK-ERROR: instruction requires: sve
40 // CHECK-UNKNOWN: df 20 d0 04
41
42 umaxp z31.d, p0/m, z31.d, z30.d
43 // CHECK-INST: umaxp z31.d, p0/m, z31.d, z30.d
44 // CHECK-ENCODING: [0xdf,0xa3,0xd5,0x44]
45 // CHECK-ERROR: instruction requires: sve2
46 // CHECK-UNKNOWN: df a3 d5 44
47
48 movprfx z31, z6
49 // CHECK-INST: movprfx z31, z6
50 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
51 // CHECK-ERROR: instruction requires: sve
52 // CHECK-UNKNOWN: df bc 20 04
53
54 umaxp z31.d, p7/m, z31.d, z30.d
55 // CHECK-INST: umaxp z31.d, p7/m, z31.d, z30.d
56 // CHECK-ENCODING: [0xdf,0xbf,0xd5,0x44]
57 // CHECK-ERROR: instruction requires: sve2
58 // CHECK-UNKNOWN: df bf d5 44
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
1
2 // --------------------------------------------------------------------------//
3 // Source and Destination Registers must match
4
5 uminp z0.b, p0/m, z1.b, z2.b
6 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
7 // CHECK-NEXT: uminp z0.b, p0/m, z1.b, z2.b
8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9
10
11 // --------------------------------------------------------------------------//
12 // Element sizes must match
13
14 uminp z0.b, p0/m, z0.d, z1.d
15 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
16 // CHECK-NEXT: uminp z0.b, p0/m, z0.d, z1.d
17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18
19 uminp z0.b, p0/m, z0.b, z1.h
20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
21 // CHECK-NEXT: uminp z0.b, p0/m, z0.b, z1.h
22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24
25 // --------------------------------------------------------------------------//
26 // Invalid predicate
27
28 uminp z0.b, p0/z, z0.b, z1.b
29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30 // CHECK-NEXT: uminp z0.b, p0/z, z0.b, z1.b
31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32
33 uminp z0.b, p8/m, z0.b, z1.b
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
35 // CHECK-NEXT: uminp z0.b, p8/m, z0.b, z1.b
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
1 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
2 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
3 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
7 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
8
9 uminp z0.b, p0/m, z0.b, z1.b
10 // CHECK-INST: uminp z0.b, p0/m, z0.b, z1.b
11 // CHECK-ENCODING: [0x20,0xa0,0x17,0x44]
12 // CHECK-ERROR: instruction requires: sve2
13 // CHECK-UNKNOWN: 20 a0 17 44
14
15 uminp z0.h, p0/m, z0.h, z1.h
16 // CHECK-INST: uminp z0.h, p0/m, z0.h, z1.h
17 // CHECK-ENCODING: [0x20,0xa0,0x57,0x44]
18 // CHECK-ERROR: instruction requires: sve2
19 // CHECK-UNKNOWN: 20 a0 57 44
20
21 uminp z29.s, p7/m, z29.s, z30.s
22 // CHECK-INST: uminp z29.s, p7/m, z29.s, z30.s
23 // CHECK-ENCODING: [0xdd,0xbf,0x97,0x44]
24 // CHECK-ERROR: instruction requires: sve2
25 // CHECK-UNKNOWN: dd bf 97 44
26
27 uminp z31.d, p7/m, z31.d, z30.d
28 // CHECK-INST: uminp z31.d, p7/m, z31.d, z30.d
29 // CHECK-ENCODING: [0xdf,0xbf,0xd7,0x44]
30 // CHECK-ERROR: instruction requires: sve2
31 // CHECK-UNKNOWN: df bf d7 44
32
33 // --------------------------------------------------------------------------//
34 // Test compatibility with MOVPRFX instruction.
35
36 movprfx z31.d, p0/z, z6.d
37 // CHECK-INST: movprfx z31.d, p0/z, z6.d
38 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
39 // CHECK-ERROR: instruction requires: sve
40 // CHECK-UNKNOWN: df 20 d0 04
41
42 uminp z31.d, p0/m, z31.d, z30.d
43 // CHECK-INST: uminp z31.d, p0/m, z31.d, z30.d
44 // CHECK-ENCODING: [0xdf,0xa3,0xd7,0x44]
45 // CHECK-ERROR: instruction requires: sve2
46 // CHECK-UNKNOWN: df a3 d7 44
47
48 movprfx z31, z6
49 // CHECK-INST: movprfx z31, z6
50 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
51 // CHECK-ERROR: instruction requires: sve
52 // CHECK-UNKNOWN: df bc 20 04
53
54 uminp z31.d, p7/m, z31.d, z30.d
55 // CHECK-INST: uminp z31.d, p7/m, z31.d, z30.d
56 // CHECK-ENCODING: [0xdf,0xbf,0xd7,0x44]
57 // CHECK-ERROR: instruction requires: sve2
58 // CHECK-UNKNOWN: df bf d7 44