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[PowerPC] Basic support for P9 atomic loads and stores This patch corresponds to review: http://reviews.llvm.org/D18032 This patch provides asm implementation for the following instructions: lwat, ldat, stwat, stdat, ldmx, mcrxrx git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265022 91177308-0d34-0410-b5e6-96231b3b80d8 Nemanja Ivanovic 4 years ago
11 changed file(s) with 108 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
162162 def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
163163 "Treat vector data stream cache control instructions as deprecated">;
164164
165 def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
166 "true",
167 "Enable instructions added in ISA 3.0.">;
168
165169 /* Since new processors generally contain a superset of features of those that
166170 came before them, the idea is to make implementations of new processors
167171 less error prone and easier to read.
243243 // (EH=1 - see Power ISA 2.07 Book II 4.4.2)
244244 def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
245245 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT;
246
247 let hasExtraDefRegAllocReq = 1 in
248 def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
249 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64,
250 Requires<[IsISA3_0]>;
246251 }
247252
248253 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in
249254 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
250255 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT;
256
257 let mayStore = 1, hasSideEffects = 0 in
258 def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC),
259 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64,
260 Requires<[IsISA3_0]>;
251261
252262 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
253263 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
904914 "ldux $rD, $addr", IIC_LdStLDUX,
905915 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
906916 NoEncode<"$ea_result">, isPPC64;
917
918 def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src),
919 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64,
920 Requires<[IsISA3_0]>;
907921 }
908922 }
909923
797797 let Inst{13-20} = IMM8;
798798 let Inst{21-30} = xo;
799799 let Inst{31} = XT{5};
800 }
801
802 // XForm_base_r3xo for instructions such as P9 atomics where we don't want
803 // to specify an SDAG pattern for matching.
804 class X_RD5_RS5_IM5 opcode, bits<10> xo, dag OOL, dag IOL,
805 string asmstr, InstrItinClass itin>
806 : XForm_base_r3xo {
807 }
808
809 class X_BF3 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
810 InstrItinClass itin>
811 : XForm_17 {
812 let FRA = 0;
813 let FRB = 0;
800814 }
801815
802816 // XX*-Form (VSX)
776776 def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">;
777777 def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
778778 def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
779 def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">;
779780
780781 //===----------------------------------------------------------------------===//
781782 // PowerPC Multiclass Definitions.
15731574
15741575 def LWARXL : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
15751576 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
1577
1578 // The atomic instructions use the destination register as well as the next one
1579 // or two registers in order (modulo 31).
1580 let hasExtraSrcRegAllocReq = 1 in
1581 def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
1582 "lwat $rD, $rA, $FC", IIC_LdStLoad>,
1583 Requires<[IsISA3_0]>;
15761584 }
15771585
15781586 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
15871595 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
15881596 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
15891597 }
1598
1599 let mayStore = 1, hasSideEffects = 0 in
1600 def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
1601 "stwat $rS, $rA, $FC", IIC_LdStStore>,
1602 Requires<[IsISA3_0]>;
15901603
15911604 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
15921605 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
23582371 "mfcr $rT", IIC_SprMFCR>,
23592372 PPC970_MicroCode, PPC970_Unit_CRU;
23602373 } // hasExtraSrcRegAllocReq = 1
2374
2375 def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
2376 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
23612377 } // hasSideEffects = 0
23622378
23632379 // Pseudo instruction to perform FADD in round-to-zero mode.
103103 HasHTM = false;
104104 HasFusion = false;
105105 HasFloat128 = false;
106 IsISA3_0 = false;
106107
107108 HasPOPCNTD = POPCNTD_Unavailable;
108109 }
129129 bool HasHTM;
130130 bool HasFusion;
131131 bool HasFloat128;
132 bool IsISA3_0;
132133
133134 POPCNTDKind HasPOPCNTD;
134135
271272 bool hasHTM() const { return HasHTM; }
272273 bool hasFusion() const { return HasFusion; }
273274 bool hasFloat128() const { return HasFloat128; }
275 bool isISA3_0() const { return IsISA3_0; }
274276
275277 POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
276278
557557 - Load Vector Word & Splat Indexed: lxvwsx
558558 . Likely needs an intrinsic
559559 . (set v?:$XT, (int_ppc_vsx_lxvwsx xoaddr:$src))
560
561 Atomic operations (l[dw]at, st[dw]at):
562 - Provide custom lowering for common atomic operations to use these
563 instructions with the correct Function Code
564 - Ensure the operands are in the correct register (i.e. RT+1, RT+2)
565 - Provide builtins since not all FC's necessarily have an existing LLVM
566 atomic operation
567
568 Load Doubleword Monitored (ldmx):
569 - Investigate whether there are any uses for this. It seems to be related to
570 Garbage Collection so it isn't likely to be all that useful for most
571 languages we deal with.
572
573 Move to CR from XER Extended (mcrxrx):
574 - Is there a use for this in LLVM?
3131
3232 # CHECK: stdcx. 2, 3, 4
3333 0x7c 0x43 0x21 0xad
34
35 # CHECK: stwat 2, 3, 28
36 0x7c 0x43 0xe5 0x8c
37
38 # CHECK: stdat 2, 3, 28
39 0x7c 0x43 0xe5 0xcc
3440
3541 # CHECK: ptesync
3642 0x7c 0x40 0x04 0xac
7177 # CHECK: ldarx 2, 3, 4, 1
7278 0x7c 0x43 0x20 0xa9
7379
80 # CHECK: lwat 2, 3, 28
81 0x7c 0x43 0xe4 0x8c
82
83 # CHECK: ldat 2, 3, 28
84 0x7c 0x43 0xe4 0xcc
85
7486 # CHECK: sync
7587 0x7c 0x00 0x04 0xac
7688
150150 # CHECK: ldux 2, 3, 4
151151 0x7c 0x43 0x20 0x6a
152152
153 # CHECK: ldmx 2, 3, 4
154 0x7c 0x43 0x22 0x6a
155
153156 # CHECK: stb 2, 128(4)
154157 0x98 0x44 0x00 0x80
155158
657660 # CHECK: mfocrf 16, 8
658661 0x7e 0x10 0x80 0x26
659662
663 # CHECK: mcrxrx 7
664 0x7f 0x80 0x04 0x80
665
660666 # CHECK: mtsrin 10, 12
661667 0x7d 0x40 0x61 0xe4
668
662669 # CHECK: mfsrin 10, 12
663670 0x7d 0x40 0x65 0x26
7272 # CHECK-BE: stwcx. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x2d]
7373 # CHECK-LE: stwcx. 2, 3, 4 # encoding: [0x2d,0x21,0x43,0x7c]
7474 stwcx. 2, 3, 4
75
7576 # CHECK-BE: stdcx. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xad]
7677 # CHECK-LE: stdcx. 2, 3, 4 # encoding: [0xad,0x21,0x43,0x7c]
7778 stdcx. 2, 3, 4
79
80 # CHECK-BE: stwat 2, 3, 28 # encoding: [0x7c,0x43,0xe5,0x8c]
81 # CHECK-LE: stwat 2, 3, 28 # encoding: [0x8c,0xe5,0x43,0x7c]
82 stwat 2, 3, 28
83
84 # CHECK-BE: stdat 2, 3, 28 # encoding: [0x7c,0x43,0xe5,0xcc]
85 # CHECK-LE: stdat 2, 3, 28 # encoding: [0xcc,0xe5,0x43,0x7c]
86 stdat 2, 3, 28
7887
7988 # CHECK-BE: ptesync # encoding: [0x7c,0x40,0x04,0xac]
8089 # CHECK-LE: ptesync # encoding: [0xac,0x04,0x40,0x7c]
130139 # CHECK-LE: ldarx 2, 3, 4, 1 # encoding: [0xa9,0x20,0x43,0x7c]
131140 ldarx 2, 3, 4, 1
132141
142 # CHECK-BE: lwat 2, 3, 28 # encoding: [0x7c,0x43,0xe4,0x8c]
143 # CHECK-LE: lwat 2, 3, 28 # encoding: [0x8c,0xe4,0x43,0x7c]
144 lwat 2, 3, 28
145
146 # CHECK-BE: ldat 2, 3, 28 # encoding: [0x7c,0x43,0xe4,0xcc]
147 # CHECK-LE: ldat 2, 3, 28 # encoding: [0xcc,0xe4,0x43,0x7c]
148 ldat 2, 3, 28
149
133150 # CHECK-BE: sync # encoding: [0x7c,0x00,0x04,0xac]
134151 # CHECK-LE: sync # encoding: [0xac,0x04,0x00,0x7c]
135152 sync
196196 # CHECK-BE: ldux 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x6a]
197197 # CHECK-LE: ldux 2, 3, 4 # encoding: [0x6a,0x20,0x43,0x7c]
198198 ldux 2, 3, 4
199 # CHECK-BE: ldmx 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x6a]
200 # CHECK-LE: ldmx 2, 3, 4 # encoding: [0x6a,0x22,0x43,0x7c]
201 ldmx 2, 3, 4
199202
200203 # Fixed-point store instructions
201204
832835 # CHECK-BE: mfocrf 16, 8 # encoding: [0x7e,0x10,0x80,0x26]
833836 # CHECK-LE: mfocrf 16, 8 # encoding: [0x26,0x80,0x10,0x7e]
834837 mfocrf 16, 8
838 # CHECK-BE: mcrxrx 7 # encoding: [0x7f,0x80,0x04,0x80]
839 # CHECK-LE: mcrxrx 7 # encoding: [0x80,0x04,0x80,0x7f]
840 mcrxrx 7
835841
836842 # Move to/from segment register
837843 # CHECK-BE: mtsr 12, 10 # encoding: [0x7d,0x4c,0x01,0xa4]