llvm.org GIT mirror llvm / 5a675ff
[TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.h As it stands, the OperandMatchResultTy is only included in the generated header if there is custom operand parsing. However, almost all backends make use of MatchOperand_Success and friends from OperandMatchResultTy for e.g. parseRegister. This is a pain when starting an AsmParser for a new backend that doesn't yet have custom operand parsing. Move the enum to MCTargetAsmParser.h. This patch is a prerequisite for D23563 Differential Revision: https://reviews.llvm.org/D23496 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285705 91177308-0d34-0410-b5e6-96231b3b80d8 Alex Bradbury 2 years ago
10 changed file(s) with 84 addition(s) and 85 deletion(s). Raw diff Collapse all Expand all
7979 ParseInstructionInfo() : AsmRewrites(nullptr) {}
8080 ParseInstructionInfo(SmallVectorImpl *rewrites)
8181 : AsmRewrites(rewrites) {}
82 };
83
84 enum OperandMatchResultTy {
85 MatchOperand_Success, // operand matched successfully
86 MatchOperand_NoMatch, // operand did not match
87 MatchOperand_ParseFail // operand matched but had errors
8288 };
8389
8490 /// MCTargetAsmParser - Generic interface to target specific assembly parsers.
20252025 }
20262026
20272027 /// tryParseSysCROperand - Try to parse a system instruction CR operand name.
2028 AArch64AsmParser::OperandMatchResultTy
2028 OperandMatchResultTy
20292029 AArch64AsmParser::tryParseSysCROperand(OperandVector &Operands) {
20302030 MCAsmParser &Parser = getParser();
20312031 SMLoc S = getLoc();
20552055 }
20562056
20572057 /// tryParsePrefetch - Try to parse a prefetch operand.
2058 AArch64AsmParser::OperandMatchResultTy
2058 OperandMatchResultTy
20592059 AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) {
20602060 MCAsmParser &Parser = getParser();
20612061 SMLoc S = getLoc();
21042104 }
21052105
21062106 /// tryParsePSBHint - Try to parse a PSB operand, mapped to Hint command
2107 AArch64AsmParser::OperandMatchResultTy
2107 OperandMatchResultTy
21082108 AArch64AsmParser::tryParsePSBHint(OperandVector &Operands) {
21092109 MCAsmParser &Parser = getParser();
21102110 SMLoc S = getLoc();
21282128
21292129 /// tryParseAdrpLabel - Parse and validate a source label for the ADRP
21302130 /// instruction.
2131 AArch64AsmParser::OperandMatchResultTy
2131 OperandMatchResultTy
21322132 AArch64AsmParser::tryParseAdrpLabel(OperandVector &Operands) {
21332133 MCAsmParser &Parser = getParser();
21342134 SMLoc S = getLoc();
21792179
21802180 /// tryParseAdrLabel - Parse and validate a source label for the ADR
21812181 /// instruction.
2182 AArch64AsmParser::OperandMatchResultTy
2182 OperandMatchResultTy
21832183 AArch64AsmParser::tryParseAdrLabel(OperandVector &Operands) {
21842184 MCAsmParser &Parser = getParser();
21852185 SMLoc S = getLoc();
21992199 }
22002200
22012201 /// tryParseFPImm - A floating point immediate expression operand.
2202 AArch64AsmParser::OperandMatchResultTy
2202 OperandMatchResultTy
22032203 AArch64AsmParser::tryParseFPImm(OperandVector &Operands) {
22042204 MCAsmParser &Parser = getParser();
22052205 SMLoc S = getLoc();
22632263 }
22642264
22652265 /// tryParseAddSubImm - Parse ADD/SUB shifted immediate operand
2266 AArch64AsmParser::OperandMatchResultTy
2266 OperandMatchResultTy
22672267 AArch64AsmParser::tryParseAddSubImm(OperandVector &Operands) {
22682268 MCAsmParser &Parser = getParser();
22692269 SMLoc S = getLoc();
23812381
23822382 /// tryParseOptionalShift - Some operands take an optional shift argument. Parse
23832383 /// them if present.
2384 AArch64AsmParser::OperandMatchResultTy
2384 OperandMatchResultTy
23852385 AArch64AsmParser::tryParseOptionalShiftExtend(OperandVector &Operands) {
23862386 MCAsmParser &Parser = getParser();
23872387 const AsmToken &Tok = Parser.getTok();
27212721 return false;
27222722 }
27232723
2724 AArch64AsmParser::OperandMatchResultTy
2724 OperandMatchResultTy
27252725 AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
27262726 MCAsmParser &Parser = getParser();
27272727 const AsmToken &Tok = Parser.getTok();
27752775 return MatchOperand_Success;
27762776 }
27772777
2778 AArch64AsmParser::OperandMatchResultTy
2778 OperandMatchResultTy
27792779 AArch64AsmParser::tryParseSysReg(OperandVector &Operands) {
27802780 MCAsmParser &Parser = getParser();
27812781 const AsmToken &Tok = Parser.getTok();
30743074 return false;
30753075 }
30763076
3077 AArch64AsmParser::OperandMatchResultTy
3077 OperandMatchResultTy
30783078 AArch64AsmParser::tryParseGPR64sp0Operand(OperandVector &Operands) {
30793079 MCAsmParser &Parser = getParser();
30803080 const AsmToken &Tok = Parser.getTok();
46344634 }
46354635
46364636
4637 AArch64AsmParser::OperandMatchResultTy
4637 OperandMatchResultTy
46384638 AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
46394639
46404640 SMLoc S = getLoc();
11981198 return AMDGPUOperand::CreateReg(this, Reg, StartLoc, EndLoc, false);
11991199 }
12001200
1201 AMDGPUAsmParser::OperandMatchResultTy
1201 OperandMatchResultTy
12021202 AMDGPUAsmParser::parseImm(OperandVector &Operands) {
12031203 // TODO: add syntactic sugar for 1/(2*PI)
12041204 bool Minus = false;
12361236 }
12371237 }
12381238
1239 AMDGPUAsmParser::OperandMatchResultTy
1239 OperandMatchResultTy
12401240 AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands) {
12411241 auto res = parseImm(Operands);
12421242 if (res != MatchOperand_NoMatch) {
12521252 return MatchOperand_ParseFail;
12531253 }
12541254
1255 AMDGPUAsmParser::OperandMatchResultTy
1255 OperandMatchResultTy
12561256 AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands) {
12571257 // XXX: During parsing we can't determine if minus sign means
12581258 // negate-modifier or negative immediate value.
13161316 return MatchOperand_Success;
13171317 }
13181318
1319 AMDGPUAsmParser::OperandMatchResultTy
1319 OperandMatchResultTy
13201320 AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands) {
13211321 bool Sext = false;
13221322
17121712 return true;
17131713 }
17141714
1715 AMDGPUAsmParser::OperandMatchResultTy
1715 OperandMatchResultTy
17161716 AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
17171717
17181718 // Try to parse with a custom parser
17841784 Operands.push_back(AMDGPUOperand::CreateToken(this, Name, NameLoc));
17851785
17861786 while (!getLexer().is(AsmToken::EndOfStatement)) {
1787 AMDGPUAsmParser::OperandMatchResultTy Res = parseOperand(Operands, Name);
1787 OperandMatchResultTy Res = parseOperand(Operands, Name);
17881788
17891789 // Eat the comma or space if there is one.
17901790 if (getLexer().is(AsmToken::Comma))
18141814 // Utility functions
18151815 //===----------------------------------------------------------------------===//
18161816
1817 AMDGPUAsmParser::OperandMatchResultTy
1817 OperandMatchResultTy
18181818 AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, int64_t &Int) {
18191819 switch(getLexer().getKind()) {
18201820 default: return MatchOperand_NoMatch;
18401840 return MatchOperand_Success;
18411841 }
18421842
1843 AMDGPUAsmParser::OperandMatchResultTy
1843 OperandMatchResultTy
18441844 AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
18451845 enum AMDGPUOperand::ImmTy ImmTy,
18461846 bool (*ConvertResult)(int64_t&)) {
18481848 SMLoc S = Parser.getTok().getLoc();
18491849 int64_t Value = 0;
18501850
1851 AMDGPUAsmParser::OperandMatchResultTy Res = parseIntWithPrefix(Prefix, Value);
1851 OperandMatchResultTy Res = parseIntWithPrefix(Prefix, Value);
18521852 if (Res != MatchOperand_Success)
18531853 return Res;
18541854
18601860 return MatchOperand_Success;
18611861 }
18621862
1863 AMDGPUAsmParser::OperandMatchResultTy
1863 OperandMatchResultTy
18641864 AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands,
18651865 enum AMDGPUOperand::ImmTy ImmTy) {
18661866 int64_t Bit = 0;
19061906 }
19071907 }
19081908
1909 AMDGPUAsmParser::OperandMatchResultTy
1909 OperandMatchResultTy
19101910 AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix, StringRef &Value) {
19111911 if (getLexer().isNot(AsmToken::Identifier)) {
19121912 return MatchOperand_NoMatch;
20312031 return false;
20322032 }
20332033
2034 AMDGPUAsmParser::OperandMatchResultTy
2034 OperandMatchResultTy
20352035 AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {
20362036 IsaVersion IV = getIsaVersion(getSTI().getFeatureBits());
20372037 int64_t Waitcnt = getWaitcntBitMask(IV);
21172117 return false;
21182118 }
21192119
2120 AMDGPUAsmParser::OperandMatchResultTy
2120 OperandMatchResultTy
21212121 AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {
21222122 using namespace llvm::AMDGPU::Hwreg;
21232123
22652265 return false;
22662266 }
22672267
2268 AMDGPUAsmParser::OperandMatchResultTy
2268 OperandMatchResultTy
22692269 AMDGPUAsmParser::parseSendMsgOp(OperandVector &Operands) {
22702270 using namespace llvm::AMDGPU::SendMsg;
22712271
23522352 // sopp branch targets
23532353 //===----------------------------------------------------------------------===//
23542354
2355 AMDGPUAsmParser::OperandMatchResultTy
2355 OperandMatchResultTy
23562356 AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) {
23572357 SMLoc S = Parser.getTok().getLoc();
23582358
26252625 {"dst_unused", AMDGPUOperand::ImmTySdwaDstUnused, false, nullptr},
26262626 };
26272627
2628 AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) {
2628 OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) {
26292629 OperandMatchResultTy res;
26302630 for (const OptionalOperand &Op : AMDGPUOptionalOperandTable) {
26312631 // try to parse any optional operand here
26492649 return MatchOperand_NoMatch;
26502650 }
26512651
2652 AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands)
2652 OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands)
26532653 {
26542654 StringRef Name = Parser.getTok().getString();
26552655 if (Name == "mul") {
27552755 return isImm() && isUInt<4>(getImm());
27562756 }
27572757
2758 AMDGPUAsmParser::OperandMatchResultTy
2758 OperandMatchResultTy
27592759 AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
27602760 SMLoc S = Parser.getTok().getLoc();
27612761 StringRef Prefix;
29082908 // sdwa
29092909 //===----------------------------------------------------------------------===//
29102910
2911 AMDGPUAsmParser::OperandMatchResultTy
2911 OperandMatchResultTy
29122912 AMDGPUAsmParser::parseSDWASel(OperandVector &Operands, StringRef Prefix,
29132913 AMDGPUOperand::ImmTy Type) {
29142914 using namespace llvm::AMDGPU::SDWA;
29152915
29162916 SMLoc S = Parser.getTok().getLoc();
29172917 StringRef Value;
2918 AMDGPUAsmParser::OperandMatchResultTy res;
2918 OperandMatchResultTy res;
29192919
29202920 res = parseStringWithPrefix(Prefix, Value);
29212921 if (res != MatchOperand_Success) {
29422942 return MatchOperand_Success;
29432943 }
29442944
2945 AMDGPUAsmParser::OperandMatchResultTy
2945 OperandMatchResultTy
29462946 AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {
29472947 using namespace llvm::AMDGPU::SDWA;
29482948
29492949 SMLoc S = Parser.getTok().getLoc();
29502950 StringRef Value;
2951 AMDGPUAsmParser::OperandMatchResultTy res;
2951 OperandMatchResultTy res;
29522952
29532953 res = parseStringWithPrefix("dst_unused", Value);
29542954 if (res != MatchOperand_Success) {
34483448 }
34493449
34503450 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3451 ARMAsmParser::OperandMatchResultTy
3451 OperandMatchResultTy
34523452 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
34533453 MCAsmParser &Parser = getParser();
34543454 SMLoc S = Parser.getTok().getLoc();
34863486 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
34873487 /// token must be an Identifier when called, and if it is a coprocessor
34883488 /// number, the token is eaten and the operand is added to the operand list.
3489 ARMAsmParser::OperandMatchResultTy
3489 OperandMatchResultTy
34903490 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
34913491 MCAsmParser &Parser = getParser();
34923492 SMLoc S = Parser.getTok().getLoc();
35093509 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
35103510 /// token must be an Identifier when called, and if it is a coprocessor
35113511 /// number, the token is eaten and the operand is added to the operand list.
3512 ARMAsmParser::OperandMatchResultTy
3512 OperandMatchResultTy
35133513 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
35143514 MCAsmParser &Parser = getParser();
35153515 SMLoc S = Parser.getTok().getLoc();
35283528
35293529 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
35303530 /// coproc_option : '{' imm0_255 '}'
3531 ARMAsmParser::OperandMatchResultTy
3531 OperandMatchResultTy
35323532 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
35333533 MCAsmParser &Parser = getParser();
35343534 SMLoc S = Parser.getTok().getLoc();
37383738 }
37393739
37403740 // Helper function to parse the lane index for vector lists.
3741 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3741 OperandMatchResultTy ARMAsmParser::
37423742 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
37433743 MCAsmParser &Parser = getParser();
37443744 Index = 0; // Always return a defined index value.
37903790 }
37913791
37923792 // parse a vector register list
3793 ARMAsmParser::OperandMatchResultTy
3793 OperandMatchResultTy
37943794 ARMAsmParser::parseVectorList(OperandVector &Operands) {
37953795 MCAsmParser &Parser = getParser();
37963796 VectorLaneTy LaneKind;
40424042 }
40434043
40444044 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
4045 ARMAsmParser::OperandMatchResultTy
4045 OperandMatchResultTy
40464046 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
40474047 MCAsmParser &Parser = getParser();
40484048 SMLoc S = Parser.getTok().getLoc();
41144114 }
41154115
41164116 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
4117 ARMAsmParser::OperandMatchResultTy
4117 OperandMatchResultTy
41184118 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
41194119 MCAsmParser &Parser = getParser();
41204120 SMLoc S = Parser.getTok().getLoc();
41664166
41674167
41684168 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
4169 ARMAsmParser::OperandMatchResultTy
4169 OperandMatchResultTy
41704170 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
41714171 MCAsmParser &Parser = getParser();
41724172 SMLoc S = Parser.getTok().getLoc();
42014201 }
42024202
42034203 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
4204 ARMAsmParser::OperandMatchResultTy
4204 OperandMatchResultTy
42054205 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
42064206 MCAsmParser &Parser = getParser();
42074207 SMLoc S = Parser.getTok().getLoc();
43544354
43554355 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
43564356 /// use in the MRS/MSR instructions added to support virtualization.
4357 ARMAsmParser::OperandMatchResultTy
4357 OperandMatchResultTy
43584358 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
43594359 MCAsmParser &Parser = getParser();
43604360 SMLoc S = Parser.getTok().getLoc();
44094409 return MatchOperand_Success;
44104410 }
44114411
4412 ARMAsmParser::OperandMatchResultTy
4412 OperandMatchResultTy
44134413 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
44144414 int High) {
44154415 MCAsmParser &Parser = getParser();
44584458 return MatchOperand_Success;
44594459 }
44604460
4461 ARMAsmParser::OperandMatchResultTy
4461 OperandMatchResultTy
44624462 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
44634463 MCAsmParser &Parser = getParser();
44644464 const AsmToken &Tok = Parser.getTok();
44884488 /// lsl #n 'n' in [0,31]
44894489 /// asr #n 'n' in [1,32]
44904490 /// n == 32 encoded as n == 0.
4491 ARMAsmParser::OperandMatchResultTy
4491 OperandMatchResultTy
44924492 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
44934493 MCAsmParser &Parser = getParser();
44944494 const AsmToken &Tok = Parser.getTok();
45594559 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
45604560 /// of instructions. Legal values are:
45614561 /// ror #n 'n' in {0, 8, 16, 24}
4562 ARMAsmParser::OperandMatchResultTy
4562 OperandMatchResultTy
45634563 ARMAsmParser::parseRotImm(OperandVector &Operands) {
45644564 MCAsmParser &Parser = getParser();
45654565 const AsmToken &Tok = Parser.getTok();
46064606 return MatchOperand_Success;
46074607 }
46084608
4609 ARMAsmParser::OperandMatchResultTy
4609 OperandMatchResultTy
46104610 ARMAsmParser::parseModImm(OperandVector &Operands) {
46114611 MCAsmParser &Parser = getParser();
46124612 MCAsmLexer &Lexer = getLexer();
47234723 }
47244724 }
47254725
4726 ARMAsmParser::OperandMatchResultTy
4726 OperandMatchResultTy
47274727 ARMAsmParser::parseBitfield(OperandVector &Operands) {
47284728 MCAsmParser &Parser = getParser();
47294729 SMLoc S = Parser.getTok().getLoc();
47924792 return MatchOperand_Success;
47934793 }
47944794
4795 ARMAsmParser::OperandMatchResultTy
4795 OperandMatchResultTy
47964796 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
47974797 // Check for a post-index addressing register operand. Specifically:
47984798 // postidx_reg := '+' register {, shift}
48424842 return MatchOperand_Success;
48434843 }
48444844
4845 ARMAsmParser::OperandMatchResultTy
4845 OperandMatchResultTy
48464846 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
48474847 // Check for a post-index addressing register operand. Specifically:
48484848 // am3offset := '+' register
52445244 }
52455245
52465246 /// parseFPImm - A floating point immediate expression operand.
5247 ARMAsmParser::OperandMatchResultTy
5247 OperandMatchResultTy
52485248 ARMAsmParser::parseFPImm(OperandVector &Operands) {
52495249 MCAsmParser &Parser = getParser();
52505250 // Anything that can accept a floating point constant as an operand
495495 return true;
496496 }
497497
498 AVRAsmParser::OperandMatchResultTy
498 OperandMatchResultTy
499499 AVRAsmParser::parseMemriOperand(OperandVector &Operands) {
500500 DEBUG(dbgs() << "parseMemriOperand()\n");
501501
843843 }
844844
845845 // Matches memory operand. Returns true if error encountered.
846 LanaiAsmParser::OperandMatchResultTy
846 OperandMatchResultTy
847847 LanaiAsmParser::parseMemoryOperand(OperandVector &Operands) {
848848 // Try to match a memory operand.
849849 // The memory operands are of the form:
977977 // Looks at a token type and creates the relevant operand from this
978978 // information, adding to operands.
979979 // If operand was parsed, returns false, else true.
980 LanaiAsmParser::OperandMatchResultTy
980 OperandMatchResultTy
981981 LanaiAsmParser::parseOperand(OperandVector *Operands, StringRef Mnemonic) {
982982 // Check if the current operand has a custom associated parser, if so, try to
983983 // custom parse the operand, or fallback to the general approach.
45114511 return getParser().parseExpression(Res);
45124512 }
45134513
4514 MipsAsmParser::OperandMatchResultTy
4514 OperandMatchResultTy
45154515 MipsAsmParser::parseMemOperand(OperandVector &Operands) {
45164516 MCAsmParser &Parser = getParser();
45174517 DEBUG(dbgs() << "parseMemOperand\n");
45184518 const MCExpr *IdVal = nullptr;
45194519 SMLoc S;
45204520 bool isParenExpr = false;
4521 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
4521 OperandMatchResultTy Res = MatchOperand_NoMatch;
45224522 // First operand is the offset.
45234523 S = Parser.getTok().getLoc();
45244524
46754675 return false;
46764676 }
46774677
4678 MipsAsmParser::OperandMatchResultTy
4678 OperandMatchResultTy
46794679 MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
46804680 StringRef Identifier,
46814681 SMLoc S) {
47384738 return MatchOperand_NoMatch;
47394739 }
47404740
4741 MipsAsmParser::OperandMatchResultTy
4741 OperandMatchResultTy
47424742 MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) {
47434743 MCAsmParser &Parser = getParser();
47444744 auto Token = Parser.getLexer().peekTok(false);
47624762 return MatchOperand_NoMatch;
47634763 }
47644764
4765 MipsAsmParser::OperandMatchResultTy
4765 OperandMatchResultTy
47664766 MipsAsmParser::parseAnyRegister(OperandVector &Operands) {
47674767 MCAsmParser &Parser = getParser();
47684768 DEBUG(dbgs() << "parseAnyRegister\n");
47904790 return ResTy;
47914791 }
47924792
4793 MipsAsmParser::OperandMatchResultTy
4793 OperandMatchResultTy
47944794 MipsAsmParser::parseJumpTarget(OperandVector &Operands) {
47954795 MCAsmParser &Parser = getParser();
47964796 DEBUG(dbgs() << "parseJumpTarget\n");
48134813 return MatchOperand_Success;
48144814 }
48154815
4816 MipsAsmParser::OperandMatchResultTy
4816 OperandMatchResultTy
48174817 MipsAsmParser::parseInvNum(OperandVector &Operands) {
48184818 MCAsmParser &Parser = getParser();
48194819 const MCExpr *IdVal;
48324832 return MatchOperand_Success;
48334833 }
48344834
4835 MipsAsmParser::OperandMatchResultTy
4835 OperandMatchResultTy
48364836 MipsAsmParser::parseRegisterList(OperandVector &Operands) {
48374837 MCAsmParser &Parser = getParser();
48384838 SmallVector Regs;
49184918 return MatchOperand_Success;
49194919 }
49204920
4921 MipsAsmParser::OperandMatchResultTy
4921 OperandMatchResultTy
49224922 MipsAsmParser::parseRegisterPair(OperandVector &Operands) {
49234923 MCAsmParser &Parser = getParser();
49244924
49344934 return MatchOperand_Success;
49354935 }
49364936
4937 MipsAsmParser::OperandMatchResultTy
4937 OperandMatchResultTy
49384938 MipsAsmParser::parseMovePRegPair(OperandVector &Operands) {
49394939 MCAsmParser &Parser = getParser();
49404940 SmallVector, 8> TmpOperands;
714714 return false;
715715 }
716716
717 SparcAsmParser::OperandMatchResultTy
717 OperandMatchResultTy
718718 SparcAsmParser::parseMEMOperand(OperandVector &Operands) {
719719
720720 SMLoc S, E;
752752 return MatchOperand_Success;
753753 }
754754
755 SparcAsmParser::OperandMatchResultTy
755 OperandMatchResultTy
756756 SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
757757
758758 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
820820 return MatchOperand_Success;
821821 }
822822
823 SparcAsmParser::OperandMatchResultTy
823 OperandMatchResultTy
824824 SparcAsmParser::parseSparcAsmOperand(std::unique_ptr &Op,
825825 bool isCall) {
826826
907907 return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
908908 }
909909
910 SparcAsmParser::OperandMatchResultTy
910 OperandMatchResultTy
911911 SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {
912912
913913 // parse (,a|,pn|,pt)+
661661 }
662662
663663 // Parse a register and add it to Operands. The other arguments are as above.
664 SystemZAsmParser::OperandMatchResultTy
664 OperandMatchResultTy
665665 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
666666 const unsigned *Regs, RegisterKind Kind) {
667667 if (Parser.getTok().isNot(AsmToken::Percent))
678678 }
679679
680680 // Parse any type of register (including integers) and add it to Operands.
681 SystemZAsmParser::OperandMatchResultTy
681 OperandMatchResultTy
682682 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
683683 // Handle integer values.
684684 if (Parser.getTok().is(AsmToken::Integer)) {
791791
792792 // Parse a memory operand and add it to Operands. The other arguments
793793 // are as above.
794 SystemZAsmParser::OperandMatchResultTy
794 OperandMatchResultTy
795795 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
796796 const unsigned *Regs, RegisterKind RegKind) {
797797 SMLoc StartLoc = Parser.getTok().getLoc();
11821182 llvm_unreachable("Unexpected match type");
11831183 }
11841184
1185 SystemZAsmParser::OperandMatchResultTy
1185 OperandMatchResultTy
11861186 SystemZAsmParser::parseAccessReg(OperandVector &Operands) {
11871187 if (Parser.getTok().isNot(AsmToken::Percent))
11881188 return MatchOperand_NoMatch;
11971197 return MatchOperand_Success;
11981198 }
11991199
1200 SystemZAsmParser::OperandMatchResultTy
1200 OperandMatchResultTy
12011201 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
12021202 int64_t MaxVal, bool AllowTLS) {
12031203 MCContext &Ctx = getContext();
27272727
27282728 // Emit the operand class switch to call the correct custom parser for
27292729 // the found operand class.
2730 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2731 << Target.getName() << ClassName << "::\n"
2730 OS << "OperandMatchResultTy " << Target.getName() << ClassName << "::\n"
27322731 << "tryCustomParseOperand(OperandVector"
27332732 << " &Operands,\n unsigned MCK) {\n\n"
27342733 << " switch(MCK) {\n";
27492748 // Emit the static custom operand parser. This code is very similar with
27502749 // the other matcher. Also use MatchResultTy here just in case we go for
27512750 // a better error handling.
2752 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2753 << Target.getName() << ClassName << "::\n"
2751 OS << "OperandMatchResultTy " << Target.getName() << ClassName << "::\n"
27542752 << "MatchOperandParserImpl(OperandVector"
27552753 << " &Operands,\n StringRef Mnemonic) {\n";
27562754
29042902 << " unsigned VariantID = 0);\n";
29052903
29062904 if (!Info.OperandMatchInfo.empty()) {
2907 OS << "\n enum OperandMatchResultTy {\n";
2908 OS << " MatchOperand_Success, // operand matched successfully\n";
2909 OS << " MatchOperand_NoMatch, // operand did not match\n";
2910 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2911 OS << " };\n";
29122905 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
29132906 OS << " OperandVector &Operands,\n";
29142907 OS << " StringRef Mnemonic);\n";