llvm.org GIT mirror llvm / 5a3c6a8
Exit with nice warnings when register allocator run out of registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63267 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 11 years ago
5 changed file(s) with 124 addition(s) and 41 deletion(s). Raw diff Collapse all Expand all
376376 const int *RHSValNoAssignments,
377377 SmallVector &NewVNInfo);
378378
379 /// isInOneLiveRange - Return true if the range specified is entirely in the
380 /// a single LiveRange of the live interval.
381 bool isInOneLiveRange(unsigned Start, unsigned End);
382
379383 /// removeRange - Remove the specified range from this interval. Note that
380384 /// the range must be a single LiveRange in its entirety.
381385 void removeRange(unsigned Start, unsigned End, bool RemoveDeadValNo = false);
241241 // Otherwise, this is just a new range that doesn't interact with anything.
242242 // Insert it.
243243 return ranges.insert(it, LR);
244 }
245
246 /// isInOneLiveRange - Return true if the range specified is entirely in the
247 /// a single LiveRange of the live interval.
248 bool LiveInterval::isInOneLiveRange(unsigned Start, unsigned End) {
249 Ranges::iterator I = std::upper_bound(ranges.begin(), ranges.end(), Start);
250 if (I == ranges.begin())
251 return false;
252 --I;
253 return I->contains(Start) && I->contains(End-1);
244254 }
245255
246256
22272227 unsigned Index = getInstructionIndex(MI);
22282228 if (pli.liveAt(Index)) {
22292229 vrm.addEmergencySpill(SpillReg, MI);
2230 pli.removeRange(getLoadIndex(Index), getStoreIndex(Index)+1);
2230 unsigned StartIdx = getLoadIndex(Index);
2231 unsigned EndIdx = getStoreIndex(Index)+1;
2232 if (pli.isInOneLiveRange(StartIdx, EndIdx))
2233 pli.removeRange(StartIdx, EndIdx);
2234 else {
2235 cerr << "Ran out of registers during register allocation!\n";
2236 if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
2237 cerr << "Please check your inline asm statement for invalid "
2238 << "constraints:\n";
2239 MI->print(cerr.stream(), tm_);
2240 }
2241 exit(1);
2242 }
22312243 for (const unsigned* AS = tri_->getSubRegisters(SpillReg); *AS; ++AS) {
22322244 if (!hasInterval(*AS))
22332245 continue;
2626 #include "llvm/Support/Compiler.h"
2727 #include "llvm/ADT/DenseMap.h"
2828 #include "llvm/ADT/IndexedMap.h"
29 #include "llvm/ADT/SmallSet.h"
2930 #include "llvm/ADT/SmallVector.h"
3031 #include "llvm/ADT/Statistic.h"
3132 #include "llvm/ADT/STLExtras.h"
236237 /// value. This method returns the modified instruction.
237238 ///
238239 MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
239 unsigned OpNum);
240 unsigned OpNum, SmallSet &RRegs);
240241
241242 /// ComputeLocalLiveness - Computes liveness of registers within a basic
242243 /// block, setting the killed/dead flags as appropriate.
474475 /// modified instruction.
475476 ///
476477 MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
477 unsigned OpNum) {
478 unsigned OpNum,
479 SmallSet &ReloadedRegs) {
478480 unsigned VirtReg = MI->getOperand(OpNum).getReg();
479481
480482 // If the virtual register is already available, just update the instruction
512514 MF->getRegInfo().setPhysRegUsed(PhysReg);
513515 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
514516 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
517
518 if (!ReloadedRegs.insert(PhysReg)) {
519 cerr << "Ran out of registers during register allocation!\n";
520 if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
521 cerr << "Please check your inline asm statement for invalid "
522 << "constraints:\n";
523 MI->print(cerr.stream(), TM);
524 }
525 exit(1);
526 }
527 for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
528 *SubRegs; ++SubRegs) {
529 if (!ReloadedRegs.insert(*SubRegs)) {
530 cerr << "Ran out of registers during register allocation!\n";
531 if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
532 cerr << "Please check your inline asm statement for invalid "
533 << "constraints:\n";
534 MI->print(cerr.stream(), TM);
535 }
536 exit(1);
537 }
538 }
539
515540 return MI;
516541 }
517542
580605
581606 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue;
582607
583 const unsigned* subregs = TRI->getAliasSet(MO.getReg());
584 if (subregs) {
585 while (*subregs) {
608 const unsigned* Aliases = TRI->getAliasSet(MO.getReg());
609 if (Aliases) {
610 while (*Aliases) {
586611 DenseMap >::iterator
587 alias = LastUseDef.find(*subregs);
612 alias = LastUseDef.find(*Aliases);
588613
589 if (alias != LastUseDef.end() &&
590 alias->second.first != I)
591 LastUseDef[*subregs] = std::make_pair(I, i);
614 if (alias != LastUseDef.end() && alias->second.first != I)
615 LastUseDef[*Aliases] = std::make_pair(I, i);
592616
593 ++subregs;
617 ++Aliases;
594618 }
595619 }
596620 }
694718 MF->getRegInfo().setPhysRegUsed(Reg);
695719 PhysRegsUsed[Reg] = 0; // It is free and reserved now
696720 AddToPhysRegsUseOrder(Reg);
697 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
698 *AliasSet; ++AliasSet) {
699 if (PhysRegsUsed[*AliasSet] != -2) {
700 AddToPhysRegsUseOrder(*AliasSet);
701 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
702 MF->getRegInfo().setPhysRegUsed(*AliasSet);
721 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
722 *SubRegs; ++SubRegs) {
723 if (PhysRegsUsed[*SubRegs] != -2) {
724 AddToPhysRegsUseOrder(*SubRegs);
725 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
726 MF->getRegInfo().setPhysRegUsed(*SubRegs);
703727 }
704728 }
705729 }
777801 PhysRegsUsed[Reg] = 0; // It is free and reserved now
778802 AddToPhysRegsUseOrder(Reg);
779803
780 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
781 *AliasSet; ++AliasSet) {
782 if (PhysRegsUsed[*AliasSet] != -2) {
783 MF->getRegInfo().setPhysRegUsed(*AliasSet);
784 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
785 AddToPhysRegsUseOrder(*AliasSet);
804 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
805 *SubRegs; ++SubRegs) {
806 if (PhysRegsUsed[*SubRegs] != -2) {
807 MF->getRegInfo().setPhysRegUsed(*SubRegs);
808 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
809 AddToPhysRegsUseOrder(*SubRegs);
786810 }
787811 }
788812 }
796820 // physical register is referenced by the instruction, that it is guaranteed
797821 // to be live-in, or the input is badly hosed.
798822 //
823 SmallSet ReloadedRegs;
799824 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
800825 MachineOperand& MO = MI->getOperand(i);
801826 // here we are looking for only used operands (never def&use)
802827 if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
803828 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
804 MI = reloadVirtReg(MBB, MI, i);
829 MI = reloadVirtReg(MBB, MI, i, ReloadedRegs);
805830 }
806831
807832 // If this instruction is the last user of this register, kill the
829854 DOUT << " Last use of " << TRI->getName(PhysReg)
830855 << "[%reg" << VirtReg <<"], removing it from live set\n";
831856 removePhysReg(PhysReg);
832 for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg);
833 *AliasSet; ++AliasSet) {
834 if (PhysRegsUsed[*AliasSet] != -2) {
857 for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
858 *SubRegs; ++SubRegs) {
859 if (PhysRegsUsed[*SubRegs] != -2) {
835860 DOUT << " Last use of "
836 << TRI->getName(*AliasSet)
861 << TRI->getName(*SubRegs)
837862 << "[%reg" << VirtReg <<"], removing it from live set\n";
838 removePhysReg(*AliasSet);
863 removePhysReg(*SubRegs);
839864 }
840865 }
841866 }
860885 PhysRegsUsed[Reg] = 0; // It is free and reserved now
861886 AddToPhysRegsUseOrder(Reg);
862887
863 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
864 *AliasSet; ++AliasSet) {
865 if (PhysRegsUsed[*AliasSet] != -2) {
866 MF->getRegInfo().setPhysRegUsed(*AliasSet);
867 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
868 AddToPhysRegsUseOrder(*AliasSet);
888 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
889 *SubRegs; ++SubRegs) {
890 if (PhysRegsUsed[*SubRegs] != -2) {
891 MF->getRegInfo().setPhysRegUsed(*SubRegs);
892 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
893 AddToPhysRegsUseOrder(*SubRegs);
869894 }
870895 }
871896 }
882907 PhysRegsUsed[Reg] = 0; // It is free and reserved now
883908 }
884909 MF->getRegInfo().setPhysRegUsed(Reg);
885 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
886 *AliasSet; ++AliasSet) {
887 if (PhysRegsUsed[*AliasSet] != -2) {
888 AddToPhysRegsUseOrder(*AliasSet);
889 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
890 MF->getRegInfo().setPhysRegUsed(*AliasSet);
910 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
911 *SubRegs; ++SubRegs) {
912 if (PhysRegsUsed[*SubRegs] != -2) {
913 AddToPhysRegsUseOrder(*SubRegs);
914 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
915 MF->getRegInfo().setPhysRegUsed(*SubRegs);
891916 }
892917 }
893918 }
0 ; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -disable-fp-elim
1 ; XFAIL: *
2 ; Expected to run out of registers during allocation.
3 ; rdar://6251720
4
5 %struct.CABACContext = type { i32, i32, i8* }
6 %struct.H264Context = type { %struct.CABACContext, [460 x i8] }
7 @coeff_abs_level_m1_offset = common global [6 x i32] zeroinitializer ; <[6 x i32]*> [#uses=1]
8 @coeff_abs_level1_ctx = common global [8 x i8] zeroinitializer ; <[8 x i8]*> [#uses=1]
9
10 define i32 @decode_cabac_residual(%struct.H264Context* %h, i32 %cat) nounwind {
11 entry:
12 %0 = getelementptr [6 x i32]* @coeff_abs_level_m1_offset, i32 0, i32 %cat ; [#uses=1]
13 %1 = load i32* %0, align 4 ; [#uses=1]
14 %2 = load i8* getelementptr ([8 x i8]* @coeff_abs_level1_ctx, i32 0, i32 0), align 1 ; [#uses=1]
15 %3 = zext i8 %2 to i32 ; [#uses=1]
16 %.sum = add i32 %3, %1 ; [#uses=1]
17 %4 = getelementptr %struct.H264Context* %h, i32 0, i32 1, i32 %.sum ; [#uses=2]
18 %5 = getelementptr %struct.H264Context* %h, i32 0, i32 0, i32 0 ; [#uses=2]
19 %6 = getelementptr %struct.H264Context* %h, i32 0, i32 0, i32 1 ; [#uses=2]
20 %7 = getelementptr %struct.H264Context* %h, i32 0, i32 0, i32 2 ; [#uses=2]
21 %8 = load i32* %5, align 4 ; [#uses=1]
22 %9 = load i32* %6, align 4 ; [#uses=1]
23 %10 = load i8* %4, align 4 ; [#uses=1]
24 %asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#$0 $1 $2 $3 $4 $5", "=&{di},=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %7, i8* %4, i32 %8, i32 %9, i8** %7, i8 %10) nounwind ; <{ i32, i32, i32, i32 }> [#uses=3]
25 %asmresult = extractvalue { i32, i32, i32, i32 } %asmtmp, 0 ; [#uses=1]
26 %asmresult1 = extractvalue { i32, i32, i32, i32 } %asmtmp, 1 ; [#uses=1]
27 store i32 %asmresult1, i32* %5
28 %asmresult2 = extractvalue { i32, i32, i32, i32 } %asmtmp, 2 ; [#uses=1]
29 store i32 %asmresult2, i32* %6
30 ret i32 %asmresult
31 }