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Merging r300404: ------------------------------------------------------------------------ r300404 | dim | 2017-04-15 18:15:01 -0400 (Sat, 15 Apr 2017) | 22 lines Use correct registers for "A" inline asm constraint Summary: In PR32594, inline assembly using the 'A' constraint on x86_64 causes llvm to crash with a "Cannot select" stack trace. This is because `X86TargetLowering::getRegForInlineAsmConstraint` hardcodes that 'A' means the EAX and EDX registers. However, on x86_64 it means the RAX and RDX registers, and on 16-bit x86 (ia16?) it means the old AX and DX registers. Add new register classes in `X86RegisterInfo.td` to support these cases, and amend the logic in `getRegForInlineAsmConstraint` to cope with different subtargets. Also add a test case, derived from PR32594. Reviewers: craig.topper, qcolombet, RKSimon, ab Reviewed By: ab Subscribers: ab, emaste, royger, llvm-commits Differential Revision: https://reviews.llvm.org/D31902 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_40@301436 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 years ago
3 changed file(s) with 51 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
3471634716 return Res;
3471734717 }
3471834718
34719 // 'A' means EAX + EDX.
34719 // 'A' means [ER]AX + [ER]DX.
3472034720 if (Constraint == "A") {
34721 Res.first = X86::EAX;
34722 Res.second = &X86::GR32_ADRegClass;
34721 if (Subtarget.is64Bit()) {
34722 Res.first = X86::RAX;
34723 Res.second = &X86::GR64_ADRegClass;
34724 } else if (Subtarget.is32Bit()) {
34725 Res.first = X86::EAX;
34726 Res.second = &X86::GR32_ADRegClass;
34727 } else if (Subtarget.is16Bit()) {
34728 Res.first = X86::AX;
34729 Res.second = &X86::GR16_ADRegClass;
34730 } else {
34731 llvm_unreachable("Expecting 64, 32 or 16 bit subtarget");
34732 }
3472334733 return Res;
3472434734 }
3472534735 return Res;
436436 def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,
437437 (add LOW32_ADDR_ACCESS, RBP)>;
438438
439 // A class to support the 'A' assembler constraint: EAX then EDX.
439 // A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.
440 def GR16_AD : RegisterClass<"X86", [i16], 16, (add AX, DX)>;
440441 def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
442 def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;
441443
442444 // Scalar SSE2 floating point registers.
443445 def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>;
0 ; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
1
2 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
3 target triple = "x86_64--"
4
5 ; Function Attrs: nounwind uwtable
6 define { i64, i64 } @foo(i8* %ptr, i128* nocapture readonly %src, i128* nocapture readonly %dst) local_unnamed_addr #0 {
7 entry:
8 %0 = load i128, i128* %dst, align 16, !tbaa !1
9 %shr = lshr i128 %0, 64
10 %conv = trunc i128 %shr to i64
11 %conv1 = trunc i128 %0 to i64
12 %1 = load i128, i128* %src, align 16, !tbaa !1
13 %2 = tail call i128 asm sideeffect "lock; cmpxchg16b $1", "=A,=*m,{cx},{bx},0,*m,~{dirflag},~{fpsr},~{flags}"(i8* %ptr, i64 %conv, i64 %conv1, i128 %1, i8* %ptr) #1, !srcloc !5
14 %retval.sroa.0.0.extract.trunc = trunc i128 %2 to i64
15 %retval.sroa.2.0.extract.shift = lshr i128 %2, 64
16 %retval.sroa.2.0.extract.trunc = trunc i128 %retval.sroa.2.0.extract.shift to i64
17 %.fca.0.insert = insertvalue { i64, i64 } undef, i64 %retval.sroa.0.0.extract.trunc, 0
18 %.fca.1.insert = insertvalue { i64, i64 } %.fca.0.insert, i64 %retval.sroa.2.0.extract.trunc, 1
19 ret { i64, i64 } %.fca.1.insert
20 }
21 ; CHECK: lock
22 ; CHECK-NEXT: cmpxchg16b
23
24 attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
25 attributes #1 = { nounwind }
26
27 !llvm.ident = !{!0}
28
29 !0 = !{!"clang version 5.0.0 (trunk 300088)"}
30 !1 = !{!2, !2, i64 0}
31 !2 = !{!"__int128", !3, i64 0}
32 !3 = !{!"omnipotent char", !4, i64 0}
33 !4 = !{!"Simple C/C++ TBAA"}
34 !5 = !{i32 269}