llvm.org GIT mirror llvm / 59a0caa
[mips] Split out ASEPredicate from InsnPredicates (NFC) This simplifies tagging instructions with the correct ISA and ASE, albeit making instruction definitions a bit more verbose. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44299 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327265 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Dardis 2 years ago
5 changed file(s) with 46 addition(s) and 46 deletion(s). Raw diff Collapse all Expand all
88
99 class MMDSPInst
1010 : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
11 let InsnPredicates = [HasDSP];
11 let ASEPredicate = [HasDSP];
1212 let AdditionalPredicates = [InMicroMips];
1313 string BaseOpcode = opstr;
1414 string Arch = "mmdsp";
1717
1818 class MMDSPInstAlias
1919 : InstAlias, PredicateControl {
20 let InsnPredicates = [HasDSP];
20 let ASEPredicate = [HasDSP];
2121 let AdditionalPredicates = [InMicroMips];
2222 }
2323
2727 list PTRPredicates = [];
2828 // Predicates for the FGR size and layout such as IsFP64bit
2929 list FGRPredicates = [];
30 // Predicates for the instruction group membership such as ISA's and ASE's
30 // Predicates for the instruction group membership such as ISA's.
3131 list InsnPredicates = [];
32 // Predicate for the ASE that an instruction belongs to.
33 list ASEPredicate = [];
3234 // Predicate for marking the instruction as usable in hard-float mode only.
3335 list HardFloatPredicate = [];
3436 // Predicates for anything else
3941 FGRPredicates,
4042 InsnPredicates,
4143 HardFloatPredicate,
44 ASEPredicate,
4245 AdditionalPredicates);
4346 }
4447
2828 AssemblerPredicate<"FeatureDSPR3">;
2929
3030 class ISA_DSPR2 {
31 list InsnPredicates = [HasDSPR2];
31 list ASEPredicate = [HasDSPR2];
3232 }
3333
3434 class ISA_DSPR3 {
35 list InsnPredicates = [HasDSPR3];
35 list ASEPredicate = [HasDSPR3];
3636 }
3737
3838 // Fields.
4545
4646 class DSPInst
4747 : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
48 let InsnPredicates = [HasDSP];
48 let ASEPredicate = [HasDSP];
4949 string BaseOpcode = opstr;
5050 string Arch = "dsp";
5151 }
5353 class PseudoDSP pattern,
5454 InstrItinClass itin = IIPseudo>
5555 : MipsPseudo {
56 let InsnPredicates = [HasDSP];
56 let ASEPredicate = [HasDSP];
5757 }
5858
5959 class DSPInstAlias
6060 : InstAlias, PredicateControl {
61 let InsnPredicates = [HasDSP];
61 let ASEPredicate = [HasDSP];
6262 }
6363
6464 // ADDU.QB sub-class format.
177177 //===----------------------------------------------------------------------===//
178178
179179 /// Load and Store EVA Instructions
180 def LBE : MMRel, LBE_ENC, LBE_DESC, INSN_EVA;
181 def LBuE : MMRel, LBuE_ENC, LBuE_DESC, INSN_EVA;
182 def LHE : MMRel, LHE_ENC, LHE_DESC, INSN_EVA;
183 def LHuE : MMRel, LHuE_ENC, LHuE_DESC, INSN_EVA;
184 let AdditionalPredicates = [NotInMicroMips] in {
185 def LWE : MMRel, LWE_ENC, LWE_DESC, INSN_EVA;
186 }
187 def SBE : MMRel, SBE_ENC, SBE_DESC, INSN_EVA;
188 def SHE : MMRel, SHE_ENC, SHE_DESC, INSN_EVA;
189 let AdditionalPredicates = [NotInMicroMips] in {
190 def SWE : MMRel, SWE_ENC, SWE_DESC, INSN_EVA;
180 def LBE : MMRel, LBE_ENC, LBE_DESC, ASE_EVA;
181 def LBuE : MMRel, LBuE_ENC, LBuE_DESC, ASE_EVA;
182 def LHE : MMRel, LHE_ENC, LHE_DESC, ASE_EVA;
183 def LHuE : MMRel, LHuE_ENC, LHuE_DESC, ASE_EVA;
184 let AdditionalPredicates = [NotInMicroMips] in {
185 def LWE : MMRel, LWE_ENC, LWE_DESC, ASE_EVA;
186 }
187 def SBE : MMRel, SBE_ENC, SBE_DESC, ASE_EVA;
188 def SHE : MMRel, SHE_ENC, SHE_DESC, ASE_EVA;
189 let AdditionalPredicates = [NotInMicroMips] in {
190 def SWE : MMRel, SWE_ENC, SWE_DESC, ASE_EVA;
191191 }
192192
193193 /// load/store left/right EVA
194194 let AdditionalPredicates = [NotInMicroMips] in {
195 def LWLE : LWLE_ENC, LWLE_DESC, INSN_EVA_NOT_32R6_64R6;
196 def LWRE : LWRE_ENC, LWRE_DESC, INSN_EVA_NOT_32R6_64R6;
197 def SWLE : SWLE_ENC, SWLE_DESC, INSN_EVA_NOT_32R6_64R6;
198 def SWRE : SWRE_ENC, SWRE_DESC, INSN_EVA_NOT_32R6_64R6;
195 def LWLE : LWLE_ENC, LWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
196 def LWRE : LWRE_ENC, LWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
197 def SWLE : SWLE_ENC, SWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
198 def SWRE : SWRE_ENC, SWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
199199 }
200200
201201 /// Load-linked EVA, Store-conditional EVA
202202 let AdditionalPredicates = [NotInMicroMips] in {
203 def LLE : MMRel, LLE_ENC, LLE_DESC, INSN_EVA;
204 def SCE : MMRel, SCE_ENC, SCE_DESC, INSN_EVA;
205 }
206
207 let AdditionalPredicates = [NotInMicroMips] in {
208 def TLBINV : TLBINV_ENC, TLBINV_DESC, INSN_EVA;
209 def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, INSN_EVA;
210 }
211
212 def CACHEE : MMRel, CACHEE_ENC, CACHEE_DESC, INSN_EVA;
213 def PREFE : MMRel, PREFE_ENC, PREFE_DESC, INSN_EVA;
203 def LLE : MMRel, LLE_ENC, LLE_DESC, ASE_EVA;
204 def SCE : MMRel, SCE_ENC, SCE_DESC, ASE_EVA;
205 }
206
207 let AdditionalPredicates = [NotInMicroMips] in {
208 def TLBINV : TLBINV_ENC, TLBINV_DESC, ASE_EVA;
209 def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, ASE_EVA;
210 }
211
212 def CACHEE : MMRel, CACHEE_ENC, CACHEE_DESC, ASE_EVA;
213 def PREFE : MMRel, PREFE_ENC, PREFE_DESC, ASE_EVA;
360360 list InsnPredicates = [NotMips32r6];
361361 list EncodingPredicates = [InMicroMips];
362362 }
363 class INSN_EVA { list InsnPredicates = [HasEVA]; }
364 class INSN_EVA_NOT_32R6_64R6 {
365 list InsnPredicates = [NotMips32r6, NotMips64r6, HasEVA];
366 }
363 class ASE_EVA { list ASEPredicate = [HasEVA]; }
367364
368365 // The portions of MIPS-III that were also added to MIPS32
369366 class INSN_MIPS3_32 {
418415 }
419416
420417 class ASE_CNMIPS {
421 list InsnPredicates = [HasCnMips];
418 list ASEPredicate = [HasCnMips];
422419 }
423420
424421 class NOT_ASE_CNMIPS {
425 list InsnPredicates = [NotCnMips];
422 list ASEPredicate = [NotCnMips];
426423 }
427424
428425 class ASE_MIPS64_CNMIPS {
429 list InsnPredicates = [HasMips64, HasCnMips];
426 list ASEPredicate = [HasMips64, HasCnMips];
430427 }
431428
432429 class ASE_MSA {
433 list InsnPredicates = [HasMSA];
430 list ASEPredicate = [HasMSA];
434431 }
435432
436433 class ASE_MSA_NOT_MSA64 {
437 list InsnPredicates = [HasMSA, NotMips64];
434 list ASEPredicate = [HasMSA, NotMips64];
438435 }
439436
440437 class ASE_MSA64 {
441 list InsnPredicates = [HasMSA, HasMips64];
438 list ASEPredicate = [HasMSA, HasMips64];
442439 }
443440
444441 class ASE_MT {
445 list InsnPredicates = [HasMT];
442 list ASEPredicate = [HasMT];
446443 }
447444
448445 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
453450 }
454451
455452 class ASE_NOT_DSP {
456 list InsnPredicates = [NotDSP];
453 list ASEPredicate = [NotDSP];
457454 }
458455
459456 class MADD4 {