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[AMDGPU] gfx1010 disassembler changes for wave32 Differential Revision: https://reviews.llvm.org/D63506 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363721 91177308-0d34-0410-b5e6-96231b3b80d8 Stanislav Mekhanoshin 4 months ago
2 changed file(s) with 14 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
10381038 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
10391039 "SDWAVopcDst should be present only on GFX9+");
10401040
1041 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
1042
10411043 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
10421044 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
10431045
10451047 if (TTmpIdx >= 0) {
10461048 return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx);
10471049 } else if (Val > SGPR_MAX) {
1048 return decodeSpecialReg64(Val);
1050 return IsWave64 ? decodeSpecialReg64(Val)
1051 : decodeSpecialReg32(Val);
10491052 } else {
1050 return createSRegOperand(getSgprClassId(OPW64), Val);
1053 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
10511054 }
10521055 } else {
1053 return createRegOperand(AMDGPU::VCC);
1054 }
1056 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1057 }
1058 }
1059
1060 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
1061 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
1062 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val);
10551063 }
10561064
10571065 bool AMDGPUDisassembler::isVI() const {
122122 MCOperand decodeSDWASrc32(unsigned Val) const;
123123 MCOperand decodeSDWAVopcDst(unsigned Val) const;
124124
125 MCOperand decodeBoolReg(unsigned Val) const;
126
125127 int getTTmpIdx(unsigned Val) const;
126128
127129 bool isVI() const;