llvm.org GIT mirror llvm / 5907d86
Add an InterferenceCache class for caching per-block interference ranges. When the greedy register allocator is splitting multiple global live ranges, it tends to look at the same interference data many times. The InterferenceCache class caches queries for unaltered LiveIntervalUnions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128764 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 9 years ago
5 changed file(s) with 304 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
13271327 /// const_iterator - Create an iterator that isn't pointing anywhere.
13281328 const_iterator() : map(0) {}
13291329
1330 /// setMap - Change the map iterated over. This call must be followed by a
1331 /// call to goToBegin(), goToEnd(), or find()
1332 void setMap(const IntervalMap &m) { map = const_cast(&m); }
1333
13301334 /// valid - Return true if the current position is valid, false for end().
13311335 bool valid() const { return path.valid(); }
13321336
1818 GCStrategy.cpp
1919 IfConversion.cpp
2020 InlineSpiller.cpp
21 InterferenceCache.cpp
2122 IntrinsicLowering.cpp
2223 LLVMTargetMachine.cpp
2324 LatencyPriorityQueue.cpp
0 //===-- InterferenceCache.h - Caching per-block interference ---*- C++ -*--===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // InterferenceCache remembers per-block interference in LiveIntervalUnions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #define DEBUG_TYPE "regalloc"
14 #include "InterferenceCache.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16
17 using namespace llvm;
18
19 void InterferenceCache::init(MachineFunction *mf,
20 LiveIntervalUnion *liuarray,
21 SlotIndexes *indexes,
22 const TargetRegisterInfo *tri) {
23 MF = mf;
24 LIUArray = liuarray;
25 TRI = tri;
26 PhysRegEntries.assign(TRI->getNumRegs(), 0);
27 for (unsigned i = 0; i != CacheEntries; ++i)
28 Entries[i].clear(indexes);
29 }
30
31 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) {
32 unsigned E = PhysRegEntries[PhysReg];
33 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
34 if (!Entries[E].valid(LIUArray, TRI))
35 Entries[E].revalidate();
36 return &Entries[E];
37 }
38 // No valid entry exists, pick the next round-robin entry.
39 E = RoundRobin;
40 if (++RoundRobin == CacheEntries)
41 RoundRobin = 0;
42 Entries[E].reset(PhysReg, LIUArray, TRI, MF);
43 PhysRegEntries[PhysReg] = E;
44 return &Entries[E];
45 }
46
47 /// revalidate - LIU contents have changed, update tags.
48 void InterferenceCache::Entry::revalidate() {
49 // Invalidate all block entries.
50 ++Tag;
51 // Invalidate all iterators.
52 PrevPos = SlotIndex();
53 for (unsigned i = 0, e = Aliases.size(); i != e; ++i)
54 Aliases[i].second = Aliases[i].first->getTag();
55 }
56
57 void InterferenceCache::Entry::reset(unsigned physReg,
58 LiveIntervalUnion *LIUArray,
59 const TargetRegisterInfo *TRI,
60 const MachineFunction *MF) {
61 // LIU's changed, invalidate cache.
62 ++Tag;
63 PhysReg = physReg;
64 Blocks.resize(MF->getNumBlockIDs());
65 Aliases.clear();
66 for (const unsigned *AS = TRI->getOverlaps(PhysReg); *AS; ++AS) {
67 LiveIntervalUnion *LIU = LIUArray + *AS;
68 Aliases.push_back(std::make_pair(LIU, LIU->getTag()));
69 }
70
71 // Reset iterators.
72 PrevPos = SlotIndex();
73 unsigned e = Aliases.size();
74 Iters.resize(e);
75 for (unsigned i = 0; i != e; ++i)
76 Iters[i].setMap(Aliases[i].first->getMap());
77 }
78
79 bool InterferenceCache::Entry::valid(LiveIntervalUnion *LIUArray,
80 const TargetRegisterInfo *TRI) {
81 unsigned i = 0, e = Aliases.size();
82 for (const unsigned *AS = TRI->getOverlaps(PhysReg); *AS; ++AS, ++i) {
83 LiveIntervalUnion *LIU = LIUArray + *AS;
84 if (i == e || Aliases[i].first != LIU)
85 return false;
86 if (LIU->changedSince(Aliases[i].second))
87 return false;
88 }
89 return i == e;
90 }
91
92 void InterferenceCache::Entry::update(unsigned MBBNum) {
93 BlockInterference *BI = &Blocks[MBBNum];
94 BI->Tag = Tag;
95 BI->First = BI->Last = SlotIndex();
96
97 SlotIndex Start, Stop;
98 tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
99
100 // Use advanceTo only when possible.
101 if (!PrevPos.isValid() || Start < PrevPos)
102 for (unsigned i = 0, e = Iters.size(); i != e; ++i)
103 Iters[i].find(Start);
104 else
105 for (unsigned i = 0, e = Iters.size(); i != e; ++i)
106 Iters[i].advanceTo(Start);
107 PrevPos = Start;
108
109 // Check for first interference.
110 for (unsigned i = 0, e = Iters.size(); i != e; ++i) {
111 Iter &I = Iters[i];
112 if (!I.valid())
113 continue;
114 SlotIndex StartI = I.start();
115 if (StartI >= Stop)
116 continue;
117 if (!BI->First.isValid() || StartI < BI->First)
118 BI->First = StartI;
119 }
120
121 // No interference in block.
122 if (!BI->First.isValid())
123 return;
124
125 // Check for last interference.
126 for (unsigned i = 0, e = Iters.size(); i != e; ++i) {
127 Iter &I = Iters[i];
128 if (!I.valid() || I.start() >= Stop)
129 continue;
130 I.advanceTo(Stop);
131 if (!I.valid() || I.start() >= Stop)
132 --I;
133 SlotIndex StopI = I.stop();
134 if (!BI->Last.isValid() || StopI > BI->Last)
135 BI->Last = StopI;
136 }
137 PrevPos = Stop;
138 }
0 //===-- InterferenceCache.h - Caching per-block interference ---*- C++ -*--===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // InterferenceCache remembers per-block interference in LiveIntervalUnions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_CODEGEN_INTERFERENCECACHE
14 #define LLVM_CODEGEN_INTERFERENCECACHE
15
16 #include "LiveIntervalUnion.h"
17
18 namespace llvm {
19
20 class InterferenceCache {
21 const TargetRegisterInfo *TRI;
22 LiveIntervalUnion *LIUArray;
23 SlotIndexes *Indexes;
24 MachineFunction *MF;
25
26 /// BlockInterference - information about the interference in a single basic
27 /// block.
28 struct BlockInterference {
29 BlockInterference() : Tag(0) {}
30 unsigned Tag;
31 SlotIndex First;
32 SlotIndex Last;
33 };
34
35 /// Entry - A cache entry containing interference information for all aliases
36 /// of PhysReg in all basic blocks.
37 class Entry {
38 /// PhysReg - The register currently represented.
39 unsigned PhysReg;
40
41 /// Tag - Cache tag is changed when any of the underlying LiveIntervalUnions
42 /// change.
43 unsigned Tag;
44
45 /// Indexes - Mapping block numbers to SlotIndex ranges.
46 SlotIndexes *Indexes;
47
48 /// PrevPos - The previous position the iterators were moved to.
49 SlotIndex PrevPos;
50
51 /// AliasTags - A LiveIntervalUnion pointer and tag for each alias of
52 /// PhysReg.
53 SmallVector, 8> Aliases;
54
55 typedef LiveIntervalUnion::SegmentIter Iter;
56
57 /// Iters - an iterator for each alias
58 SmallVector Iters;
59
60 /// Blocks - Interference for each block in the function.
61 SmallVector Blocks;
62
63 /// update - Recompute Blocks[MBBNum]
64 void update(unsigned MBBNum);
65
66 public:
67 Entry() : PhysReg(0), Tag(0), Indexes(0) {}
68
69 void clear(SlotIndexes *indexes) {
70 PhysReg = 0;
71 Indexes = indexes;
72 }
73
74 unsigned getPhysReg() const { return PhysReg; }
75
76 void revalidate();
77
78 /// valid - Return true if this is a valid entry for physReg.
79 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
80
81 /// reset - Initialize entry to represent physReg's aliases.
82 void reset(unsigned physReg,
83 LiveIntervalUnion *LIUArray,
84 const TargetRegisterInfo *TRI,
85 const MachineFunction *MF);
86
87 /// get - Return an up to date BlockInterference.
88 BlockInterference *get(unsigned MBBNum) {
89 if (Blocks[MBBNum].Tag != Tag)
90 update(MBBNum);
91 return &Blocks[MBBNum];
92 }
93 };
94
95 // We don't keep a cache entry for every physical register, that would use too
96 // much memory. Instead, a fixed number of cache entries are used in a round-
97 // robin manner.
98 enum { CacheEntries = 32 };
99
100 // Point to an entry for each physreg. The entry pointed to may not be up to
101 // date, and it may have been reused for a different physreg.
102 SmallVector PhysRegEntries;
103
104 // Next round-robin entry to be picked.
105 unsigned RoundRobin;
106
107 // The actual cache entries.
108 Entry Entries[CacheEntries];
109
110 // get - Get a valid entry for PhysReg.
111 Entry *get(unsigned PhysReg);
112
113 public:
114 InterferenceCache() : TRI(0), LIUArray(0), Indexes(0), MF(0), RoundRobin(0) {}
115
116 /// init - Prepare cache for a new function.
117 void init(MachineFunction*, LiveIntervalUnion*, SlotIndexes*,
118 const TargetRegisterInfo *);
119
120 /// Cursor - The primary query interface for the block interference cache.
121 class Cursor {
122 Entry *CacheEntry;
123 BlockInterference *Current;
124 public:
125 /// Cursor - Create a cursor for the interference allocated to PhysReg and
126 /// all its aliases.
127 Cursor(InterferenceCache &Cache, unsigned PhysReg)
128 : CacheEntry(Cache.get(PhysReg)), Current(0) {}
129
130 /// moveTo - Move cursor to basic block MBBNum.
131 void moveToBlock(unsigned MBBNum) {
132 Current = CacheEntry->get(MBBNum);
133 }
134
135 /// hasInterference - Return true if the current block has any interference.
136 bool hasInterference() {
137 return Current->First.isValid();
138 }
139
140 /// first - Return the starting index of the first interfering range in the
141 /// current block.
142 SlotIndex first() {
143 return Current->First;
144 }
145
146 /// last - Return the ending index of the last interfering range in the
147 /// current block.
148 SlotIndex last() {
149 return Current->Last;
150 }
151 };
152
153 friend class Cursor;
154 };
155
156 } // namespace llvm
157
158 #endif
1313
1414 #define DEBUG_TYPE "regalloc"
1515 #include "AllocationOrder.h"
16 #include "LiveIntervalUnion.h"
16 #include "InterferenceCache.h"
1717 #include "LiveRangeEdit.h"
1818 #include "RegAllocBase.h"
1919 #include "Spiller.h"