llvm.org GIT mirror llvm / 58f59fb
[X86] PUSH/POP 'mem-mem' instructions are not RMW - these are 2 different addresses This patch adds a 'WriteCopy' [WriteLoad, WriteStore] schedule sequence instead to better model the behaviour Found by @andreadb during llvm-mca testing on btver2 which was crashing on "zero uop" WriteRMW only instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343708 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 1 year, 9 months ago
4 changed file(s) with 25 addition(s) and 24 deletion(s). Raw diff Collapse all Expand all
12091209 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable;
12101210 } // isCodeGenOnly = 1, ForceDisassemble = 1
12111211 } // mayLoad, SchedRW
1212 let mayStore = 1, mayLoad = 1, SchedRW = [WriteRMW] in {
1212 let mayStore = 1, mayLoad = 1, SchedRW = [WriteCopy] in {
12131213 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", []>,
12141214 OpSize16;
12151215 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", []>,
12161216 OpSize32, Requires<[Not64BitMode]>;
1217 } // mayStore, mayLoad, WriteRMW
1217 } // mayStore, mayLoad, SchedRW
12181218
12191219 let mayStore = 1, SchedRW = [WriteStore] in {
12201220 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
12421242 Requires<[Not64BitMode]>;
12431243 } // mayStore, SchedRW
12441244
1245 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in {
1245 let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in {
12461246 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>,
12471247 OpSize16;
12481248 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>,
13011301 OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable;
13021302 } // isCodeGenOnly = 1, ForceDisassemble = 1
13031303 } // mayLoad, SchedRW
1304 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in
1304 let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in
13051305 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", []>,
13061306 OpSize32, Requires<[In64BitMode]>;
13071307 let mayStore = 1, SchedRW = [WriteStore] in {
13131313 OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable;
13141314 } // isCodeGenOnly = 1, ForceDisassemble = 1
13151315 } // mayStore, SchedRW
1316 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in {
1316 let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in {
13171317 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>,
13181318 OpSize32, Requires<[In64BitMode]>;
13191319 } // mayLoad, mayStore, SchedRW
106106 def WriteStore : SchedWrite;
107107 def WriteStoreNT : SchedWrite;
108108 def WriteMove : SchedWrite;
109 def WriteCopy : WriteSequence<[WriteLoad, WriteStore]>; // mem->mem copy
109110
110111 // Arithmetic.
111112 defm WriteALU : X86SchedWritePair; // Simple integer ALU op.
16751675 ; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
16761676 ; SLM-NEXT: #APP
16771677 ; SLM-NEXT: popw %ax # sched: [3:1.00]
1678 ; SLM-NEXT: popw (%ecx) # sched: [1:1.00]
1678 ; SLM-NEXT: popw (%ecx) # sched: [4:2.00]
16791679 ; SLM-NEXT: pushw %ax # sched: [1:1.00]
1680 ; SLM-NEXT: pushw (%ecx) # sched: [1:1.00]
1680 ; SLM-NEXT: pushw (%ecx) # sched: [4:2.00]
16811681 ; SLM-NEXT: pushw $4095 # imm = 0xFFF
16821682 ; SLM-NEXT: # sched: [1:1.00]
16831683 ; SLM-NEXT: pushw $7 # sched: [1:1.00]
17651765 ; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
17661766 ; BTVER2-NEXT: #APP
17671767 ; BTVER2-NEXT: popw %ax # sched: [5:1.00]
1768 ; BTVER2-NEXT: popw (%ecx) # sched: [1:1.00]
1768 ; BTVER2-NEXT: popw (%ecx) # sched: [6:1.00]
17691769 ; BTVER2-NEXT: pushw %ax # sched: [1:1.00]
1770 ; BTVER2-NEXT: pushw (%ecx) # sched: [1:1.00]
1770 ; BTVER2-NEXT: pushw (%ecx) # sched: [6:1.00]
17711771 ; BTVER2-NEXT: pushw $4095 # imm = 0xFFF
17721772 ; BTVER2-NEXT: # sched: [1:1.00]
17731773 ; BTVER2-NEXT: pushw $7 # sched: [1:1.00]
18271827 ; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
18281828 ; SLM-NEXT: #APP
18291829 ; SLM-NEXT: popl %eax # sched: [3:1.00]
1830 ; SLM-NEXT: popl (%ecx) # sched: [1:1.00]
1830 ; SLM-NEXT: popl (%ecx) # sched: [4:2.00]
18311831 ; SLM-NEXT: pushl %eax # sched: [1:1.00]
1832 ; SLM-NEXT: pushl (%ecx) # sched: [1:1.00]
1832 ; SLM-NEXT: pushl (%ecx) # sched: [4:2.00]
18331833 ; SLM-NEXT: pushl $4095 # imm = 0xFFF
18341834 ; SLM-NEXT: # sched: [1:1.00]
18351835 ; SLM-NEXT: pushl $7 # sched: [1:1.00]
19171917 ; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
19181918 ; BTVER2-NEXT: #APP
19191919 ; BTVER2-NEXT: popl %eax # sched: [5:1.00]
1920 ; BTVER2-NEXT: popl (%ecx) # sched: [1:1.00]
1920 ; BTVER2-NEXT: popl (%ecx) # sched: [6:1.00]
19211921 ; BTVER2-NEXT: pushl %eax # sched: [1:1.00]
1922 ; BTVER2-NEXT: pushl (%ecx) # sched: [1:1.00]
1922 ; BTVER2-NEXT: pushl (%ecx) # sched: [6:1.00]
19231923 ; BTVER2-NEXT: pushl $4095 # imm = 0xFFF
19241924 ; BTVER2-NEXT: # sched: [1:1.00]
19251925 ; BTVER2-NEXT: pushl $7 # sched: [1:1.00]
19321932 ; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
19331933 ; ZNVER1-NEXT: #APP
19341934 ; ZNVER1-NEXT: popl %eax # sched: [8:0.50]
1935 ; ZNVER1-NEXT: popl (%ecx) # sched: [1:0.50]
1935 ; ZNVER1-NEXT: popl (%ecx) # sched: [9:1.00]
19361936 ; ZNVER1-NEXT: pushl %eax # sched: [1:0.50]
19371937 ; ZNVER1-NEXT: pushl (%ecx) # sched: [4:0.50]
19381938 ; ZNVER1-NEXT: pushl $4095 # imm = 0xFFF
96479647 ; SLM: # %bb.0:
96489648 ; SLM-NEXT: #APP
96499649 ; SLM-NEXT: popw %ax # sched: [3:1.00]
9650 ; SLM-NEXT: popw (%rsi) # sched: [1:1.00]
9650 ; SLM-NEXT: popw (%rsi) # sched: [4:2.00]
96519651 ; SLM-NEXT: pushw %di # sched: [1:1.00]
9652 ; SLM-NEXT: pushw (%rsi) # sched: [1:1.00]
9652 ; SLM-NEXT: pushw (%rsi) # sched: [4:2.00]
96539653 ; SLM-NEXT: pushw $4095 # imm = 0xFFF
96549654 ; SLM-NEXT: # sched: [1:1.00]
96559655 ; SLM-NEXT: pushw $7 # sched: [1:1.00]
97259725 ; BTVER2: # %bb.0:
97269726 ; BTVER2-NEXT: #APP
97279727 ; BTVER2-NEXT: popw %ax # sched: [5:1.00]
9728 ; BTVER2-NEXT: popw (%rsi) # sched: [1:1.00]
9728 ; BTVER2-NEXT: popw (%rsi) # sched: [6:1.00]
97299729 ; BTVER2-NEXT: pushw %di # sched: [1:1.00]
9730 ; BTVER2-NEXT: pushw (%rsi) # sched: [1:1.00]
9730 ; BTVER2-NEXT: pushw (%rsi) # sched: [6:1.00]
97319731 ; BTVER2-NEXT: pushw $4095 # imm = 0xFFF
97329732 ; BTVER2-NEXT: # sched: [1:1.00]
97339733 ; BTVER2-NEXT: pushw $7 # sched: [1:1.00]
97809780 ; SLM: # %bb.0:
97819781 ; SLM-NEXT: #APP
97829782 ; SLM-NEXT: popq %rax # sched: [3:1.00]
9783 ; SLM-NEXT: popq (%rsi) # sched: [1:1.00]
9783 ; SLM-NEXT: popq (%rsi) # sched: [4:2.00]
97849784 ; SLM-NEXT: pushq %rdi # sched: [1:1.00]
9785 ; SLM-NEXT: pushq (%rsi) # sched: [1:1.00]
9785 ; SLM-NEXT: pushq (%rsi) # sched: [4:2.00]
97869786 ; SLM-NEXT: pushq $4095 # imm = 0xFFF
97879787 ; SLM-NEXT: # sched: [1:1.00]
97889788 ; SLM-NEXT: pushq $7 # sched: [1:1.00]
98589858 ; BTVER2: # %bb.0:
98599859 ; BTVER2-NEXT: #APP
98609860 ; BTVER2-NEXT: popq %rax # sched: [5:1.00]
9861 ; BTVER2-NEXT: popq (%rsi) # sched: [1:1.00]
9861 ; BTVER2-NEXT: popq (%rsi) # sched: [6:1.00]
98629862 ; BTVER2-NEXT: pushq %rdi # sched: [1:1.00]
9863 ; BTVER2-NEXT: pushq (%rsi) # sched: [1:1.00]
9863 ; BTVER2-NEXT: pushq (%rsi) # sched: [6:1.00]
98649864 ; BTVER2-NEXT: pushq $4095 # imm = 0xFFF
98659865 ; BTVER2-NEXT: # sched: [1:1.00]
98669866 ; BTVER2-NEXT: pushq $7 # sched: [1:1.00]
98719871 ; ZNVER1: # %bb.0:
98729872 ; ZNVER1-NEXT: #APP
98739873 ; ZNVER1-NEXT: popq %rax # sched: [8:0.50]
9874 ; ZNVER1-NEXT: popq (%rsi) # sched: [1:0.50]
9874 ; ZNVER1-NEXT: popq (%rsi) # sched: [9:1.00]
98759875 ; ZNVER1-NEXT: pushq %rdi # sched: [1:0.50]
9876 ; ZNVER1-NEXT: pushq (%rsi) # sched: [1:0.50]
9876 ; ZNVER1-NEXT: pushq (%rsi) # sched: [9:1.00]
98779877 ; ZNVER1-NEXT: pushq $4095 # imm = 0xFFF
98789878 ; ZNVER1-NEXT: # sched: [1:0.50]
98799879 ; ZNVER1-NEXT: pushq $7 # sched: [1:0.50]