llvm.org GIT mirror llvm / 58f58c9
[cleanup] Lift using directives, DEBUG_TYPE definitions, and even some system headers above the includes of generated '.inc' files that actually contain code. In a few targets this was already done pretty consistently, but it wasn't done *really* consistently anywhere. It is strictly cleaner IMO and necessary in a bunch of places where the DEBUG_TYPE is referenced from the generated code. Consistency with the necessary places trumps. Hopefully the build bots are OK with the movement of intrin.h... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206838 91177308-0d34-0410-b5e6-96231b3b80d8 Chandler Carruth 6 years ago
48 changed file(s) with 119 addition(s) and 123 deletion(s). Raw diff Collapse all Expand all
2727 #include "llvm/Support/TargetRegistry.h"
2828 #include
2929
30 using namespace llvm;
31
3032 #define GET_INSTRINFO_CTOR_DTOR
3133 #include "AArch64GenInstrInfo.inc"
32
33 using namespace llvm;
3434
3535 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
3636 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
2323 #include "llvm/CodeGen/MachineRegisterInfo.h"
2424 #include "llvm/CodeGen/RegisterScavenging.h"
2525
26 using namespace llvm;
27
2628 #define GET_REGINFO_TARGET_DESC
2729 #include "AArch64GenRegisterInfo.inc"
28
29 using namespace llvm;
3030
3131 AArch64RegisterInfo::AArch64RegisterInfo()
3232 : AArch64GenRegisterInfo(AArch64::X30) {
1818 #include "llvm/Support/CommandLine.h"
1919 #include "llvm/Target/TargetSubtargetInfo.h"
2020
21 using namespace llvm;
22
2123 #define DEBUG_TYPE "aarch64-subtarget"
2224
2325 #define GET_SUBTARGETINFO_TARGET_DESC
2426 #define GET_SUBTARGETINFO_CTOR
2527 #include "AArch64GenSubtargetInfo.inc"
26
27 using namespace llvm;
2828
2929 enum AlignMode {
3030 DefaultAlign,
2424 #include "llvm/Support/ErrorHandling.h"
2525 #include "llvm/Support/TargetRegistry.h"
2626
27 using namespace llvm;
28
2729 #define GET_REGINFO_MC_DESC
2830 #include "AArch64GenRegisterInfo.inc"
2931
3234
3335 #define GET_SUBTARGETINFO_MC_DESC
3436 #include "AArch64GenSubtargetInfo.inc"
35
36 using namespace llvm;
3737
3838 MCSubtargetInfo *AArch64_MC::createAArch64MCSubtargetInfo(StringRef TT,
3939 StringRef CPU,
3636 #include "llvm/Support/Debug.h"
3737 #include "llvm/Support/ErrorHandling.h"
3838
39 using namespace llvm;
40
41 #define DEBUG_TYPE "arm-instrinfo"
42
3943 #define GET_INSTRINFO_CTOR_DTOR
4044 #include "ARMGenInstrInfo.inc"
41
42 using namespace llvm;
43
44 #define DEBUG_TYPE "arm-instrinfo"
4545
4646 static cl::opt
4747 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
2020 #include "llvm/Target/TargetInstrInfo.h"
2121 #include "llvm/Target/TargetOptions.h"
2222
23 using namespace llvm;
24
2325 #define DEBUG_TYPE "arm-subtarget"
2426
2527 #define GET_SUBTARGETINFO_TARGET_DESC
2628 #define GET_SUBTARGETINFO_CTOR
2729 #include "ARMGenSubtargetInfo.inc"
28
29 using namespace llvm;
3030
3131 static cl::opt
3232 ReserveR9("arm-reserve-r9", cl::Hidden,
2222 #include "llvm/Support/ErrorHandling.h"
2323 #include "llvm/Support/TargetRegistry.h"
2424
25 using namespace llvm;
26
2527 #define GET_INSTRINFO_CTOR_DTOR
2628 #include "ARM64GenInstrInfo.inc"
27
28 using namespace llvm;
2929
3030 ARM64InstrInfo::ARM64InstrInfo(const ARM64Subtarget &STI)
3131 : ARM64GenInstrInfo(ARM64::ADJCALLSTACKDOWN, ARM64::ADJCALLSTACKUP),
2626 #include "llvm/Target/TargetFrameLowering.h"
2727 #include "llvm/Target/TargetOptions.h"
2828
29 using namespace llvm;
30
2931 #define GET_REGINFO_TARGET_DESC
3032 #include "ARM64GenRegisterInfo.inc"
31
32 using namespace llvm;
3333
3434 ARM64RegisterInfo::ARM64RegisterInfo(const ARM64InstrInfo *tii,
3535 const ARM64Subtarget *sti)
1717 #include "llvm/IR/GlobalValue.h"
1818 #include "llvm/Support/TargetRegistry.h"
1919
20 using namespace llvm;
21
2022 #define DEBUG_TYPE "arm64-subtarget"
2123
2224 #define GET_SUBTARGETINFO_CTOR
2325 #define GET_SUBTARGETINFO_TARGET_DESC
2426 #include "ARM64GenSubtargetInfo.inc"
25
26 using namespace llvm;
2727
2828 ARM64Subtarget::ARM64Subtarget(const std::string &TT, const std::string &CPU,
2929 const std::string &FS)
2222 #include "llvm/Support/MemoryObject.h"
2323 #include "llvm/Support/TargetRegistry.h"
2424 #include "llvm/Support/ErrorHandling.h"
25
26 using namespace llvm;
2527
2628 // Pull DecodeStatus and its enum values into the global namespace.
2729 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
177179 #include "ARM64GenDisassemblerTables.inc"
178180 #include "ARM64GenInstrInfo.inc"
179181
180 using namespace llvm;
181
182182 #define Success llvm::MCDisassembler::Success
183183 #define Fail llvm::MCDisassembler::Fail
184184
2222 #include "llvm/Support/ErrorHandling.h"
2323 #include "llvm/Support/TargetRegistry.h"
2424
25 using namespace llvm;
26
2527 #define GET_INSTRINFO_MC_DESC
2628 #include "ARM64GenInstrInfo.inc"
2729
3032
3133 #define GET_REGINFO_MC_DESC
3234 #include "ARM64GenRegisterInfo.inc"
33
34 using namespace llvm;
3535
3636 static MCInstrInfo *createARM64MCInstrInfo() {
3737 MCInstrInfo *X = new MCInstrInfo();
2525 #include "llvm/Support/Debug.h"
2626 #include "llvm/Support/MathExtras.h"
2727 #include "llvm/Support/raw_ostream.h"
28
29 using namespace llvm;
30
31 #define DEBUG_TYPE "hexagon-instrinfo"
32
2833 #define GET_INSTRINFO_CTOR_DTOR
2934 #define GET_INSTRMAP_INFO
3035 #include "HexagonGenInstrInfo.inc"
3136 #include "HexagonGenDFAPacketizer.inc"
32
33 using namespace llvm;
34
35 #define DEBUG_TYPE "hexagon-instrinfo"
3637
3738 ///
3839 /// Constants for Hexagon instructions.
2222 #include "llvm/Support/ErrorHandling.h"
2323 #include "llvm/Support/TargetRegistry.h"
2424
25 using namespace llvm;
26
2527 #define GET_INSTRINFO_MC_DESC
2628 #include "HexagonGenInstrInfo.inc"
2729
3032
3133 #define GET_REGINFO_MC_DESC
3234 #include "HexagonGenRegisterInfo.inc"
33
34 using namespace llvm;
3535
3636 static MCInstrInfo *createHexagonMCInstrInfo() {
3737 MCInstrInfo *X = new MCInstrInfo();
1919 #include "llvm/MC/MCSubtargetInfo.h"
2020 #include "llvm/Support/TargetRegistry.h"
2121
22 using namespace llvm;
23
2224 #define GET_INSTRINFO_MC_DESC
2325 #include "MSP430GenInstrInfo.inc"
2426
2729
2830 #define GET_REGINFO_MC_DESC
2931 #include "MSP430GenRegisterInfo.inc"
30
31 using namespace llvm;
3232
3333 static MCInstrInfo *createMSP430MCInstrInfo() {
3434 MCInstrInfo *X = new MCInstrInfo();
2121 #include "llvm/Support/ErrorHandling.h"
2222 #include "llvm/Support/TargetRegistry.h"
2323
24 using namespace llvm;
25
2426 #define GET_INSTRINFO_CTOR_DTOR
2527 #include "MSP430GenInstrInfo.inc"
26
27 using namespace llvm;
2828
2929 // Pin the vtable to this file.
3030 void MSP430InstrInfo::anchor() {}
2525 #include "llvm/Target/TargetMachine.h"
2626 #include "llvm/Target/TargetOptions.h"
2727
28 using namespace llvm;
29
2830 #define GET_REGINFO_TARGET_DESC
2931 #include "MSP430GenRegisterInfo.inc"
30
31 using namespace llvm;
3232
3333 // FIXME: Provide proper call frame setup / destroy opcodes.
3434 MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm)
1414 #include "MSP430.h"
1515 #include "llvm/Support/TargetRegistry.h"
1616
17 using namespace llvm;
18
1719 #define DEBUG_TYPE "msp430-subtarget"
1820
1921 #define GET_SUBTARGETINFO_TARGET_DESC
2022 #define GET_SUBTARGETINFO_CTOR
2123 #include "MSP430GenSubtargetInfo.inc"
22
23 using namespace llvm;
2424
2525 void MSP430Subtarget::anchor() { }
2626
2929 #include "llvm/Support/FormattedStream.h"
3030 #include "llvm/Support/TargetRegistry.h"
3131
32 using namespace llvm;
33
3234 #define GET_INSTRINFO_MC_DESC
3335 #include "MipsGenInstrInfo.inc"
3436
3739
3840 #define GET_REGINFO_MC_DESC
3941 #include "MipsGenRegisterInfo.inc"
40
41 using namespace llvm;
4242
4343 /// Select the Mips CPU for the given triple and cpu name.
4444 /// FIXME: Merge with the copy in MipsSubtarget.cpp
2121 #include "llvm/Support/ErrorHandling.h"
2222 #include "llvm/Support/TargetRegistry.h"
2323
24 using namespace llvm;
25
2426 #define GET_INSTRINFO_CTOR_DTOR
2527 #include "MipsGenInstrInfo.inc"
26
27 using namespace llvm;
2828
2929 // Pin the vtable to this file.
3030 void MipsInstrInfo::anchor() {}
3636 #include "llvm/Target/TargetMachine.h"
3737 #include "llvm/Target/TargetOptions.h"
3838
39 using namespace llvm;
40
3941 #define GET_REGINFO_TARGET_DESC
4042 #include "MipsGenRegisterInfo.inc"
41
42 using namespace llvm;
4343
4444 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST)
4545 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
2424 #include "llvm/Support/TargetRegistry.h"
2525 #include "llvm/Support/raw_ostream.h"
2626
27 using namespace llvm;
28
2729 #define GET_SUBTARGETINFO_TARGET_DESC
2830 #define GET_SUBTARGETINFO_CTOR
2931 #include "MipsGenSubtargetInfo.inc"
30
31
32 using namespace llvm;
3332
3433 // FIXME: Maybe this should be on by default when Mips16 is specified
3534 //
1919 #include "llvm/MC/MCSubtargetInfo.h"
2020 #include "llvm/Support/TargetRegistry.h"
2121
22 using namespace llvm;
23
2224 #define GET_INSTRINFO_MC_DESC
2325 #include "NVPTXGenInstrInfo.inc"
2426
2729
2830 #define GET_REGINFO_MC_DESC
2931 #include "NVPTXGenRegisterInfo.inc"
30
31 using namespace llvm;
3232
3333 static MCInstrInfo *createNVPTXMCInstrInfo() {
3434 MCInstrInfo *X = new MCInstrInfo();
1313 #include "NVPTX.h"
1414 #include "NVPTXInstrInfo.h"
1515 #include "NVPTXTargetMachine.h"
16 #define GET_INSTRINFO_CTOR_DTOR
17 #include "NVPTXGenInstrInfo.inc"
1816 #include "llvm/IR/Function.h"
1917 #include "llvm/ADT/STLExtras.h"
2018 #include "llvm/CodeGen/MachineFunction.h"
2220 #include "llvm/CodeGen/MachineRegisterInfo.h"
2321
2422 using namespace llvm;
23
24 #define GET_INSTRINFO_CTOR_DTOR
25 #include "NVPTXGenInstrInfo.inc"
2526
2627 // Pin the vtable to this file.
2728 void NVPTXInstrInfo::anchor() {}
1212
1313 #include "NVPTXSubtarget.h"
1414
15 using namespace llvm;
16
1517 #define DEBUG_TYPE "nvptx-subtarget"
1618
1719 #define GET_SUBTARGETINFO_ENUM
1820 #define GET_SUBTARGETINFO_TARGET_DESC
1921 #define GET_SUBTARGETINFO_CTOR
2022 #include "NVPTXGenSubtargetInfo.inc"
21
22 using namespace llvm;
2323
2424 // Pin the vtable to this file.
2525 void NVPTXSubtarget::anchor() {}
2525 #include "llvm/Support/FormattedStream.h"
2626 #include "llvm/Support/TargetRegistry.h"
2727
28 using namespace llvm;
29
2830 #define GET_INSTRINFO_MC_DESC
2931 #include "PPCGenInstrInfo.inc"
3032
3335
3436 #define GET_REGINFO_MC_DESC
3537 #include "PPCGenRegisterInfo.inc"
36
37 using namespace llvm;
3838
3939 // Pin the vtable to this file.
4040 PPCTargetStreamer::~PPCTargetStreamer() {}
3434 #include "llvm/Support/TargetRegistry.h"
3535 #include "llvm/Support/raw_ostream.h"
3636
37 using namespace llvm;
38
39 #define DEBUG_TYPE "ppc-instr-info"
40
3741 #define GET_INSTRMAP_INFO
3842 #define GET_INSTRINFO_CTOR_DTOR
3943 #include "PPCGenInstrInfo.inc"
40
41 using namespace llvm;
42
43 #define DEBUG_TYPE "ppc-instr-info"
4444
4545 static cl::
4646 opt DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
4141 #include "llvm/Target/TargetOptions.h"
4242 #include
4343
44 using namespace llvm;
45
4446 #define GET_REGINFO_TARGET_DESC
4547 #include "PPCGenRegisterInfo.inc"
46
47 using namespace llvm;
4848
4949 static cl::opt
5050 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
2323 #include "llvm/Target/TargetMachine.h"
2424 #include
2525
26 using namespace llvm;
27
2628 #define DEBUG_TYPE "ppc-subtarget"
2729
2830 #define GET_SUBTARGETINFO_TARGET_DESC
2931 #define GET_SUBTARGETINFO_CTOR
3032 #include "PPCGenSubtargetInfo.inc"
31
32 using namespace llvm;
3333
3434 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
3535 const std::string &FS, bool is64Bit,
1919 #include "llvm/CodeGen/MachineInstrBuilder.h"
2020 #include "llvm/CodeGen/MachineRegisterInfo.h"
2121
22 using namespace llvm;
23
2224 #define GET_INSTRINFO_CTOR_DTOR
2325 #define GET_INSTRINFO_NAMED_OPS
2426 #define GET_INSTRMAP_INFO
2527 #include "AMDGPUGenInstrInfo.inc"
26
27 using namespace llvm;
28
2928
3029 // Pin the vtable to this file.
3130 void AMDGPUInstrInfo::anchor() {}
2323 #include "llvm/Support/ErrorHandling.h"
2424 #include "llvm/Support/TargetRegistry.h"
2525
26 using namespace llvm;
27
2628 #define GET_INSTRINFO_MC_DESC
2729 #include "AMDGPUGenInstrInfo.inc"
2830
3133
3234 #define GET_REGINFO_MC_DESC
3335 #include "AMDGPUGenRegisterInfo.inc"
34
35 using namespace llvm;
3636
3737 static MCInstrInfo *createAMDGPUMCInstrInfo() {
3838 MCInstrInfo *X = new MCInstrInfo();
2222 #include "llvm/CodeGen/MachineInstrBuilder.h"
2323 #include "llvm/CodeGen/MachineRegisterInfo.h"
2424
25 using namespace llvm;
26
2527 #define GET_INSTRINFO_CTOR_DTOR
2628 #include "AMDGPUGenDFAPacketizer.inc"
27
28 using namespace llvm;
2929
3030 R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
3131 : AMDGPUInstrInfo(tm),
2121 #include "llvm/Support/ErrorHandling.h"
2222 #include "llvm/Support/TargetRegistry.h"
2323
24 using namespace llvm;
25
2426 #define GET_INSTRINFO_MC_DESC
2527 #include "SparcGenInstrInfo.inc"
2628
2931
3032 #define GET_REGINFO_MC_DESC
3133 #include "SparcGenRegisterInfo.inc"
32
33 using namespace llvm;
34
3534
3635 static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI,
3736 StringRef TT) {
2323 #include "llvm/Support/ErrorHandling.h"
2424 #include "llvm/Support/TargetRegistry.h"
2525
26 using namespace llvm;
27
2628 #define GET_INSTRINFO_CTOR_DTOR
2729 #include "SparcGenInstrInfo.inc"
28
29 using namespace llvm;
30
3130
3231 // Pin the vtable to this file.
3332 void SparcInstrInfo::anchor() {}
2424 #include "llvm/Support/ErrorHandling.h"
2525 #include "llvm/Target/TargetInstrInfo.h"
2626
27 using namespace llvm;
28
2729 #define GET_REGINFO_TARGET_DESC
2830 #include "SparcGenRegisterInfo.inc"
29
30 using namespace llvm;
3131
3232 static cl::opt
3333 ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
1515 #include "llvm/Support/MathExtras.h"
1616 #include "llvm/Support/TargetRegistry.h"
1717
18 using namespace llvm;
19
1820 #define DEBUG_TYPE "sparc-subtarget"
1921
2022 #define GET_SUBTARGETINFO_TARGET_DESC
2123 #define GET_SUBTARGETINFO_CTOR
2224 #include "SparcGenSubtargetInfo.inc"
23
24 using namespace llvm;
2525
2626 void SparcSubtarget::anchor() { }
2727
1515 #include "llvm/MC/MCSubtargetInfo.h"
1616 #include "llvm/Support/TargetRegistry.h"
1717
18 using namespace llvm;
19
1820 #define GET_INSTRINFO_MC_DESC
1921 #include "SystemZGenInstrInfo.inc"
2022
2325
2426 #define GET_REGINFO_MC_DESC
2527 #include "SystemZGenRegisterInfo.inc"
26
27 using namespace llvm;
2828
2929 const unsigned SystemZMC::GR32Regs[16] = {
3030 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
1616 #include "llvm/CodeGen/LiveVariables.h"
1717 #include "llvm/CodeGen/MachineRegisterInfo.h"
1818
19 using namespace llvm;
20
1921 #define GET_INSTRINFO_CTOR_DTOR
2022 #define GET_INSTRMAP_INFO
2123 #include "SystemZGenInstrInfo.inc"
22
23 using namespace llvm;
2424
2525 // Return a mask with Count low bits set.
2626 static uint64_t allOnes(unsigned int Count) {
1111 #include "llvm/CodeGen/MachineInstrBuilder.h"
1212 #include "llvm/CodeGen/MachineRegisterInfo.h"
1313
14 using namespace llvm;
15
1416 #define GET_REGINFO_TARGET_DESC
1517 #include "SystemZGenRegisterInfo.inc"
16
17 using namespace llvm;
1818
1919 SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm)
2020 : SystemZGenRegisterInfo(SystemZ::R14D), TM(tm) {}
1111 #include "llvm/IR/GlobalValue.h"
1212 #include "llvm/Support/Host.h"
1313
14 using namespace llvm;
15
1416 #define DEBUG_TYPE "systemz-subtarget"
1517
1618 #define GET_SUBTARGETINFO_TARGET_DESC
1719 #define GET_SUBTARGETINFO_CTOR
1820 #include "SystemZGenSubtargetInfo.inc"
19
20 using namespace llvm;
2121
2222 // Pin the vtabel to this file.
2323 void SystemZSubtarget::anchor() {}
2626 #include "llvm/Support/TargetRegistry.h"
2727 #include "llvm/Support/raw_ostream.h"
2828
29 using namespace llvm;
30 using namespace llvm::X86Disassembler;
31
32 #define DEBUG_TYPE "x86-disassembler"
33
2934 #define GET_REGINFO_ENUM
3035 #include "X86GenRegisterInfo.inc"
3136 #define GET_INSTRINFO_ENUM
3237 #include "X86GenInstrInfo.inc"
3338 #define GET_SUBTARGETINFO_ENUM
3439 #include "X86GenSubtargetInfo.inc"
35
36 using namespace llvm;
37 using namespace llvm::X86Disassembler;
38
39 #define DEBUG_TYPE "x86-disassembler"
4040
4141 void llvm::X86Disassembler::Debug(const char *file, unsigned line,
4242 const char *s) {
2626 #include "llvm/Support/Host.h"
2727 #include "llvm/Support/TargetRegistry.h"
2828
29 #define GET_REGINFO_MC_DESC
30 #include "X86GenRegisterInfo.inc"
31
32 #define GET_INSTRINFO_MC_DESC
33 #include "X86GenInstrInfo.inc"
34
35 #define GET_SUBTARGETINFO_MC_DESC
36 #include "X86GenSubtargetInfo.inc"
37
3829 #if _MSC_VER
3930 #include
4031 #endif
4132
4233 using namespace llvm;
4334
35 #define GET_REGINFO_MC_DESC
36 #include "X86GenRegisterInfo.inc"
37
38 #define GET_INSTRINFO_MC_DESC
39 #include "X86GenInstrInfo.inc"
40
41 #define GET_SUBTARGETINFO_MC_DESC
42 #include "X86GenSubtargetInfo.inc"
4443
4544 std::string X86_MC::ParseX86Triple(StringRef TT) {
4645 Triple TheTriple(TT);
3535 #include "llvm/Target/TargetOptions.h"
3636 #include
3737
38 using namespace llvm;
39
3840 #define DEBUG_TYPE "x86-instr-info"
3941
4042 #define GET_INSTRINFO_CTOR_DTOR
4143 #include "X86GenInstrInfo.inc"
42
43 using namespace llvm;
4444
4545 static cl::opt
4646 NoFusing("disable-spill-fusing",
3737 #include "llvm/Target/TargetMachine.h"
3838 #include "llvm/Target/TargetOptions.h"
3939
40 using namespace llvm;
41
4042 #define GET_REGINFO_TARGET_DESC
4143 #include "X86GenRegisterInfo.inc"
42
43 using namespace llvm;
4444
4545 cl::opt
4646 ForceStackAlign("force-align-stack",
2323 #include "llvm/Target/TargetMachine.h"
2424 #include "llvm/Target/TargetOptions.h"
2525
26 using namespace llvm;
27
28 #if defined(_MSC_VER)
29 #include
30 #endif
31
2632 #define GET_SUBTARGETINFO_TARGET_DESC
2733 #define GET_SUBTARGETINFO_CTOR
2834 #include "X86GenSubtargetInfo.inc"
29
30 using namespace llvm;
31
32 #if defined(_MSC_VER)
33 #include
34 #endif
3535
3636 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
3737 /// current subtarget according to how we should reference it in a non-pcrel
2222 #include "llvm/Support/FormattedStream.h"
2323 #include "llvm/Support/TargetRegistry.h"
2424
25 using namespace llvm;
26
2527 #define GET_INSTRINFO_MC_DESC
2628 #include "XCoreGenInstrInfo.inc"
2729
3032
3133 #define GET_REGINFO_MC_DESC
3234 #include "XCoreGenRegisterInfo.inc"
33
34 using namespace llvm;
3535
3636 static MCInstrInfo *createXCoreMCInstrInfo() {
3737 MCInstrInfo *X = new MCInstrInfo();
2525 #include "llvm/Support/ErrorHandling.h"
2626 #include "llvm/Support/TargetRegistry.h"
2727
28 using namespace llvm;
29
2830 #define GET_INSTRINFO_CTOR_DTOR
2931 #include "XCoreGenInstrInfo.inc"
3032
3941 };
4042 }
4143 }
42
43 using namespace llvm;
44
4544
4645 // Pin the vtable to this file.
4746 void XCoreInstrInfo::anchor() {}
3232 #include "llvm/Target/TargetMachine.h"
3333 #include "llvm/Target/TargetOptions.h"
3434
35 using namespace llvm;
36
37 #define DEBUG_TYPE "xcore-reg-info"
38
3539 #define GET_REGINFO_TARGET_DESC
3640 #include "XCoreGenRegisterInfo.inc"
37
38 using namespace llvm;
39
40 #define DEBUG_TYPE "xcore-reg-info"
4141
4242 XCoreRegisterInfo::XCoreRegisterInfo()
4343 : XCoreGenRegisterInfo(XCore::LR) {
1414 #include "XCore.h"
1515 #include "llvm/Support/TargetRegistry.h"
1616
17 using namespace llvm;
18
1719 #define DEBUG_TYPE "xcore-subtarget"
1820
1921 #define GET_SUBTARGETINFO_TARGET_DESC
2022 #define GET_SUBTARGETINFO_CTOR
2123 #include "XCoreGenSubtargetInfo.inc"
22
23 using namespace llvm;
2424
2525 void XCoreSubtarget::anchor() { }
2626