llvm.org GIT mirror llvm / 589130f
Simplify printing of ARM shifted immediates. Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 8 years ago
12 changed file(s) with 22 addition(s) and 58 deletion(s). Raw diff Collapse all Expand all
433433 return ARM_AM::getSOImmVal(Imm) != -1;
434434 }]> {
435435 let EncoderMethod = "getSOImmOpValue";
436 let PrintMethod = "printSOImmOperand";
437436 }
438437
439438 // Break so_imm's up into two pieces. This handles immediates with up to 16
123123 assert(Op.isExpr() && "unknown operand kind in printOperand");
124124 O << *Op.getExpr();
125125 }
126 }
127
128 static void printSOImm(raw_ostream &O, int64_t V, raw_ostream *CommentStream,
129 const MCAsmInfo *MAI) {
130 // Break it up into two parts that make up a shifter immediate.
131 V = ARM_AM::getSOImmVal(V);
132 assert(V != -1 && "Not a valid so_imm value!");
133
134 unsigned Imm = ARM_AM::getSOImmValImm(V);
135 unsigned Rot = ARM_AM::getSOImmValRot(V);
136
137 // Print low-level immediate formation info, per
138 // A5.2.3: Data-processing (immediate), and
139 // A5.2.4: Modified immediate constants in ARM instructions
140 if (Rot) {
141 O << "#" << Imm << ", #" << Rot;
142 // Pretty printed version.
143 if (CommentStream)
144 *CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";
145 } else {
146 O << "#" << Imm;
147 }
148 }
149
150
151 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
152 /// immediate in bits 0-7.
153 void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
154 raw_ostream &O) {
155 const MCOperand &MO = MI->getOperand(OpNum);
156 assert(MO.isImm() && "Not a valid so_imm value!");
157 printSOImm(O, MO.getImm(), CommentStream, &MAI);
158126 }
159127
160128 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
3636
3737
3838 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
39
40 void printSOImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
4139
4240 void printSORegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
4341
1313
1414 define i32 @f3() {
1515 ; CHECK: f3
16 ; CHECK: mov r0, #1, #24
16 ; CHECK: mov r0, #256
1717 ret i32 256
1818 }
1919
2020 define i32 @f4() {
2121 ; CHECK: f4
22 ; CHECK: orr{{.*}}#1, #24
22 ; CHECK: orr{{.*}}#256
2323 ret i32 257
2424 }
2525
2626 define i32 @f5() {
2727 ; CHECK: f5
28 ; CHECK: mov r0, #255, #2
28 ; CHECK: mov r0, #-1073741761
2929 ret i32 -1073741761
3030 }
3131
3232 define i32 @f6() {
3333 ; CHECK: f6
34 ; CHECK: mov r0, #63, #28
34 ; CHECK: mov r0, #1008
3535 ret i32 1008
3636 }
3737
3838 define void @f7(i32 %a) {
3939 ; CHECK: f7
40 ; CHECK: cmp r0, #1, #16
40 ; CHECK: cmp r0, #65536
4141 %b = icmp ugt i32 %a, 65536
4242 br i1 %b, label %r, label %r
4343 r:
4242 br label %b2
4343
4444 ; THUMB: add.w {{.*}} #4096
45 ; ARM: add {{.*}} #1, #20
45 ; ARM: add {{.*}} #4096
4646
4747 b2:
4848 %b = add i32 %tmp, 4095
4141
4242 define double @h(double* %v) {
4343 ;CHECK: h:
44 ;CHECK: vldr.64
44 ;CHECK: vldr.64
4545 ;CHECK-NEXT: vmov
4646 entry:
4747 %tmp = load double* %v ; [#uses=1]
5050
5151 define float @h2() {
5252 ;CHECK: h2:
53 ;CHECK: mov r0, #254, #10
53 ;CHECK: mov r0, #1065353216
5454 entry:
5555 ret float 1.000000e+00
5656 }
1313
1414 define i64 @f3() {
1515 ; CHECK: f3:
16 ; CHECK: mvn r0, #2, #2
16 ; CHECK: mvn r0, #-2147483648
1717 entry:
1818 ret i64 2147483647
1919 }
2020
2121 define i64 @f4() {
2222 ; CHECK: f4:
23 ; CHECK: mov r0, #2, #2
23 ; CHECK: mov r0, #-2147483648
2424 entry:
2525 ret i64 2147483648
2626 }
2828 define i64 @f5() {
2929 ; CHECK: f5:
3030 ; CHECK: mvn r0, #0
31 ; CHECK: mvn r1, #2, #2
31 ; CHECK: mvn r1, #-2147483648
3232 entry:
3333 ret i64 9223372036854775807
3434 }
55 entry:
66 ; ARM: t1:
77 ; ARM: mov [[R1:r[0-9]+]], #101
8 ; ARM: orr [[R1b:r[0-9]+]], [[R1]], #1, #24
8 ; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256
99 ; ARM: movgt r0, #123
1010
1111 ; ARMT2: t1:
2626 ; ARM: t2:
2727 ; ARM: mov r0, #123
2828 ; ARM: movgt r0, #101
29 ; ARM: orrgt r0, r0, #1, #24
29 ; ARM: orrgt r0, r0, #256
3030
3131 ; ARMT2: t2:
3232 ; ARMT2: mov r0, #123
33
44 define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
55 ; ARM: t1:
6 ; ARM: sub r0, r1, #6, #2
6 ; ARM: sub r0, r1, #-2147483647
77 ; ARM: movgt r0, r1
88
99 ; T2: t1:
1111 ; 66846720 = 0x03fc0000
1212 define i64 @f2(i64 %a) {
1313 ; CHECK: f2
14 ; CHECK: subs r0, r0, #255, #14
14 ; CHECK: subs r0, r0, #66846720
1515 ; CHECK: sbc r1, r1, #0
1616 %tmp = sub i64 %a, 66846720
1717 ret i64 %tmp
3838
3939 define i32 @f4(i32 %a, i32 %b) {
4040 ; CHECK: f4
41 ; CHECK: add r0, r0, #254, #28 @ encoding: [0xfe,0x0e,0x80,0xe2]
42 ; CHECK: @ 4064
41 ; CHECK: add r0, r0, #4064 @ encoding: [0xfe,0x0e,0x80,0xe2]
4342 ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
4443 %add = add nsw i32 %a, 4064
4544 ret i32 %add
117116 define i64 @f13() {
118117 ; CHECK: f13:
119118 ; CHECK: mvn r0, #0 @ encoding: [0x00,0x00,0xe0,0xe3]
120 ; CHECK: mvn r1, #2, #2 @ encoding: [0x02,0x11,0xe0,0xe3]
119 ; CHECK: mvn r1, #-2147483648 @ encoding: [0x02,0x11,0xe0,0xe3]
121120 ret i64 9223372036854775807
122121 }
123122
228227
229228 define void @f24(i32 %a) {
230229 ; CHECK: f24
231 ; CHECK: cmp r0, #1, #16 @ encoding: [0x01,0x08,0x50,0xe3]
230 ; CHECK: cmp r0, #65536 @ encoding: [0x01,0x08,0x50,0xe3]
232231 %b = icmp ugt i32 %a, 65536
233232 br i1 %b, label %r, label %r
234233 r:
0 # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s
11
2 # CHECK: addpl r4, pc, #19, #8
2 # CHECK: addpl r4, pc, #318767104
33 0x4c 0x45 0x8f 0x52
44
55 # CHECK: b #0
2020 # CHECK: mov pc, lr
2121 0x0e 0xf0 0xa0 0xe1
2222
23 # CHECK: mov pc, #255, #2
23 # CHECK: mov pc, #3221225535
2424 0xff 0xf1 0xa0 0xe3
2525
2626 # CHECK: movw r7, #4096
7171 # CHECK: movt r8, #65535
7272 0xff 0x8f 0x4f 0xe3
7373
74 # CHECK: mvnspl r7, #245, #2
74 # CHECK: mvnspl r7, #1073741885
7575 0xf5 0x71 0xf0 0x53
7676
7777 # CHECK-NOT: orr r7, r8, r7, rrx #0
151151 # CHECK: msr cpsr_fc, r0
152152 0x00 0xf0 0x29 0xe1
153153
154 # CHECK: msrmi cpsr_c, #241, #8
154 # CHECK: msrmi cpsr_c, #4043309056
155155 0xf1 0xf4 0x21 0x43
156156
157157 # CHECK: rsbs r6, r7, r8