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AMDGPU/GlobalISel: Select G_UNMERGE_VALUES git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365483 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 4 months ago
3 changed file(s) with 278 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
357357
358358 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI))
359359 return false;
360
361 MI.eraseFromParent();
362 return true;
363 }
364
365 bool AMDGPUInstructionSelector::selectG_UNMERGE_VALUES(MachineInstr &MI) const {
366 MachineBasicBlock *BB = MI.getParent();
367 MachineFunction *MF = BB->getParent();
368 MachineRegisterInfo &MRI = MF->getRegInfo();
369 const int NumDst = MI.getNumOperands() - 1;
370
371 MachineOperand &Src = MI.getOperand(NumDst);
372
373 Register SrcReg = Src.getReg();
374 Register DstReg0 = MI.getOperand(0).getReg();
375 LLT DstTy = MRI.getType(DstReg0);
376 LLT SrcTy = MRI.getType(SrcReg);
377
378 const unsigned DstSize = DstTy.getSizeInBits();
379 const unsigned SrcSize = SrcTy.getSizeInBits();
380 const DebugLoc &DL = MI.getDebugLoc();
381 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, TRI);
382
383 const TargetRegisterClass *SrcRC =
384 TRI.getRegClassForSizeOnBank(SrcSize, *SrcBank, MRI);
385 if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI))
386 return false;
387
388 const unsigned SrcFlags = getUndefRegState(Src.isUndef());
389
390 // Note we could have mixed SGPR and VGPR destination banks for an SGPR
391 // source, and this relies on the fact that the same subregister indices are
392 // used for both.
393 ArrayRef SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8);
394 for (int I = 0, E = NumDst; I != E; ++I) {
395 MachineOperand &Dst = MI.getOperand(I);
396 BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::COPY), Dst.getReg())
397 .addReg(SrcReg, SrcFlags, SubRegs[I]);
398
399 const TargetRegisterClass *DstRC =
400 TRI.getConstrainedRegClassForOperand(Dst, MRI);
401 if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, MRI))
402 return false;
403 }
360404
361405 MI.eraseFromParent();
362406 return true;
11841228 case TargetOpcode::G_MERGE_VALUES:
11851229 case TargetOpcode::G_CONCAT_VECTORS:
11861230 return selectG_MERGE_VALUES(I);
1231 case TargetOpcode::G_UNMERGE_VALUES:
1232 return selectG_UNMERGE_VALUES(I);
11871233 case TargetOpcode::G_GEP:
11881234 return selectG_GEP(I);
11891235 case TargetOpcode::G_IMPLICIT_DEF:
7575 bool selectG_ADD(MachineInstr &I) const;
7676 bool selectG_EXTRACT(MachineInstr &I) const;
7777 bool selectG_MERGE_VALUES(MachineInstr &I) const;
78 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
7879 bool selectG_GEP(MachineInstr &I) const;
7980 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
8081 bool selectG_INSERT(MachineInstr &I) const;
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -o - %s 2> %t | FileCheck -check-prefix=GCN %s
2 # RUN: FileCheck -check-prefix=ERR %s < %t
3
4 # ERR-NOT: remark:
5 # ERR: remark: :0:0: cannot select: %1:sgpr(s64), %2:sgpr(s64), %3:sgpr(s64) = G_UNMERGE_VALUES %0:sgpr(s192) (in function: test_unmerge_values_s_s64_s_s64_s64_s_s192)
6 # ERR-NOT: remark:
7
8 ---
9 name: test_unmerge_values_v_s32_v_s32_v_s64
10 legalized: true
11 regBankSelected: true
12 tracksRegLiveness: true
13
14 body: |
15 bb.0:
16 liveins: $vgpr0_vgpr1
17
18 ; GCN-LABEL: name: test_unmerge_values_v_s32_v_s32_v_s64
19 ; GCN: liveins: $vgpr0_vgpr1
20 ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
21 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
22 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
23 ; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
24 %0:vgpr(s64) = COPY $vgpr0_vgpr1
25 %1:vgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES %0
26 S_ENDPGM 0, implicit %1, implicit %2
27 ...
28
29 ---
30 name: test_unmerge_values_s_s32_s_s32_s_s64
31 legalized: true
32 regBankSelected: true
33 tracksRegLiveness: true
34
35 body: |
36 bb.0:
37 liveins: $sgpr0_sgpr1
38
39 ; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s_s64
40 ; GCN: liveins: $sgpr0_sgpr1
41 ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
42 ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0
43 ; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
44 ; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
45 %0:sgpr(s64) = COPY $sgpr0_sgpr1
46 %1:sgpr(s32), %2:sgpr(s32) = G_UNMERGE_VALUES %0
47 S_ENDPGM 0, implicit %1, implicit %2
48 ...
49
50 ---
51 name: test_unmerge_values_v_s32_s_s32_s_s64
52 legalized: true
53 regBankSelected: true
54 tracksRegLiveness: true
55
56 body: |
57 bb.0:
58 liveins: $sgpr0_sgpr1
59
60 ; GCN-LABEL: name: test_unmerge_values_v_s32_s_s32_s_s64
61 ; GCN: liveins: $sgpr0_sgpr1
62 ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
63 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
64 ; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
65 ; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
66 %0:sgpr(s64) = COPY $sgpr0_sgpr1
67 %1:vgpr(s32), %2:sgpr(s32) = G_UNMERGE_VALUES %0
68 S_ENDPGM 0, implicit %1, implicit %2
69 ...
70
71 ---
72 name: test_unmerge_values_s_s32_v_s32_s_s64
73 legalized: true
74 regBankSelected: true
75 tracksRegLiveness: true
76
77 body: |
78 bb.0:
79 liveins: $sgpr0_sgpr1
80
81 ; GCN-LABEL: name: test_unmerge_values_s_s32_v_s32_s_s64
82 ; GCN: liveins: $sgpr0_sgpr1
83 ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
84 ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0
85 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
86 ; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
87 %0:sgpr(s64) = COPY $sgpr0_sgpr1
88 %1:sgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES %0
89 S_ENDPGM 0, implicit %1, implicit %2
90 ...
91
92 ---
93 name: test_unmerge_values_s_s32_v_s32_s_s64_undef_src
94 legalized: true
95 regBankSelected: true
96 tracksRegLiveness: true
97
98 body: |
99 bb.0:
100
101 ; GCN-LABEL: name: test_unmerge_values_s_s32_v_s32_s_s64_undef_src
102 ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY undef %2.sub0:sreg_64_xexec
103 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY undef %2.sub1:sreg_64_xexec
104 ; GCN: S_ENDPGM 0, implicit [[COPY]], implicit [[COPY1]]
105 %1:sgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES undef %0:sgpr(s64)
106 S_ENDPGM 0, implicit %1, implicit %2
107 ...
108
109 ---
110 name: test_unmerge_values_s_s32_s_s32_s32_s_s96
111 legalized: true
112 regBankSelected: true
113 tracksRegLiveness: true
114
115 body: |
116 bb.0:
117 liveins: $sgpr0_sgpr1_sgpr2
118
119 ; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s32_s_s96
120 ; GCN: liveins: $sgpr0_sgpr1_sgpr2
121 ; GCN: [[COPY:%[0-9]+]]:sreg_96 = COPY $sgpr0_sgpr1_sgpr2
122 ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0
123 ; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
124 ; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub2
125 ; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]]
126 %0:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2
127 %1:sgpr(s32), %2:sgpr(s32), %3:sgpr(s32) = G_UNMERGE_VALUES %0
128 S_ENDPGM 0, implicit %1, implicit %2, implicit %3
129 ...
130
131 ---
132 name: test_unmerge_values_s_s32_s_s32_s32_s_s32_s_s128
133 legalized: true
134 regBankSelected: true
135 tracksRegLiveness: true
136
137 body: |
138 bb.0:
139 liveins: $sgpr0_sgpr1_sgpr2_sgpr3
140
141 ; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s32_s_s32_s_s128
142 ; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
143 ; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
144 ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0
145 ; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
146 ; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub2
147 ; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub3
148 ; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY4]]
149 %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
150 %1:sgpr(s32), %2:sgpr(s32), %3:sgpr(s32), %4:sgpr(s32) = G_UNMERGE_VALUES %0
151 S_ENDPGM 0, implicit %1, implicit %2, implicit %3, implicit %4
152 ...
153
154 ---
155 name: test_unmerge_values_s_s64_s_s64_s_s128
156 legalized: true
157 regBankSelected: true
158 tracksRegLiveness: true
159
160 body: |
161 bb.0:
162 liveins: $sgpr0_sgpr1_sgpr2_sgpr3
163
164 ; GCN-LABEL: name: test_unmerge_values_s_s64_s_s64_s_s128
165 ; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
166 ; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
167 ; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]].sub0_sub1
168 ; GCN: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]].sub2_sub3
169 ; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
170 %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
171 %1:sgpr(s64), %2:sgpr(s64) = G_UNMERGE_VALUES %0
172 S_ENDPGM 0, implicit %1, implicit %2
173 ...
174
175 ---
176 name: test_unmerge_values_s_s64_s_s64_s64_s_s192
177 legalized: true
178 regBankSelected: true
179 tracksRegLiveness: true
180
181 body: |
182 bb.0:
183 liveins: $sgpr0_sgpr1_sgpr2_sgpr3
184
185 %0:sgpr(s192) = G_IMPLICIT_DEF
186 %1:sgpr(s64), %2:sgpr(s64), %3:sgpr(s64) = G_UNMERGE_VALUES %0
187 S_ENDPGM 0, implicit %1, implicit %2, implicit %3
188 ...
189
190 ---
191 name: test_unmerge_values_rc_set_def_v_s32_v_s32_v_s64
192 legalized: true
193 regBankSelected: true
194 tracksRegLiveness: true
195
196 body: |
197 bb.0:
198 liveins: $vgpr0_vgpr1
199
200 ; GCN-LABEL: name: test_unmerge_values_rc_set_def_v_s32_v_s32_v_s64
201 ; GCN: liveins: $vgpr0_vgpr1
202 ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
203 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
204 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
205 ; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
206 %0:vgpr(s64) = COPY $vgpr0_vgpr1
207 %1:vgpr_32(s32), %2:vgpr_32(s32) = G_UNMERGE_VALUES %0
208 S_ENDPGM 0, implicit %1, implicit %2
209 ...
210
211 ---
212 name: test_unmerge_values_rc_set_use_v_s32_v_s32_v_s64
213 legalized: true
214 regBankSelected: true
215 tracksRegLiveness: true
216
217 body: |
218 bb.0:
219 liveins: $vgpr0_vgpr1
220
221 ; GCN-LABEL: name: test_unmerge_values_rc_set_use_v_s32_v_s32_v_s64
222 ; GCN: liveins: $vgpr0_vgpr1
223 ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
224 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
225 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
226 ; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
227 %0:vreg_64(s64) = COPY $vgpr0_vgpr1
228 %1:vgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES %0
229 S_ENDPGM 0, implicit %1, implicit %2
230 ...