llvm.org GIT mirror llvm / 57e9efe
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233451 91177308-0d34-0410-b5e6-96231b3b80d8 Akira Hatanaka 5 years ago
4 changed file(s) with 292 addition(s) and 145 deletion(s). Raw diff Collapse all Expand all
479479 // Declare the target which we are implementing
480480 //===----------------------------------------------------------------------===//
481481
482 def ARMAsmWriter : AsmWriter {
483 string AsmWriterClassName = "InstPrinter";
484 int PassSubtarget = 1;
485 int Variant = 0;
486 bit isMCAsmWriter = 1;
487 }
488
482489 def ARM : Target {
483490 // Pull in Instruction Info:
484491 let InstructionSet = ARMInstrInfo;
492 let AssemblyWriters = [ARMAsmWriter];
485493 }
6060 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
6161 const MCRegisterInfo &MRI,
6262 const MCSubtargetInfo &STI)
63 : MCInstPrinter(MAI, MII, MRI) {
64 // Initialize the set of available features.
65 setAvailableFeatures(STI.getFeatureBits());
66 }
63 : MCInstPrinter(MAI, MII, MRI) {}
6764
6865 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
6966 OS << markup("");
9693 O << "\tsev";
9794 break;
9895 case 5:
99 if ((getAvailableFeatures() & ARM::HasV8Ops)) {
96 if ((STI.getFeatureBits() & ARM::HasV8Ops)) {
10097 O << "\tsevl";
10198 break;
10299 } // Fallthrough for non-v8
103100 default:
104101 // Anything else should just print normally.
105 printInstruction(MI, O);
102 printInstruction(MI, STI, O);
106103 printAnnotation(O, Annot);
107104 return;
108105 }
109 printPredicateOperand(MI, 1, O);
106 printPredicateOperand(MI, 1, STI, O);
110107 if (Opcode == ARM::t2HINT)
111108 O << ".w";
112109 printAnnotation(O, Annot);
121118 const MCOperand &MO3 = MI->getOperand(3);
122119
123120 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
124 printSBitModifierOperand(MI, 6, O);
125 printPredicateOperand(MI, 4, O);
121 printSBitModifierOperand(MI, 6, STI, O);
122 printPredicateOperand(MI, 4, STI, O);
126123
127124 O << '\t';
128125 printRegName(O, Dst.getReg());
143140 const MCOperand &MO2 = MI->getOperand(2);
144141
145142 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
146 printSBitModifierOperand(MI, 5, O);
147 printPredicateOperand(MI, 3, O);
143 printSBitModifierOperand(MI, 5, STI, O);
144 printPredicateOperand(MI, 3, STI, O);
148145
149146 O << '\t';
150147 printRegName(O, Dst.getReg());
168165 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
169166 // Should only print PUSH if there are at least two registers in the list.
170167 O << '\t' << "push";
171 printPredicateOperand(MI, 2, O);
168 printPredicateOperand(MI, 2, STI, O);
172169 if (Opcode == ARM::t2STMDB_UPD)
173170 O << ".w";
174171 O << '\t';
175 printRegisterList(MI, 4, O);
172 printRegisterList(MI, 4, STI, O);
176173 printAnnotation(O, Annot);
177174 return;
178175 } else
182179 if (MI->getOperand(2).getReg() == ARM::SP &&
183180 MI->getOperand(3).getImm() == -4) {
184181 O << '\t' << "push";
185 printPredicateOperand(MI, 4, O);
182 printPredicateOperand(MI, 4, STI, O);
186183 O << "\t{";
187184 printRegName(O, MI->getOperand(1).getReg());
188185 O << "}";
197194 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
198195 // Should only print POP if there are at least two registers in the list.
199196 O << '\t' << "pop";
200 printPredicateOperand(MI, 2, O);
197 printPredicateOperand(MI, 2, STI, O);
201198 if (Opcode == ARM::t2LDMIA_UPD)
202199 O << ".w";
203200 O << '\t';
204 printRegisterList(MI, 4, O);
201 printRegisterList(MI, 4, STI, O);
205202 printAnnotation(O, Annot);
206203 return;
207204 } else
211208 if (MI->getOperand(2).getReg() == ARM::SP &&
212209 MI->getOperand(4).getImm() == 4) {
213210 O << '\t' << "pop";
214 printPredicateOperand(MI, 5, O);
211 printPredicateOperand(MI, 5, STI, O);
215212 O << "\t{";
216213 printRegName(O, MI->getOperand(0).getReg());
217214 O << "}";
225222 case ARM::VSTMDDB_UPD:
226223 if (MI->getOperand(0).getReg() == ARM::SP) {
227224 O << '\t' << "vpush";
228 printPredicateOperand(MI, 2, O);
225 printPredicateOperand(MI, 2, STI, O);
229226 O << '\t';
230 printRegisterList(MI, 4, O);
227 printRegisterList(MI, 4, STI, O);
231228 printAnnotation(O, Annot);
232229 return;
233230 } else
238235 case ARM::VLDMDIA_UPD:
239236 if (MI->getOperand(0).getReg() == ARM::SP) {
240237 O << '\t' << "vpop";
241 printPredicateOperand(MI, 2, O);
238 printPredicateOperand(MI, 2, STI, O);
242239 O << '\t';
243 printRegisterList(MI, 4, O);
240 printRegisterList(MI, 4, STI, O);
244241 printAnnotation(O, Annot);
245242 return;
246243 } else
256253
257254 O << "\tldm";
258255
259 printPredicateOperand(MI, 1, O);
256 printPredicateOperand(MI, 1, STI, O);
260257 O << '\t';
261258 printRegName(O, BaseReg);
262259 if (Writeback)
263260 O << "!";
264261 O << ", ";
265 printRegisterList(MI, 3, O);
262 printRegisterList(MI, 3, STI, O);
266263 printAnnotation(O, Annot);
267264 return;
268265 }
294291 // Copy the rest operands into NewMI.
295292 for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
296293 NewMI.addOperand(MI->getOperand(i));
297 printInstruction(&NewMI, O);
294 printInstruction(&NewMI, STI, O);
298295 return;
299296 }
300297 break;
305302 case ARM::t2SUBS_PC_LR: {
306303 if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() &&
307304 MI->getOperand(0).getImm() == 0 &&
308 (getAvailableFeatures() & ARM::FeatureVirtualization)) {
305 (STI.getFeatureBits() & ARM::FeatureVirtualization)) {
309306 O << "\teret";
310 printPredicateOperand(MI, 1, O);
307 printPredicateOperand(MI, 1, STI, O);
311308 printAnnotation(O, Annot);
312309 return;
313310 }
315312 }
316313 }
317314
318 printInstruction(MI, O);
315 printInstruction(MI, STI, O);
319316 printAnnotation(O, Annot);
320317 }
321318
322319 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
323 raw_ostream &O) {
320 const MCSubtargetInfo &STI, raw_ostream &O) {
324321 const MCOperand &Op = MI->getOperand(OpNo);
325322 if (Op.isReg()) {
326323 unsigned Reg = Op.getReg();
358355 }
359356
360357 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
358 const MCSubtargetInfo &STI,
361359 raw_ostream &O) {
362360 const MCOperand &MO1 = MI->getOperand(OpNum);
363361 if (MO1.isExpr()) {
387385 // REG REG 0,SH_OPC - e.g. R5, ROR R3
388386 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
389387 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
388 const MCSubtargetInfo &STI,
390389 raw_ostream &O) {
391390 const MCOperand &MO1 = MI->getOperand(OpNum);
392391 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
406405 }
407406
408407 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
408 const MCSubtargetInfo &STI,
409409 raw_ostream &O) {
410410 const MCOperand &MO1 = MI->getOperand(OpNum);
411411 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
422422 //===--------------------------------------------------------------------===//
423423
424424 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
425 const MCSubtargetInfo &STI,
425426 raw_ostream &O) {
426427 const MCOperand &MO1 = MI->getOperand(Op);
427428 const MCOperand &MO2 = MI->getOperand(Op + 1);
450451 }
451452
452453 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
454 const MCSubtargetInfo &STI,
453455 raw_ostream &O) {
454456 const MCOperand &MO1 = MI->getOperand(Op);
455457 const MCOperand &MO2 = MI->getOperand(Op + 1);
461463 }
462464
463465 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
466 const MCSubtargetInfo &STI,
464467 raw_ostream &O) {
465468 const MCOperand &MO1 = MI->getOperand(Op);
466469 const MCOperand &MO2 = MI->getOperand(Op + 1);
472475 }
473476
474477 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
478 const MCSubtargetInfo &STI,
475479 raw_ostream &O) {
476480 const MCOperand &MO1 = MI->getOperand(Op);
477481
478482 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
479 printOperand(MI, Op, O);
483 printOperand(MI, Op, STI, O);
480484 return;
481485 }
482486
486490 assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
487491 #endif
488492
489 printAM2PreOrOffsetIndexOp(MI, Op, O);
493 printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
490494 }
491495
492496 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
493497 unsigned OpNum,
498 const MCSubtargetInfo &STI,
494499 raw_ostream &O) {
495500 const MCOperand &MO1 = MI->getOperand(OpNum);
496501 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
544549
545550 template
546551 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
552 const MCSubtargetInfo &STI,
547553 raw_ostream &O) {
548554 const MCOperand &MO1 = MI->getOperand(Op);
549555 if (!MO1.isReg()) { // For label symbolic references.
550 printOperand(MI, Op, O);
556 printOperand(MI, Op, STI, O);
551557 return;
552558 }
553559
559565
560566 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
561567 unsigned OpNum,
568 const MCSubtargetInfo &STI,
562569 raw_ostream &O) {
563570 const MCOperand &MO1 = MI->getOperand(OpNum);
564571 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
576583 }
577584
578585 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
586 const MCSubtargetInfo &STI,
579587 raw_ostream &O) {
580588 const MCOperand &MO = MI->getOperand(OpNum);
581589 unsigned Imm = MO.getImm();
584592 }
585593
586594 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
595 const MCSubtargetInfo &STI,
587596 raw_ostream &O) {
588597 const MCOperand &MO1 = MI->getOperand(OpNum);
589598 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
593602 }
594603
595604 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
605 const MCSubtargetInfo &STI,
596606 raw_ostream &O) {
597607 const MCOperand &MO = MI->getOperand(OpNum);
598608 unsigned Imm = MO.getImm();
601611 }
602612
603613 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
614 const MCSubtargetInfo &STI,
604615 raw_ostream &O) {
605616 ARM_AM::AMSubMode Mode =
606617 ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm());
609620
610621 template
611622 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
623 const MCSubtargetInfo &STI,
612624 raw_ostream &O) {
613625 const MCOperand &MO1 = MI->getOperand(OpNum);
614626 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
615627
616628 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
617 printOperand(MI, OpNum, O);
629 printOperand(MI, OpNum, STI, O);
618630 return;
619631 }
620632
631643 }
632644
633645 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
646 const MCSubtargetInfo &STI,
634647 raw_ostream &O) {
635648 const MCOperand &MO1 = MI->getOperand(OpNum);
636649 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
644657 }
645658
646659 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
660 const MCSubtargetInfo &STI,
647661 raw_ostream &O) {
648662 const MCOperand &MO1 = MI->getOperand(OpNum);
649663 O << markup("
653667
654668 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
655669 unsigned OpNum,
670 const MCSubtargetInfo &STI,
656671 raw_ostream &O) {
657672 const MCOperand &MO = MI->getOperand(OpNum);
658673 if (MO.getReg() == 0)
665680
666681 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
667682 unsigned OpNum,
683 const MCSubtargetInfo &STI,
668684 raw_ostream &O) {
669685 const MCOperand &MO = MI->getOperand(OpNum);
670686 uint32_t v = ~MO.getImm();
676692 }
677693
678694 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
695 const MCSubtargetInfo &STI,
679696 raw_ostream &O) {
680697 unsigned val = MI->getOperand(OpNum).getImm();
681 O << ARM_MB::MemBOptToString(val, (getAvailableFeatures() & ARM::HasV8Ops));
698 O << ARM_MB::MemBOptToString(val, (STI.getFeatureBits() & ARM::HasV8Ops));
682699 }
683700
684701 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
702 const MCSubtargetInfo &STI,
685703 raw_ostream &O) {
686704 unsigned val = MI->getOperand(OpNum).getImm();
687705 O << ARM_ISB::InstSyncBOptToString(val);
688706 }
689707
690708 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
709 const MCSubtargetInfo &STI,
691710 raw_ostream &O) {
692711 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
693712 bool isASR = (ShiftOp & (1 << 5)) != 0;
701720 }
702721
703722 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
723 const MCSubtargetInfo &STI,
704724 raw_ostream &O) {
705725 unsigned Imm = MI->getOperand(OpNum).getImm();
706726 if (Imm == 0)
710730 }
711731
712732 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
733 const MCSubtargetInfo &STI,
713734 raw_ostream &O) {
714735 unsigned Imm = MI->getOperand(OpNum).getImm();
715736 // A shift amount of 32 is encoded as 0.
720741 }
721742
722743 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
744 const MCSubtargetInfo &STI,
723745 raw_ostream &O) {
724746 O << "{";
725747 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
731753 }
732754
733755 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
756 const MCSubtargetInfo &STI,
734757 raw_ostream &O) {
735758 unsigned Reg = MI->getOperand(OpNum).getReg();
736759 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
739762 }
740763
741764 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
765 const MCSubtargetInfo &STI,
742766 raw_ostream &O) {
743767 const MCOperand &Op = MI->getOperand(OpNum);
744768 if (Op.getImm())
748772 }
749773
750774 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
751 raw_ostream &O) {
775 const MCSubtargetInfo &STI, raw_ostream &O) {
752776 const MCOperand &Op = MI->getOperand(OpNum);
753777 O << ARM_PROC::IModToString(Op.getImm());
754778 }
755779
756780 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
757 raw_ostream &O) {
781 const MCSubtargetInfo &STI, raw_ostream &O) {
758782 const MCOperand &Op = MI->getOperand(OpNum);
759783 unsigned IFlags = Op.getImm();
760784 for (int i = 2; i >= 0; --i)
766790 }
767791
768792 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
793 const MCSubtargetInfo &STI,
769794 raw_ostream &O) {
770795 const MCOperand &Op = MI->getOperand(OpNum);
771796 unsigned SpecRegRBit = Op.getImm() >> 4;
772797 unsigned Mask = Op.getImm() & 0xf;
773 uint64_t FeatureBits = getAvailableFeatures();
798 uint64_t FeatureBits = STI.getFeatureBits();
774799
775800 if (FeatureBits & ARM::FeatureMClass) {
776801 unsigned SYSm = Op.getImm();
914939 }
915940
916941 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
942 const MCSubtargetInfo &STI,
917943 raw_ostream &O) {
918944 uint32_t Banked = MI->getOperand(OpNum).getImm();
919945 uint32_t R = (Banked & 0x20) >> 5;
965991 }
966992
967993 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
994 const MCSubtargetInfo &STI,
968995 raw_ostream &O) {
969996 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
970997 // Handle the undefined 15 CC value here for printing so we don't abort().
9761003
9771004 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
9781005 unsigned OpNum,
1006 const MCSubtargetInfo &STI,
9791007 raw_ostream &O) {
9801008 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
9811009 O << ARMCondCodeToString(CC);
9821010 }
9831011
9841012 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
1013 const MCSubtargetInfo &STI,
9851014 raw_ostream &O) {
9861015 if (MI->getOperand(OpNum).getReg()) {
9871016 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
9911020 }
9921021
9931022 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
1023 const MCSubtargetInfo &STI,
9941024 raw_ostream &O) {
9951025 O << MI->getOperand(OpNum).getImm();
9961026 }
9971027
9981028 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
1029 const MCSubtargetInfo &STI,
9991030 raw_ostream &O) {
10001031 O << "p" << MI->getOperand(OpNum).getImm();
10011032 }
10021033
10031034 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
1035 const MCSubtargetInfo &STI,
10041036 raw_ostream &O) {
10051037 O << "c" << MI->getOperand(OpNum).getImm();
10061038 }
10071039
10081040 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
1041 const MCSubtargetInfo &STI,
10091042 raw_ostream &O) {
10101043 O << "{" << MI->getOperand(OpNum).getImm() << "}";
10111044 }
10121045
10131046 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
1014 raw_ostream &O) {
1047 const MCSubtargetInfo &STI, raw_ostream &O) {
10151048 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
10161049 }
10171050
10181051 template
10191052 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
1053 const MCSubtargetInfo &STI,
10201054 raw_ostream &O) {
10211055 const MCOperand &MO = MI->getOperand(OpNum);
10221056
10381072 }
10391073
10401074 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
1075 const MCSubtargetInfo &STI,
10411076 raw_ostream &O) {
10421077 O << markup("getOperand(OpNum).getImm() * 4)
10431078 << markup(">");
10441079 }
10451080
10461081 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
1082 const MCSubtargetInfo &STI,
10471083 raw_ostream &O) {
10481084 unsigned Imm = MI->getOperand(OpNum).getImm();
10491085 O << markup("
10511087 }
10521088
10531089 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1090 const MCSubtargetInfo &STI,
10541091 raw_ostream &O) {
10551092 // (3 - the number of trailing zeros) is the number of then / else.
10561093 unsigned Mask = MI->getOperand(OpNum).getImm();
10681105 }
10691106
10701107 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
1108 const MCSubtargetInfo &STI,
10711109 raw_ostream &O) {
10721110 const MCOperand &MO1 = MI->getOperand(Op);
10731111 const MCOperand &MO2 = MI->getOperand(Op + 1);
10741112
10751113 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1076 printOperand(MI, Op, O);
1114 printOperand(MI, Op, STI, O);
10771115 return;
10781116 }
10791117
10871125 }
10881126
10891127 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
1090 unsigned Op, raw_ostream &O,
1128 unsigned Op,
1129 const MCSubtargetInfo &STI,
1130 raw_ostream &O,
10911131 unsigned Scale) {
10921132 const MCOperand &MO1 = MI->getOperand(Op);
10931133 const MCOperand &MO2 = MI->getOperand(Op + 1);
10941134
10951135 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1096 printOperand(MI, Op, O);
1136 printOperand(MI, Op, STI, O);
10971137 return;
10981138 }
10991139
11081148
11091149 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
11101150 unsigned Op,
1151 const MCSubtargetInfo &STI,
11111152 raw_ostream &O) {
1112 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
1153 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1);
11131154 }
11141155
11151156 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
11161157 unsigned Op,
1158 const MCSubtargetInfo &STI,
11171159 raw_ostream &O) {
1118 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
1160 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2);
11191161 }
11201162
11211163 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
11221164 unsigned Op,
1165 const MCSubtargetInfo &STI,
11231166 raw_ostream &O) {
1124 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1167 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
11251168 }
11261169
11271170 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1171 const MCSubtargetInfo &STI,
11281172 raw_ostream &O) {
1129 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1173 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
11301174 }
11311175
11321176 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
11341178 // REG 0 0 - e.g. R5
11351179 // REG IMM, SH_OPC - e.g. R5, LSL #3
11361180 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1181 const MCSubtargetInfo &STI,
11371182 raw_ostream &O) {
11381183 const MCOperand &MO1 = MI->getOperand(OpNum);
11391184 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
11491194
11501195 template
11511196 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1197 const MCSubtargetInfo &STI,
11521198 raw_ostream &O) {
11531199 const MCOperand &MO1 = MI->getOperand(OpNum);
11541200 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
11551201
11561202 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1157 printOperand(MI, OpNum, O);
1203 printOperand(MI, OpNum, STI, O);
11581204 return;
11591205 }
11601206
11771223 template
11781224 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
11791225 unsigned OpNum,
1226 const MCSubtargetInfo &STI,
11801227 raw_ostream &O) {
11811228 const MCOperand &MO1 = MI->getOperand(OpNum);
11821229 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
12001247 template
12011248 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
12021249 unsigned OpNum,
1250 const MCSubtargetInfo &STI,
12031251 raw_ostream &O) {
12041252 const MCOperand &MO1 = MI->getOperand(OpNum);
12051253 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
12061254
12071255 if (!MO1.isReg()) { // For label symbolic references.
1208 printOperand(MI, OpNum, O);
1256 printOperand(MI, OpNum, STI, O);
12091257 return;
12101258 }
12111259
12281276 O << "]" << markup(">");
12291277 }
12301278
1231 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
1232 unsigned OpNum,
1233 raw_ostream &O) {
1279 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(
1280 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1281 raw_ostream &O) {
12341282 const MCOperand &MO1 = MI->getOperand(OpNum);
12351283 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
12361284
12431291 O << "]" << markup(">");
12441292 }
12451293
1246 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
1247 unsigned OpNum,
1248 raw_ostream &O) {
1294 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(
1295 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1296 raw_ostream &O) {
12491297 const MCOperand &MO1 = MI->getOperand(OpNum);
12501298 int32_t OffImm = (int32_t)MO1.getImm();
12511299 O << ", " << markup("
12581306 O << markup(">");
12591307 }
12601308
1261 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
1262 unsigned OpNum,
1263 raw_ostream &O) {
1309 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(
1310 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1311 raw_ostream &O) {
12641312 const MCOperand &MO1 = MI->getOperand(OpNum);
12651313 int32_t OffImm = (int32_t)MO1.getImm();
12661314
12781326
12791327 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
12801328 unsigned OpNum,
1329 const MCSubtargetInfo &STI,
12811330 raw_ostream &O) {
12821331 const MCOperand &MO1 = MI->getOperand(OpNum);
12831332 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
12991348 }
13001349
13011350 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1351 const MCSubtargetInfo &STI,
13021352 raw_ostream &O) {
13031353 const MCOperand &MO = MI->getOperand(OpNum);
13041354 O << markup("
13061356 }
13071357
13081358 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1359 const MCSubtargetInfo &STI,
13091360 raw_ostream &O) {
13101361 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
13111362 unsigned EltBits;
13161367 }
13171368
13181369 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1370 const MCSubtargetInfo &STI,
13191371 raw_ostream &O) {
13201372 unsigned Imm = MI->getOperand(OpNum).getImm();
13211373 O << markup("");
13221374 }
13231375
13241376 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1377 const MCSubtargetInfo &STI,
13251378 raw_ostream &O) {
13261379 unsigned Imm = MI->getOperand(OpNum).getImm();
13271380 if (Imm == 0)
13441397 }
13451398
13461399 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1400 const MCSubtargetInfo &STI,
13471401 raw_ostream &O) {
13481402 MCOperand Op = MI->getOperand(OpNum);
13491403
13501404 // Support for fixups (MCFixup)
13511405 if (Op.isExpr())
1352 return printOperand(MI, OpNum, O);
1406 return printOperand(MI, OpNum, STI, O);
13531407
13541408 unsigned Bits = Op.getImm() & 0xFF;
13551409 unsigned Rot = (Op.getImm() & 0xF00) >> 7;
13841438 }
13851439
13861440 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1387 raw_ostream &O) {
1441 const MCSubtargetInfo &STI, raw_ostream &O) {
13881442 O << markup("getOperand(OpNum).getImm()
13891443 << markup(">");
13901444 }
13911445
13921446 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1393 raw_ostream &O) {
1447 const MCSubtargetInfo &STI, raw_ostream &O) {
13941448 O << markup("getOperand(OpNum).getImm()
13951449 << markup(">");
13961450 }
13971451
13981452 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1453 const MCSubtargetInfo &STI,
13991454 raw_ostream &O) {
14001455 O << "[" << MI->getOperand(OpNum).getImm() << "]";
14011456 }
14021457
14031458 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1459 const MCSubtargetInfo &STI,
14041460 raw_ostream &O) {
14051461 O << "{";
14061462 printRegName(O, MI->getOperand(OpNum).getReg());
14081464 }
14091465
14101466 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1467 const MCSubtargetInfo &STI,
14111468 raw_ostream &O) {
14121469 unsigned Reg = MI->getOperand(OpNum).getReg();
14131470 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
14201477 }
14211478
14221479 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1480 const MCSubtargetInfo &STI,
14231481 raw_ostream &O) {
14241482 unsigned Reg = MI->getOperand(OpNum).getReg();
14251483 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
14321490 }
14331491
14341492 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1493 const MCSubtargetInfo &STI,
14351494 raw_ostream &O) {
14361495 // Normally, it's not safe to use register enum values directly with
14371496 // addition to get the next register, but for VFP registers, the
14461505 }
14471506
14481507 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1508 const MCSubtargetInfo &STI,
14491509 raw_ostream &O) {
14501510 // Normally, it's not safe to use register enum values directly with
14511511 // addition to get the next register, but for VFP registers, the
14631523
14641524 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
14651525 unsigned OpNum,
1526 const MCSubtargetInfo &STI,
14661527 raw_ostream &O) {
14671528 O << "{";
14681529 printRegName(O, MI->getOperand(OpNum).getReg());
14711532
14721533 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
14731534 unsigned OpNum,
1535 const MCSubtargetInfo &STI,
14741536 raw_ostream &O) {
14751537 unsigned Reg = MI->getOperand(OpNum).getReg();
14761538 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
14841546
14851547 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
14861548 unsigned OpNum,
1549 const MCSubtargetInfo &STI,
14871550 raw_ostream &O) {
14881551 // Normally, it's not safe to use register enum values directly with
14891552 // addition to get the next register, but for VFP registers, the
14991562
15001563 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
15011564 unsigned OpNum,
1565 const MCSubtargetInfo &STI,
15021566 raw_ostream &O) {
15031567 // Normally, it's not safe to use register enum values directly with
15041568 // addition to get the next register, but for VFP registers, the
15141578 O << "[]}";
15151579 }
15161580
1517 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1518 unsigned OpNum,
1519 raw_ostream &O) {
1581 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(
1582 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1583 raw_ostream &O) {
15201584 unsigned Reg = MI->getOperand(OpNum).getReg();
15211585 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
15221586 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
15271591 O << "[]}";
15281592 }
15291593
1530 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
1531 unsigned OpNum,
1532 raw_ostream &O) {
1594 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(
1595 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1596 raw_ostream &O) {
15331597 // Normally, it's not safe to use register enum values directly with
15341598 // addition to get the next register, but for VFP registers, the
15351599 // sort order is guaranteed because they're all of the form D.
15421606 O << "[]}";
15431607 }
15441608
1545 void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
1546 unsigned OpNum,
1547 raw_ostream &O) {
1609 void ARMInstPrinter::printVectorListFourSpacedAllLanes(
1610 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1611 raw_ostream &O) {
15481612 // Normally, it's not safe to use register enum values directly with
15491613 // addition to get the next register, but for VFP registers, the
15501614 // sort order is guaranteed because they're all of the form D.
15611625
15621626 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
15631627 unsigned OpNum,
1628 const MCSubtargetInfo &STI,
15641629 raw_ostream &O) {
15651630 // Normally, it's not safe to use register enum values directly with
15661631 // addition to get the next register, but for VFP registers, the
15751640 }
15761641
15771642 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
1643 const MCSubtargetInfo &STI,
15781644 raw_ostream &O) {
15791645 // Normally, it's not safe to use register enum values directly with
15801646 // addition to get the next register, but for VFP registers, the
3030 void printRegName(raw_ostream &OS, unsigned RegNo) const override;
3131
3232 // Autogenerated by tblgen.
33 void printInstruction(const MCInst *MI, raw_ostream &O);
33 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
34 raw_ostream &O);
3435 static const char *getRegisterName(unsigned RegNo);
3536
36 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
37
38 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
39 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
40
41 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O);
42 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O);
43 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
44 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
37 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
38 raw_ostream &O);
39
40 void printSORegRegOperand(const MCInst *MI, unsigned OpNum,
41 const MCSubtargetInfo &STI, raw_ostream &O);
42 void printSORegImmOperand(const MCInst *MI, unsigned OpNum,
43 const MCSubtargetInfo &STI, raw_ostream &O);
44
45 void printAddrModeTBB(const MCInst *MI, unsigned OpNum,
46 const MCSubtargetInfo &STI, raw_ostream &O);
47 void printAddrModeTBH(const MCInst *MI, unsigned OpNum,
48 const MCSubtargetInfo &STI, raw_ostream &O);
49 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum,
50 const MCSubtargetInfo &STI, raw_ostream &O);
51 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum,
52 const MCSubtargetInfo &STI, raw_ostream &O);
4553 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
46 raw_ostream &O);
54 const MCSubtargetInfo &STI, raw_ostream &O);
4755 void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,
48 raw_ostream &O);
49 template
50 void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
56 const MCSubtargetInfo &STI, raw_ostream &O);
57 template
58 void printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
59 const MCSubtargetInfo &STI, raw_ostream &O);
5160 void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum,
52 raw_ostream &O);
61 const MCSubtargetInfo &STI, raw_ostream &O);
5362 void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O,
5463 bool AlwaysPrintImm0);
5564 void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
56 raw_ostream &O);
57 void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
65 const MCSubtargetInfo &STI, raw_ostream &O);
66 void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
67 const MCSubtargetInfo &STI, raw_ostream &O);
5868 void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
59 raw_ostream &O);
60
61 void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
62 template
63 void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
64 void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
65 void printAddrMode7Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
69 const MCSubtargetInfo &STI, raw_ostream &O);
70
71 void printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
72 const MCSubtargetInfo &STI, raw_ostream &O);
73 template
74 void printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
75 const MCSubtargetInfo &STI, raw_ostream &O);
76 void printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
77 const MCSubtargetInfo &STI, raw_ostream &O);
78 void printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
79 const MCSubtargetInfo &STI, raw_ostream &O);
6680 void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum,
67 raw_ostream &O);
81 const MCSubtargetInfo &STI, raw_ostream &O);
6882
6983 void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum,
84 const MCSubtargetInfo &STI,
7085 raw_ostream &O);
71 void printMemBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
72 void printInstSyncBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
73 void printShiftImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
74 void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
75 void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
86 void printMemBOption(const MCInst *MI, unsigned OpNum,
87 const MCSubtargetInfo &STI, raw_ostream &O);
88 void printInstSyncBOption(const MCInst *MI, unsigned OpNum,
89 const MCSubtargetInfo &STI, raw_ostream &O);
90 void printShiftImmOperand(const MCInst *MI, unsigned OpNum,
91 const MCSubtargetInfo &STI, raw_ostream &O);
92 void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
93 const MCSubtargetInfo &STI, raw_ostream &O);
94 void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
95 const MCSubtargetInfo &STI, raw_ostream &O);
7696
7797 template
78 void printAdrLabelOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
79 void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
80 void printThumbSRImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
81 void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O);
98 void printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
99 const MCSubtargetInfo &STI, raw_ostream &O);
100 void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
101 const MCSubtargetInfo &STI, raw_ostream &O);
102 void printThumbSRImm(const MCInst *MI, unsigned OpNum,
103 const MCSubtargetInfo &STI, raw_ostream &O);
104 void printThumbITMask(const MCInst *MI, unsigned OpNum,
105 const MCSubtargetInfo &STI, raw_ostream &O);
82106 void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum,
83 raw_ostream &O);
107 const MCSubtargetInfo &STI, raw_ostream &O);
84108 void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum,
109 const MCSubtargetInfo &STI,
85110 raw_ostream &O, unsigned Scale);
86111 void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum,
112 const MCSubtargetInfo &STI,
87113 raw_ostream &O);
88114 void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum,
115 const MCSubtargetInfo &STI,
89116 raw_ostream &O);
90117 void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum,
118 const MCSubtargetInfo &STI,
91119 raw_ostream &O);
92120 void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum,
93 raw_ostream &O);
94
95 void printT2SOOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
121 const MCSubtargetInfo &STI, raw_ostream &O);
122
123 void printT2SOOperand(const MCInst *MI, unsigned OpNum,
124 const MCSubtargetInfo &STI, raw_ostream &O);
96125 template
97126 void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
98 raw_ostream &O);
127 const MCSubtargetInfo &STI, raw_ostream &O);
99128 template
100129 void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum,
101 raw_ostream &O);
130 const MCSubtargetInfo &STI, raw_ostream &O);
102131 template
103132 void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum,
104 raw_ostream &O);
133 const MCSubtargetInfo &STI, raw_ostream &O);
105134 void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum,
135 const MCSubtargetInfo &STI,
106136 raw_ostream &O);
107137 void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum,
138 const MCSubtargetInfo &STI,
108139 raw_ostream &O);
109140 void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum,
141 const MCSubtargetInfo &STI,
110142 raw_ostream &O);
111143 void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum,
112 raw_ostream &O);
113
114 void printSetendOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
115 void printCPSIMod(const MCInst *MI, unsigned OpNum, raw_ostream &O);
116 void printCPSIFlag(const MCInst *MI, unsigned OpNum, raw_ostream &O);
117 void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
118 void printBankedRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
119 void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
144 const MCSubtargetInfo &STI, raw_ostream &O);
145
146 void printSetendOperand(const MCInst *MI, unsigned OpNum,
147 const MCSubtargetInfo &STI, raw_ostream &O);
148 void printCPSIMod(const MCInst *MI, unsigned OpNum,
149 const MCSubtargetInfo &STI, raw_ostream &O);
150 void printCPSIFlag(const MCInst *MI, unsigned OpNum,
151 const MCSubtargetInfo &STI, raw_ostream &O);
152 void printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
153 const MCSubtargetInfo &STI, raw_ostream &O);
154 void printBankedRegOperand(const MCInst *MI, unsigned OpNum,
155 const MCSubtargetInfo &STI, raw_ostream &O);
156 void printPredicateOperand(const MCInst *MI, unsigned OpNum,
157 const MCSubtargetInfo &STI, raw_ostream &O);
120158 void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum,
159 const MCSubtargetInfo &STI,
121160 raw_ostream &O);
122161 void printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
123 raw_ostream &O);
124 void printRegisterList(const MCInst *MI, unsigned OpNum, raw_ostream &O);
125 void printNoHashImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O);
126 void printPImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O);
127 void printCImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O);
128 void printCoprocOptionImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
129 void printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
130 void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
131 void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
132 void printRotImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
133 void printModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
134 void printGPRPairOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
135
136 void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
162 const MCSubtargetInfo &STI, raw_ostream &O);
163 void printRegisterList(const MCInst *MI, unsigned OpNum,
164 const MCSubtargetInfo &STI, raw_ostream &O);
165 void printNoHashImmediate(const MCInst *MI, unsigned OpNum,
166 const MCSubtargetInfo &STI, raw_ostream &O);
167 void printPImmediate(const MCInst *MI, unsigned OpNum,
168 const MCSubtargetInfo &STI, raw_ostream &O);
169 void printCImmediate(const MCInst *MI, unsigned OpNum,
170 const MCSubtargetInfo &STI, raw_ostream &O);
171 void printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
172 const MCSubtargetInfo &STI, raw_ostream &O);
173 void printFPImmOperand(const MCInst *MI, unsigned OpNum,
174 const MCSubtargetInfo &STI, raw_ostream &O);
175 void printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
176 const MCSubtargetInfo &STI, raw_ostream &O);
177 void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
178 const MCSubtargetInfo &STI, raw_ostream &O);
179 void printRotImmOperand(const MCInst *MI, unsigned OpNum,
180 const MCSubtargetInfo &STI, raw_ostream &O);
181 void printModImmOperand(const MCInst *MI, unsigned OpNum,
182 const MCSubtargetInfo &STI, raw_ostream &O);
183 void printGPRPairOperand(const MCInst *MI, unsigned OpNum,
184 const MCSubtargetInfo &STI, raw_ostream &O);
185
186 void printPCLabel(const MCInst *MI, unsigned OpNum,
187 const MCSubtargetInfo &STI, raw_ostream &O);
137188 void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
138 raw_ostream &O);
139 void printFBits16(const MCInst *MI, unsigned OpNum, raw_ostream &O);
140 void printFBits32(const MCInst *MI, unsigned OpNum, raw_ostream &O);
141 void printVectorIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
142 void printVectorListOne(const MCInst *MI, unsigned OpNum, raw_ostream &O);
143 void printVectorListTwo(const MCInst *MI, unsigned OpNum, raw_ostream &O);
189 const MCSubtargetInfo &STI, raw_ostream &O);
190 void printFBits16(const MCInst *MI, unsigned OpNum,
191 const MCSubtargetInfo &STI, raw_ostream &O);
192 void printFBits32(const MCInst *MI, unsigned OpNum,
193 const MCSubtargetInfo &STI, raw_ostream &O);
194 void printVectorIndex(const MCInst *MI, unsigned OpNum,
195 const MCSubtargetInfo &STI, raw_ostream &O);
196 void printVectorListOne(const MCInst *MI, unsigned OpNum,
197 const MCSubtargetInfo &STI, raw_ostream &O);
198 void printVectorListTwo(const MCInst *MI, unsigned OpNum,
199 const MCSubtargetInfo &STI, raw_ostream &O);
144200 void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
145 raw_ostream &O);
146 void printVectorListThree(const MCInst *MI, unsigned OpNum, raw_ostream &O);
147 void printVectorListFour(const MCInst *MI, unsigned OpNum, raw_ostream &O);
201 const MCSubtargetInfo &STI, raw_ostream &O);
202 void printVectorListThree(const MCInst *MI, unsigned OpNum,
203 const MCSubtargetInfo &STI, raw_ostream &O);
204 void printVectorListFour(const MCInst *MI, unsigned OpNum,
205 const MCSubtargetInfo &STI, raw_ostream &O);
148206 void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum,
149 raw_ostream &O);
207 const MCSubtargetInfo &STI, raw_ostream &O);
150208 void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum,
151 raw_ostream &O);
209 const MCSubtargetInfo &STI, raw_ostream &O);
152210 void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum,
153 raw_ostream &O);
211 const MCSubtargetInfo &STI, raw_ostream &O);
154212 void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum,
155 raw_ostream &O);
213 const MCSubtargetInfo &STI, raw_ostream &O);
156214 void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum,
215 const MCSubtargetInfo &STI,
157216 raw_ostream &O);
158217 void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum,
218 const MCSubtargetInfo &STI,
159219 raw_ostream &O);
160220 void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum,
221 const MCSubtargetInfo &STI,
161222 raw_ostream &O);
162223 void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum,
163 raw_ostream &O);
224 const MCSubtargetInfo &STI, raw_ostream &O);
164225 void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
165 raw_ostream &O);
226 const MCSubtargetInfo &STI, raw_ostream &O);
166227 };
167228
168229 } // end namespace llvm
0 ; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s
1
2 ; CHECK: dmb ld
3
4 define void @test2() #0 {
5 call void @llvm.arm.dmb(i32 13)
6 ret void
7 }
8
9 declare void @llvm.arm.dmb(i32)
10
11 attributes #0 = { "target-cpu"="cyclone" }