llvm.org GIT mirror llvm / 5732ca0
Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77181 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 11 years ago
7 changed file(s) with 76 addition(s) and 31 deletion(s). Raw diff Collapse all Expand all
635635 if (I != MBB.end()) DL = I->getDebugLoc();
636636
637637 if (RC == ARM::GPRRegisterClass) {
638 AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::STRrr)))
638 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
639639 .addReg(SrcReg, getKillRegState(isKill))
640640 .addFrameIndex(FI).addReg(0).addImm(0));
641641 } else if (RC == ARM::DPRRegisterClass) {
658658 if (I != MBB.end()) DL = I->getDebugLoc();
659659
660660 if (RC == ARM::GPRRegisterClass) {
661 AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::LDRrr)), DestReg)
661 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
662662 .addFrameIndex(FI).addReg(0).addImm(0));
663663 } else if (RC == ARM::DPRRegisterClass) {
664664 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
678678 unsigned OpNum = Ops[0];
679679 unsigned Opc = MI->getOpcode();
680680 MachineInstr *NewMI = NULL;
681 if (Opc == getOpcode(ARMII::MOVr)) {
681 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
682682 // If it is updating CPSR, then it cannot be folded.
683683 if (MI->getOperand(4).getReg() != ARM::CPSR) {
684684 unsigned Pred = MI->getOperand(2).getImm();
687687 unsigned SrcReg = MI->getOperand(1).getReg();
688688 bool isKill = MI->getOperand(1).isKill();
689689 bool isUndef = MI->getOperand(1).isUndef();
690 NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::STRrr)))
691 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
692 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
690 if (Opc == ARM::MOVr)
691 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
692 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
693 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
694 else // ARM::t2MOVr
695 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
696 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
697 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
693698 } else { // move -> load
694699 unsigned DstReg = MI->getOperand(0).getReg();
695700 bool isDead = MI->getOperand(0).isDead();
696701 bool isUndef = MI->getOperand(0).isUndef();
697 NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::LDRrr)))
698 .addReg(DstReg,
699 RegState::Define |
700 getDeadRegState(isDead) |
701 getUndefRegState(isUndef))
702 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
702 if (Opc == ARM::MOVr)
703 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
704 .addReg(DstReg,
705 RegState::Define |
706 getDeadRegState(isDead) |
707 getUndefRegState(isUndef))
708 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
709 else // ARM::t2MOVr
710 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
711 .addReg(DstReg,
712 RegState::Define |
713 getDeadRegState(isDead) |
714 getUndefRegState(isUndef))
715 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
703716 }
704717 }
705718 }
766779 if (Ops.size() != 1) return false;
767780
768781 unsigned Opc = MI->getOpcode();
769 if (Opc == getOpcode(ARMII::MOVr)) {
782 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
770783 // If it is updating CPSR, then it cannot be folded.
771784 return MI->getOperand(4).getReg() != ARM::CPSR;
772785 } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) {
167167 B,
168168 Bcc,
169169 BX_RET,
170 LDRrr,
171170 LDRri,
172171 MOVr,
173 STRrr,
174172 STRri,
175173 SUBri,
176174 SUBrs,
270268 unsigned DestReg, unsigned SrcReg,
271269 const TargetRegisterClass *DestRC,
272270 const TargetRegisterClass *SrcRC) const;
271
273272 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
274273 MachineBasicBlock::iterator MBBI,
275274 unsigned SrcReg, bool isKill, int FrameIndex,
13041304
13051305 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
13061306 emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size);
1307 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STRrr),
1308 getOpcode(ARMII::STRri), 1, STI);
1307 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
13091308
13101309 // Darwin ABI requires FP to point to the stack slot that contains the
13111310 // previous FP.
13201319 emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size);
13211320
13221321 // Build the new SUBri to adjust SP for FP callee-save spill area.
1323 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STRrr),
1324 getOpcode(ARMII::STRri), 2, STI);
1322 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
13251323 emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize);
13261324
13271325 // Determine starting offsets of spill areas.
13611359 const ARMBaseInstrInfo &TII,
13621360 const unsigned *CSRegs) {
13631361 return ((MI->getOpcode() == (int)ARM::FLDD ||
1364 MI->getOpcode() == (int)TII.getOpcode(ARMII::LDRrr) ||
1365 MI->getOpcode() == (int)TII.getOpcode(ARMII::LDRri)) &&
1362 MI->getOpcode() == (int)ARM::LDR ||
1363 MI->getOpcode() == (int)ARM::t2LDRi12) &&
13661364 MI->getOperand(1).isFI() &&
13671365 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
13681366 }
14271425 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize());
14281426
14291427 // Move SP to start of integer callee save spill area 1.
1430 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDRrr),
1431 getOpcode(ARMII::LDRri), 2, STI);
1428 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
14321429 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size());
14331430
14341431 // Move SP to SP upon entry to the function.
1435 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDRrr),
1436 getOpcode(ARMII::LDRri), 1, STI);
1432 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
14371433 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size());
14381434 }
14391435
7070 case ARMII::B: return ARM::B;
7171 case ARMII::Bcc: return ARM::Bcc;
7272 case ARMII::BX_RET: return ARM::BX_RET;
73 case ARMII::LDRrr: return ARM::LDR;
7473 case ARMII::LDRri: return 0;
7574 case ARMII::MOVr: return ARM::MOVr;
76 case ARMII::STRrr: return ARM::STR;
7775 case ARMII::STRri: return 0;
7876 case ARMII::SUBri: return ARM::SUBri;
7977 case ARMII::SUBrs: return ARM::SUBrs;
3737 case ARMII::B: return ARM::tB;
3838 case ARMII::Bcc: return ARM::tBcc;
3939 case ARMII::BX_RET: return ARM::tBX_RET;
40 case ARMII::LDRrr: return ARM::tLDR;
4140 case ARMII::LDRri: return 0;
4241 case ARMII::MOVr: return ARM::tMOVr;
43 case ARMII::STRrr: return ARM::tSTR;
4442 case ARMII::STRri: return 0;
4543 case ARMII::SUBri: return ARM::tSUBi8;
4644 case ARMII::SUBrs: return 0;
3838 case ARMII::B: return ARM::t2B;
3939 case ARMII::Bcc: return ARM::t2Bcc;
4040 case ARMII::BX_RET: return ARM::tBX_RET;
41 case ARMII::LDRrr: return ARM::t2LDRs;
4241 case ARMII::LDRri: return ARM::t2LDRi12;
4342 case ARMII::MOVr: return ARM::t2MOVr;
44 case ARMII::STRrr: return ARM::t2STRs;
4543 case ARMII::STRri: return ARM::t2STRi12;
4644 case ARMII::SUBri: return ARM::t2SUBri;
4745 case ARMII::SUBrs: return ARM::t2SUBrs;
10199 // Handle SPR, DPR, and QPR copies.
102100 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
103101 }
102
103 void Thumb2InstrInfo::
104 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
105 unsigned SrcReg, bool isKill, int FI,
106 const TargetRegisterClass *RC) const {
107 DebugLoc DL = DebugLoc::getUnknownLoc();
108 if (I != MBB.end()) DL = I->getDebugLoc();
109
110 if (RC == ARM::GPRRegisterClass) {
111 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
112 .addReg(SrcReg, getKillRegState(isKill))
113 .addFrameIndex(FI).addImm(0));
114 return;
115 }
116
117 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC);
118 }
119
120 void Thumb2InstrInfo::
121 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
122 unsigned DestReg, int FI,
123 const TargetRegisterClass *RC) const {
124 DebugLoc DL = DebugLoc::getUnknownLoc();
125 if (I != MBB.end()) DL = I->getDebugLoc();
126
127 if (RC == ARM::GPRRegisterClass) {
128 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
129 .addFrameIndex(FI).addImm(0));
130 return;
131 }
132
133 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC);
134 }
4242 const TargetRegisterClass *DestRC,
4343 const TargetRegisterClass *SrcRC) const;
4444
45 void storeRegToStackSlot(MachineBasicBlock &MBB,
46 MachineBasicBlock::iterator MBBI,
47 unsigned SrcReg, bool isKill, int FrameIndex,
48 const TargetRegisterClass *RC) const;
49
50 void loadRegFromStackSlot(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator MBBI,
52 unsigned DestReg, int FrameIndex,
53 const TargetRegisterClass *RC) const;
54
4555 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
4656 /// such, whenever a client has an instance of instruction info, it should
4757 /// always be able to get register info as well (through this method).