llvm.org GIT mirror llvm / 57148c1
Don't cache the instruction and register info from the TargetMachine, because the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183488 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 7 years ago
15 changed file(s) with 48 addition(s) and 42 deletion(s). Raw diff Collapse all Expand all
112112 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
113113 const ScheduleDAG *DAG) const {
114114 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
115 return (ScheduleHazardRecognizer *)
116 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
115 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
117116 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
118117 }
119118
4545 MachineBasicBlock::iterator &MBBI,
4646 LiveVariables *LV) const;
4747
48 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
48 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
4949 const ARMSubtarget &getSubtarget() const { return Subtarget; }
5050
5151 ScheduleHazardRecognizer *
4242
4343 using namespace llvm;
4444
45 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
46 const ARMSubtarget &sti)
47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), TII(tii), STI(sti),
45 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti)
46 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti),
4847 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
4948 BasePtr(ARM::R6) {
5049 }
375374 ARMCC::CondCodes Pred,
376375 unsigned PredReg, unsigned MIFlags) const {
377376 MachineFunction &MF = *MBB.getParent();
377 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
378378 MachineConstantPool *ConstantPool = MF.getConstantPool();
379379 const Constant *C =
380380 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
556556 if (Ins != MBB->end())
557557 DL = Ins->getDebugLoc();
558558
559 const MachineFunction &MF = *MBB->getParent();
560 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
561 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
559562 const MCInstrDesc &MCID = TII.get(ADDriOpc);
560 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
561 const MachineFunction &MF = *MBB->getParent();
562563 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
563564
564565 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
574575 MachineInstr &MI = *I;
575576 MachineBasicBlock &MBB = *MI.getParent();
576577 MachineFunction &MF = *MBB.getParent();
578 const ARMBaseInstrInfo &TII =
579 *static_cast(MF.getTarget().getInstrInfo());
577580 ARMFunctionInfo *AFI = MF.getInfo();
578581 int Off = Offset; // ARM doesn't need the general 64-bit offsets
579582 unsigned i = 0;
671674 MachineInstr &MI = *II;
672675 MachineBasicBlock &MBB = *MI.getParent();
673676 MachineFunction &MF = *MBB.getParent();
677 const ARMBaseInstrInfo &TII =
678 *static_cast(MF.getTarget().getInstrInfo());
674679 const ARMFrameLowering *TFI =
675680 static_cast(MF.getTarget().getFrameLowering());
676681 ARMFunctionInfo *AFI = MF.getInfo();
7373
7474 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
7575 protected:
76 const ARMBaseInstrInfo &TII;
7776 const ARMSubtarget &STI;
7877
7978 /// FramePtr - ARM physical register used as frame ptr.
8584 unsigned BasePtr;
8685
8786 // Can be only subclassed.
88 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
89 const ARMSubtarget &STI);
87 explicit ARMBaseRegisterInfo(const ARMSubtarget &STI);
9088
9189 // Return the opcode that implements 'Op', or 0 if no opcode
9290 unsigned getOpcode(int Op) const;
4343 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
4444 MachineInstr *DefMI = LastMI;
4545 const MCInstrDesc &LastMCID = LastMI->getDesc();
46 const TargetMachine &TM =
47 MI->getParent()->getParent()->getTarget();
48 const ARMBaseInstrInfo &TII =
49 *static_cast(TM.getInstrInfo());
50
4651 // Skip over one non-VFP / NEON instruction.
4752 if (!LastMI->isBarrier() &&
4853 // On A9, AGU and NEON/FPU are muxed.
49 !(STI.isLikeA9() && (LastMI->mayLoad() || LastMI->mayStore())) &&
54 !(TII.getSubtarget().isLikeA9() &&
55 (LastMI->mayLoad() || LastMI->mayStore())) &&
5056 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
5157 MachineBasicBlock::iterator I = LastMI;
5258 if (I != LastMI->getParent()->begin()) {
5763
5864 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
5965 (TII.canCauseFpMLxStall(MI->getOpcode()) ||
60 hasRAWHazard(DefMI, MI, TRI))) {
66 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
6167 // Try to schedule another instruction for the next 4 cycles.
6268 if (FpMLxStalls == 0)
6369 FpMLxStalls = 4;
2727 /// ARM preRA scheduler uses an unspecialized instance of the
2828 /// ScoreboardHazardRecognizer.
2929 class ARMHazardRecognizer : public ScoreboardHazardRecognizer {
30 const ARMBaseInstrInfo &TII;
31 const ARMBaseRegisterInfo &TRI;
32 const ARMSubtarget &STI;
33
3430 MachineInstr *LastMI;
3531 unsigned FpMLxStalls;
3632
3733 public:
3834 ARMHazardRecognizer(const InstrItineraryData *ItinData,
39 const ARMBaseInstrInfo &tii,
40 const ARMBaseRegisterInfo &tri,
41 const ARMSubtarget &sti,
42 const ScheduleDAG *DAG) :
43 ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), TII(tii),
44 TRI(tri), STI(sti), LastMI(0) {}
35 const ScheduleDAG *DAG)
36 : ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"),
37 LastMI(0) {}
4538
4639 virtual HazardType getHazardType(SUnit *SU, int Stalls);
4740 virtual void Reset();
2828 using namespace llvm;
2929
3030 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
31 : ARMBaseInstrInfo(STI), RI(*this, STI) {
31 : ARMBaseInstrInfo(STI), RI(STI) {
3232 }
3333
3434 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
1717
1818 void ARMRegisterInfo::anchor() { }
1919
20 ARMRegisterInfo::ARMRegisterInfo(const ARMBaseInstrInfo &tii,
21 const ARMSubtarget &sti)
22 : ARMBaseRegisterInfo(tii, sti) {
20 ARMRegisterInfo::ARMRegisterInfo(const ARMSubtarget &sti)
21 : ARMBaseRegisterInfo(sti) {
2322 }
1818 #include "llvm/Target/TargetRegisterInfo.h"
1919
2020 namespace llvm {
21 class ARMSubtarget;
22 class ARMBaseInstrInfo;
21
22 class ARMSubtarget;
2323
2424 struct ARMRegisterInfo : public ARMBaseRegisterInfo {
2525 virtual void anchor();
2626 public:
27 ARMRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
27 ARMRegisterInfo(const ARMSubtarget &STI);
2828 };
2929
3030 } // end namespace llvm
2121 using namespace llvm;
2222
2323 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
24 : ARMBaseInstrInfo(STI), RI(*this, STI) {
24 : ARMBaseInstrInfo(STI), RI(STI) {
2525 }
2626
2727 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3939
4040 using namespace llvm;
4141
42 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
43 const ARMSubtarget &sti)
44 : ARMBaseRegisterInfo(tii, sti) {
42 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMSubtarget &sti)
43 : ARMBaseRegisterInfo(sti) {
4544 }
4645
4746 const TargetRegisterClass*
6968 ARMCC::CondCodes Pred, unsigned PredReg,
7069 unsigned MIFlags) const {
7170 MachineFunction &MF = *MBB.getParent();
71 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
7272 MachineConstantPool *ConstantPool = MF.getConstantPool();
7373 const Constant *C = ConstantInt::get(
7474 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
487487 Thumb1RegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
488488 unsigned BaseReg, int64_t Offset) const {
489489 MachineInstr &MI = *I;
490 const ARMBaseInstrInfo &TII =
491 *static_cast(
492 MI.getParent()->getParent()->getTarget().getInstrInfo());
490493 int Off = Offset; // ARM doesn't need the general 64-bit offsets
491494 unsigned i = 0;
492495
512515 // off the frame pointer (if, for example, there are alloca() calls in
513516 // the function, the offset will be negative. Use R12 instead since that's
514517 // a call clobbered register that we know won't be used in Thumb1 mode.
518 const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo();
515519 DebugLoc DL;
516520 AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
517521 .addReg(ARM::R12, RegState::Define)
557561 MachineInstr &MI = *II;
558562 MachineBasicBlock &MBB = *MI.getParent();
559563 MachineFunction &MF = *MBB.getParent();
564 const ARMBaseInstrInfo &TII =
565 *static_cast(MF.getTarget().getInstrInfo());
560566 ARMFunctionInfo *AFI = MF.getInfo();
561567 DebugLoc dl = MI.getDebugLoc();
562568 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
2424
2525 struct Thumb1RegisterInfo : public ARMBaseRegisterInfo {
2626 public:
27 Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
27 Thumb1RegisterInfo(const ARMSubtarget &STI);
2828
2929 const TargetRegisterClass*
3030 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
3030 cl::init(false));
3131
3232 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
33 : ARMBaseInstrInfo(STI), RI(*this, STI) {
33 : ARMBaseInstrInfo(STI), RI(STI) {
3434 }
3535
3636 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
2323 #include "llvm/IR/Function.h"
2424 using namespace llvm;
2525
26 Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMBaseInstrInfo &tii,
27 const ARMSubtarget &sti)
28 : ARMBaseRegisterInfo(tii, sti) {
26 Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMSubtarget &sti)
27 : ARMBaseRegisterInfo(sti) {
2928 }
3029
3130 /// emitLoadConstPool - Emits a load from constpool to materialize the
3938 ARMCC::CondCodes Pred, unsigned PredReg,
4039 unsigned MIFlags) const {
4140 MachineFunction &MF = *MBB.getParent();
41 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
4242 MachineConstantPool *ConstantPool = MF.getConstantPool();
4343 const Constant *C = ConstantInt::get(
4444 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
1919 #include "llvm/Target/TargetRegisterInfo.h"
2020
2121 namespace llvm {
22 class ARMSubtarget;
23 class ARMBaseInstrInfo;
22
23 class ARMSubtarget;
2424
2525 struct Thumb2RegisterInfo : public ARMBaseRegisterInfo {
2626 public:
27 Thumb2RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
27 Thumb2RegisterInfo(const ARMSubtarget &STI);
2828
2929 /// emitLoadConstPool - Emits a load from constpool to materialize the
3030 /// specified immediate.