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Merging r330186: ------------------------------------------------------------------------ r330186 | nemanjai | 2018-04-17 06:07:01 -0700 (Tue, 17 Apr 2018) | 11 lines [PowerPC] Mark the BDNZ intrinsic as NoDuplicate Duplicating this intrinsic is not generally valid because it has the side-effect of decrementing the CTR. Any passes that duplicate it would need to be taught to keep the regions formed completely disjoint. This patch should be NFC for typical uses as CTRLoops runs after the remaining loop passes. It only affects situations where the loop passes are scheduled on the IR after the codegen passes (as is the case with some JIT pipelines). Fixes https://bugs.llvm.org/show_bug.cgi?id=37050 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@331716 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 years ago
2 changed file(s) with 80 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
3535
3636 // Intrinsics used to generate ctr-based loops. These should only be
3737 // generated by the PowerPC backend!
38 // The branch intrinsic is marked as NoDuplicate because loop rotation will
39 // attempt to duplicate it forming loops where a block reachable from one
40 // instance of it can contain another.
3841 def int_ppc_mtctr : Intrinsic<[], [llvm_anyint_ty], []>;
39 def int_ppc_is_decremented_ctr_nonzero : Intrinsic<[llvm_i1_ty], [], []>;
42 def int_ppc_is_decremented_ctr_nonzero :
43 Intrinsic<[llvm_i1_ty], [], [IntrNoDuplicate]>;
4044
4145 // Intrinsics for [double]word extended forms of divide instructions
4246 def int_ppc_divwe : GCCBuiltin<"__builtin_divwe">,
0 ; RUN: opt -early-cse-memssa -loop-rotate -licm -loop-rotate -S %s -o - | FileCheck %s
1 ; ModuleID = 'bugpoint-reduced-simplified.bc'
2 source_filename = "bugpoint-output-8903f29.bc"
3 target datalayout = "e-m:e-i64:64-n32:64"
4 target triple = "powerpc64le-unknown-linux-gnu"
5
6 define void @test(i64 %arg.ssa, i64 %arg.nb) local_unnamed_addr {
7 ; Ensure that loop rotation doesn't duplicate the call to
8 ; llvm.ppc.is.decremented.ctr.nonzero
9 ; CHECK-LABEL: test
10 ; CHECK: call i1 @llvm.ppc.is.decremented.ctr.nonzero
11 ; CHECK-NOT: call i1 @llvm.ppc.is.decremented.ctr.nonzero
12 ; CHECK: declare i1 @llvm.ppc.is.decremented.ctr.nonzero
13 entry:
14 switch i32 undef, label %BB_8 [
15 i32 -2, label %BB_9
16 i32 0, label %BB_9
17 ]
18
19 BB_1: ; preds = %BB_12, %BB_4
20 %bcount.1.us = phi i64 [ %.810.us, %BB_4 ], [ 0, %BB_12 ]
21 %0 = add i64 %arg.ssa, %bcount.1.us
22 %.568.us = load i32, i32* undef, align 4
23 %.15.i.us = icmp slt i32 0, %.568.us
24 br i1 %.15.i.us, label %BB_3, label %BB_2
25
26 BB_2: ; preds = %BB_1
27 %.982.us = add nsw i64 %0, 1
28 unreachable
29
30 BB_3: ; preds = %BB_1
31 %1 = add i64 %arg.ssa, %bcount.1.us
32 %2 = add i64 %1, 1
33 %3 = call i1 @llvm.ppc.is.decremented.ctr.nonzero()
34 br i1 %3, label %BB_4, label %BB_7
35
36 BB_4: ; preds = %BB_3
37 %.810.us = add nuw nsw i64 %bcount.1.us, 1
38 br label %BB_1
39
40 BB_5: ; preds = %BB_7, %BB_5
41 %lsr.iv20.i116 = phi i64 [ %2, %BB_7 ], [ %lsr.iv.next21.i126, %BB_5 ]
42 %lsr.iv.next21.i126 = add i64 %lsr.iv20.i116, 1
43 br i1 undef, label %BB_5, label %BB_6
44
45 BB_6: ; preds = %BB_5
46 ret void
47
48 BB_7: ; preds = %BB_3
49 br label %BB_5
50
51 BB_8: ; preds = %entry
52 ret void
53
54 BB_9: ; preds = %entry, %entry
55 br label %BB_10
56
57 BB_10: ; preds = %BB_9
58 br label %BB_11
59
60 BB_11: ; preds = %BB_11, %BB_10
61 br i1 undef, label %BB_11, label %BB_12
62
63 BB_12: ; preds = %BB_11
64 call void @llvm.ppc.mtctr.i64(i64 %arg.nb)
65 br label %BB_1
66 }
67
68 ; Function Attrs: nounwind
69 declare void @llvm.ppc.mtctr.i64(i64) #0
70
71 ; Function Attrs: nounwind
72 declare i1 @llvm.ppc.is.decremented.ctr.nonzero() #0
73
74 attributes #0 = { nounwind }