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Merging r231659: ------------------------------------------------------------------------ r231659 | marek.olsak | 2015-03-09 11:48:09 -0400 (Mon, 09 Mar 2015) | 4 lines R600/SI: Limit SGPRs to 80 on Tonga and Iceland This is a candidate for stable. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236038 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 5 years ago
7 changed file(s) with 51 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
9595 "EnableVGPRSpilling",
9696 "true",
9797 "Enable spilling of VGPRs to scratch memory">;
98
99 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
100 "SGPRInitBug",
101 "true",
102 "VI SGPR initilization bug requiring a fixed SGPR allocation size">;
98103
99104 class SubtargetFeatureFetchLimit :
100105 SubtargetFeature <"fetch"#Value,
341341 // number of registers.
342342 ProgInfo.NumVGPR = MaxVGPR + 1;
343343 ProgInfo.NumSGPR = MaxSGPR + 1;
344
345 if (STM.hasSGPRInitBug()) {
346 if (ProgInfo.NumSGPR > AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG)
347 llvm_unreachable("Too many SGPRs used with the SGPR init bug");
348
349 ProgInfo.NumSGPR = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
350 }
344351
345352 ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
346353 ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
7979 FlatAddressSpace(false), EnableIRStructurizer(true),
8080 EnablePromoteAlloca(false), EnableIfCvt(true),
8181 EnableLoadStoreOpt(false), WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
82 EnableVGPRSpilling(false),
82 EnableVGPRSpilling(false),SGPRInitBug(false),
8383 DL(computeDataLayout(initializeSubtargetDependencies(GPU, FS))),
8484 FrameLowering(TargetFrameLowering::StackGrowsUp,
8585 64 * 16, // Maximum stack alignment (long16)
4242 SOUTHERN_ISLANDS,
4343 SEA_ISLANDS,
4444 VOLCANIC_ISLANDS,
45 };
46
47 enum {
48 FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
4549 };
4650
4751 private:
6569 bool CFALUBug;
6670 int LocalMemorySize;
6771 bool EnableVGPRSpilling;
72 bool SGPRInitBug;
6873
6974 const DataLayout DL;
7075 AMDGPUFrameLowering FrameLowering;
202207 return LocalMemorySize;
203208 }
204209
210 bool hasSGPRInitBug() const {
211 return SGPRInitBug;
212 }
213
205214 unsigned getAmdKernelCodeChipID() const;
206215
207216 bool enableMachineScheduler() const override {
112112 // Volcanic Islands
113113 //===----------------------------------------------------------------------===//
114114
115 def : ProcessorModel<"tonga", SIQuarterSpeedModel, [FeatureVolcanicIslands]>;
115 def : ProcessorModel<"tonga", SIQuarterSpeedModel,
116 [FeatureVolcanicIslands, FeatureSGPRInitBug]
117 >;
116118
117 def : ProcessorModel<"iceland", SIQuarterSpeedModel, [FeatureVolcanicIslands]>;
119 def : ProcessorModel<"iceland", SIQuarterSpeedModel,
120 [FeatureVolcanicIslands, FeatureSGPRInitBug]
121 >;
118122
119123 def : ProcessorModel<"carrizo", SIQuarterSpeedModel, [FeatureVolcanicIslands]>;
4444 // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
4545 Reserved.set(AMDGPU::VGPR255);
4646 Reserved.set(AMDGPU::VGPR254);
47
48 // Tonga and Iceland can only allocate a fixed number of SGPRs due
49 // to a hw bug.
50 if (ST.hasSGPRInitBug()) {
51 unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
52 // Reserve some SGPRs for FLAT_SCRATCH and VCC (4 SGPRs).
53 // Assume XNACK_MASK is unused.
54 unsigned Limit = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG - 4;
55
56 for (unsigned i = Limit; i < NumSGPRs; ++i) {
57 unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
58 MCRegAliasIterator R = MCRegAliasIterator(Reg, this, true);
59
60 for (; R.isValid(); ++R)
61 Reserved.set(*R);
62 }
63 }
4764
4865 return Reserved;
4966 }
0 ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s
1 ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG %s
1 ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s
22 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s
3 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG %s
3 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TONGA %s
4 ; RUN: llc < %s -march=amdgcn -mcpu=carrizo -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s
5 ; RUN: llc < %s -march=amdgcn -mcpu=carrizo -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s
46
57 ; ELF: Format: ELF32
68 ; ELF: Name: .AMDGPU.config
1416 ; CONFIG: test:
1517 ; CONFIG: .section .AMDGPU.config
1618 ; CONFIG-NEXT: .long 45096
17 ; CONFIG-NEXT: .long 0
19 ; TYPICAL-NEXT: .long 0
20 ; TONGA-NEXT: .long 576
1821 define void @test(i32 %p) #0 {
1922 %i = add i32 %p, 2
2023 %r = bitcast i32 %i to float