llvm.org GIT mirror llvm / 567409d
CodeGen: Use MachineInstr& in TargetInstrInfo, NFC This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274189 91177308-0d34-0410-b5e6-96231b3b80d8 Duncan P. N. Exon Smith 3 years ago
92 changed file(s) with 3385 addition(s) and 3430 deletion(s). Raw diff Collapse all Expand all
7777 /// This means the only allowed uses are constants and unallocatable physical
7878 /// registers so that the instructions result is independent of the place
7979 /// in the function.
80 bool isTriviallyReMaterializable(const MachineInstr *MI,
80 bool isTriviallyReMaterializable(const MachineInstr &MI,
8181 AliasAnalysis *AA = nullptr) const {
82 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
83 (MI->getDesc().isRematerializable() &&
82 return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
83 (MI.getDesc().isRematerializable() &&
8484 (isReallyTriviallyReMaterializable(MI, AA) ||
8585 isReallyTriviallyReMaterializableGeneric(MI, AA)));
8686 }
9393 /// than producing a value, or if it requres any address registers that are
9494 /// not always available.
9595 /// Requirements must be check as stated in isTriviallyReMaterializable() .
96 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
96 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
9797 AliasAnalysis *AA) const {
9898 return false;
9999 }
113113 /// Do not call this method for a non-commutable instruction.
114114 /// Even though the instruction is commutable, the method may still
115115 /// fail to commute the operands, null pointer is returned in such cases.
116 virtual MachineInstr *commuteInstructionImpl(MachineInstr *MI,
117 bool NewMI,
116 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
118117 unsigned OpIdx1,
119118 unsigned OpIdx2) const;
120119
138137 /// set and the target hook isReallyTriviallyReMaterializable returns false,
139138 /// this function does target-independent tests to determine if the
140139 /// instruction is really trivially rematerializable.
141 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
140 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
142141 AliasAnalysis *AA) const;
143142
144143 public:
156155 /// as part of a call sequence. By default, only call frame setup/destroy
157156 /// instructions adjust the stack, but targets may want to override this
158157 /// to enable more fine-grained adjustment, or adjust by a different value.
159 virtual int getSPAdjust(const MachineInstr *MI) const;
158 virtual int getSPAdjust(const MachineInstr &MI) const;
160159
161160 /// Return true if the instruction is a "coalescable" extension instruction.
162161 /// That is, it's like a copy where it's legal for the source to overlap the
174173 /// the destination along with the FrameIndex of the loaded stack slot. If
175174 /// not, return 0. This predicate must return 0 if the instruction has
176175 /// any side effects other than loading from the stack slot.
177 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
176 virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
178177 int &FrameIndex) const {
179178 return 0;
180179 }
181180
182181 /// Check for post-frame ptr elimination stack locations as well.
183182 /// This uses a heuristic so it isn't reliable for correctness.
184 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
183 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
185184 int &FrameIndex) const {
186185 return 0;
187186 }
192191 /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
193192 /// any instructions that loads from the stack. This is just a hint, as some
194193 /// cases may be missed.
195 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
194 virtual bool hasLoadFromStackSlot(const MachineInstr &MI,
196195 const MachineMemOperand *&MMO,
197196 int &FrameIndex) const;
198197
201200 /// the source reg along with the FrameIndex of the loaded stack slot. If
202201 /// not, return 0. This predicate must return 0 if the instruction has
203202 /// any side effects other than storing to the stack slot.
204 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
203 virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
205204 int &FrameIndex) const {
206205 return 0;
207206 }
208207
209208 /// Check for post-frame ptr elimination stack locations as well.
210209 /// This uses a heuristic, so it isn't reliable for correctness.
211 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
210 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
212211 int &FrameIndex) const {
213212 return 0;
214213 }
219218 /// If not, return false. Unlike isStoreToStackSlot,
220219 /// this returns true for any instructions that stores to the
221220 /// stack. This is just a hint, as some cases may be missed.
222 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
221 virtual bool hasStoreToStackSlot(const MachineInstr &MI,
223222 const MachineMemOperand *&MMO,
224223 int &FrameIndex) const;
225224
226225 /// Return true if the specified machine instruction
227226 /// is a copy of one stack slot to another and has no other effect.
228227 /// Provide the identity of the two frame indices.
229 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
228 virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
230229 int &SrcFrameIndex) const {
231230 return false;
232231 }
252251 ///
253252 /// Targets for different archs need to override this, and different
254253 /// micro-architectures can also be finely tuned inside.
255 virtual bool isAsCheapAsAMove(const MachineInstr *MI) const {
256 return MI->isAsCheapAsAMove();
254 virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
255 return MI.isAsCheapAsAMove();
257256 }
258257
259258 /// Return true if the instruction should be sunk by MachineSink.
274273 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
275274 /// SubIdx.
276275 virtual void reMaterialize(MachineBasicBlock &MBB,
277 MachineBasicBlock::iterator MI,
278 unsigned DestReg, unsigned SubIdx,
279 const MachineInstr *Orig,
276 MachineBasicBlock::iterator MI, unsigned DestReg,
277 unsigned SubIdx, const MachineInstr &Orig,
280278 const TargetRegisterInfo &TRI) const;
281279
282280 /// Create a duplicate of the Orig instruction in MF. This is like
284282 /// that are required to be unique.
285283 ///
286284 /// The instruction must be duplicable as indicated by isNotDuplicable().
287 virtual MachineInstr *duplicate(MachineInstr *Orig,
285 virtual MachineInstr *duplicate(MachineInstr &Orig,
288286 MachineFunction &MF) const;
289287
290288 /// This method must be implemented by targets that
297295 /// This method returns a null pointer if the transformation cannot be
298296 /// performed, otherwise it returns the last new instruction.
299297 ///
300 virtual MachineInstr *
301 convertToThreeAddress(MachineFunction::iterator &MFI,
302 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
298 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
299 MachineInstr &MI,
300 LiveVariables *LV) const {
303301 return nullptr;
304302 }
305303
326324 /// Even though the instruction is commutable, the method may still
327325 /// fail to commute the operands, null pointer is returned in such cases.
328326 MachineInstr *
329 commuteInstruction(MachineInstr *MI,
330 bool NewMI = false,
327 commuteInstruction(MachineInstr &MI, bool NewMI = false,
331328 unsigned OpIdx1 = CommuteAnyOperandIndex,
332329 unsigned OpIdx2 = CommuteAnyOperandIndex) const;
333330
348345 /// findCommutedOpIndices(MI, Op1, Op2);
349346 /// can be interpreted as a query asking to find an operand that would be
350347 /// commutable with the operand#1.
351 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
348 virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
352349 unsigned &SrcOpIdx2) const;
353350
354351 /// A pair composed of a register and a sub-register index.
435432 /// are deemed identical except for defs. If this function is called when the
436433 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
437434 /// aggressive checks.
438 virtual bool produceSameValue(const MachineInstr *MI0,
439 const MachineInstr *MI1,
435 virtual bool produceSameValue(const MachineInstr &MI0,
436 const MachineInstr &MI1,
440437 const MachineRegisterInfo *MRI = nullptr) const;
441438
442439 /// Analyze the branching code at the end of MBB, returning
712709 /// @param FalseOp Operand number of the value selected when Cond is false.
713710 /// @param Optimizable Returned as true if MI is optimizable.
714711 /// @returns False on success.
715 virtual bool analyzeSelect(const MachineInstr *MI,
712 virtual bool analyzeSelect(const MachineInstr &MI,
716713 SmallVectorImpl &Cond,
717714 unsigned &TrueOp, unsigned &FalseOp,
718715 bool &Optimizable) const {
719 assert(MI && MI->getDesc().isSelect() && "MI must be a select instruction");
716 assert(MI.getDesc().isSelect() && "MI must be a select instruction");
720717 return true;
721718 }
722719
735732 /// MI. Has to be updated with any newly created MI or deleted ones.
736733 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
737734 /// @returns Optimized instruction or NULL.
738 virtual MachineInstr *optimizeSelect(MachineInstr *MI,
735 virtual MachineInstr *optimizeSelect(MachineInstr &MI,
739736 SmallPtrSetImpl &NewMIs,
740737 bool PreferFalse = false) const {
741738 // This function must be implemented if Optimizable is ever set.
788785 /// into real instructions. The target can edit MI in place, or it can insert
789786 /// new instructions and erase MI. The function should return true if
790787 /// anything was changed.
791 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
792 return false;
793 }
788 virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
794789
795790 /// Attempt to fold a load or store of the specified stack
796791 /// slot into the specified machine instruction for the specified operand(s).
798793 /// operand folded, otherwise NULL is returned.
799794 /// The new instruction is inserted before MI, and the client is responsible
800795 /// for removing the old instruction.
801 MachineInstr *foldMemoryOperand(MachineBasicBlock::iterator MI,
802 ArrayRef Ops, int FrameIndex,
796 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef Ops,
797 int FrameIndex,
803798 LiveIntervals *LIS = nullptr) const;
804799
805800 /// Same as the previous version except it allows folding of any load and
806801 /// store from / to any address, not just from a specific stack slot.
807 MachineInstr *foldMemoryOperand(MachineBasicBlock::iterator MI,
808 ArrayRef Ops,
809 MachineInstr *LoadMI,
802 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef Ops,
803 MachineInstr &LoadMI,
810804 LiveIntervals *LIS = nullptr) const;
811805
812806 /// Return true when there is potentially a faster code sequence
884878 /// take care of adding a MachineMemOperand to the newly created instruction.
885879 /// The instruction and any auxiliary instructions necessary will be inserted
886880 /// at InsertPt.
887 virtual MachineInstr *foldMemoryOperandImpl(
888 MachineFunction &MF, MachineInstr *MI, ArrayRef Ops,
889 MachineBasicBlock::iterator InsertPt, int FrameIndex,
890 LiveIntervals *LIS = nullptr) const {
881 virtual MachineInstr *
882 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
883 ArrayRef Ops,
884 MachineBasicBlock::iterator InsertPt, int FrameIndex,
885 LiveIntervals *LIS = nullptr) const {
891886 return nullptr;
892887 }
893888
897892 /// The instruction and any auxiliary instructions necessary will be inserted
898893 /// at InsertPt.
899894 virtual MachineInstr *foldMemoryOperandImpl(
900 MachineFunction &MF, MachineInstr *MI, ArrayRef Ops,
901 MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI,
895 MachineFunction &MF, MachineInstr &MI, ArrayRef Ops,
896 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
902897 LiveIntervals *LIS = nullptr) const {
903898 return nullptr;
904899 }
950945 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
951946 /// a store or a load and a store into two or more instruction. If this is
952947 /// possible, returns true as well as the new instructions by reference.
953 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
954 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
955 SmallVectorImpl &NewMIs) const{
948 virtual bool
949 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
950 bool UnfoldLoad, bool UnfoldStore,
951 SmallVectorImpl &NewMIs) const {
956952 return false;
957953 }
958954
998994
999995 /// Get the base register and byte offset of an instruction that reads/writes
1000996 /// memory.
1001 virtual bool getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg,
997 virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
1002998 int64_t &Offset,
1003999 const TargetRegisterInfo *TRI) const {
10041000 return false;
10081004
10091005 virtual bool enableClusterStores() const { return false; }
10101006
1011 virtual bool shouldClusterMemOps(MachineInstr *FirstLdSt,
1012 MachineInstr *SecondLdSt,
1007 virtual bool shouldClusterMemOps(MachineInstr &FirstLdSt,
1008 MachineInstr &SecondLdSt,
10131009 unsigned NumLoads) const {
10141010 return false;
10151011 }
10161012
10171013 /// Can this target fuse the given instructions if they are scheduled
10181014 /// adjacent.
1019 virtual bool shouldScheduleAdjacent(MachineInstr* First,
1020 MachineInstr *Second) const {
1015 virtual bool shouldScheduleAdjacent(MachineInstr &First,
1016 MachineInstr &Second) const {
10211017 return false;
10221018 }
10231019
10821078
10831079 /// Test if the given instruction should be considered a scheduling boundary.
10841080 /// This primarily includes labels and terminators.
1085 virtual bool isSchedulingBoundary(const MachineInstr *MI,
1081 virtual bool isSchedulingBoundary(const MachineInstr &MI,
10861082 const MachineBasicBlock *MBB,
10871083 const MachineFunction &MF) const;
10881084
11241120 /// in SrcReg and SrcReg2 if having two register operands, and the value it
11251121 /// compares against in CmpValue. Return true if the comparison instruction
11261122 /// can be analyzed.
1127 virtual bool analyzeCompare(const MachineInstr *MI,
1128 unsigned &SrcReg, unsigned &SrcReg2,
1129 int &Mask, int &Value) const {
1123 virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1124 unsigned &SrcReg2, int &Mask, int &Value) const {
11301125 return false;
11311126 }
11321127
11331128 /// See if the comparison instruction can be converted
11341129 /// into something more efficient. E.g., on ARM most instructions can set the
11351130 /// flags register, obviating the need for a separate CMP.
1136 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr,
1137 unsigned SrcReg, unsigned SrcReg2,
1138 int Mask, int Value,
1131 virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1132 unsigned SrcReg2, int Mask, int Value,
11391133 const MachineRegisterInfo *MRI) const {
11401134 return false;
11411135 }
1142 virtual bool optimizeCondBranch(MachineInstr *MI) const { return false; }
1136 virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
11431137
11441138 /// Try to remove the load by folding it to a register operand at the use.
11451139 /// We fold the load instructions if and only if the
11481142 /// defined by the load we are trying to fold. DefMI returns the machine
11491143 /// instruction that defines FoldAsLoadDefReg, and the function returns
11501144 /// the machine instruction generated due to folding.
1151 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
1152 const MachineRegisterInfo *MRI,
1153 unsigned &FoldAsLoadDefReg,
1154 MachineInstr *&DefMI) const {
1145 virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
1146 const MachineRegisterInfo *MRI,
1147 unsigned &FoldAsLoadDefReg,
1148 MachineInstr *&DefMI) const {
11551149 return nullptr;
11561150 }
11571151
11611155 /// then the caller may assume that DefMI has been erased from its parent
11621156 /// block. The caller may assume that it will not be erased by this
11631157 /// function otherwise.
1164 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1158 virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
11651159 unsigned Reg, MachineRegisterInfo *MRI) const {
11661160 return false;
11671161 }
11711165 /// IssueWidth is the number of microops that can be dispatched each
11721166 /// cycle. An instruction with zero microops takes no dispatch resources.
11731167 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1174 const MachineInstr *MI) const;
1168 const MachineInstr &MI) const;
11751169
11761170 /// Return true for pseudo instructions that don't consume any
11771171 /// machine resources in their current form. These are common cases that the
11941188 /// by a target. Use computeOperandLatency to get the best estimate of
11951189 /// latency.
11961190 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1197 const MachineInstr *DefMI, unsigned DefIdx,
1198 const MachineInstr *UseMI,
1191 const MachineInstr &DefMI, unsigned DefIdx,
1192 const MachineInstr &UseMI,
11991193 unsigned UseIdx) const;
12001194
1201 /// Compute and return the latency of the given data
1202 /// dependent def and use when the operand indices are already known.
1195 /// Compute and return the latency of the given data dependent def and use
1196 /// when the operand indices are already known. UseMI may be \c nullptr for
1197 /// an unknown use.
1198 ///
1199 /// FindMin may be set to get the minimum vs. expected latency. Minimum
1200 /// latency is used for scheduling groups, while expected latency is for
1201 /// instruction cost and critical path.
1202 ///
1203 /// Depending on the subtarget's itinerary properties, this may or may not
1204 /// need to call getOperandLatency(). For most subtargets, we don't need
1205 /// DefIdx or UseIdx to compute min latency.
12031206 unsigned computeOperandLatency(const InstrItineraryData *ItinData,
1204 const MachineInstr *DefMI, unsigned DefIdx,
1205 const MachineInstr *UseMI, unsigned UseIdx)
1206 const;
1207 const MachineInstr &DefMI, unsigned DefIdx,
1208 const MachineInstr *UseMI,
1209 unsigned UseIdx) const;
12071210
12081211 /// Compute the instruction latency of a given instruction.
12091212 /// If the instruction has higher cost when predicated, it's returned via
12101213 /// PredCost.
12111214 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1212 const MachineInstr *MI,
1215 const MachineInstr &MI,
12131216 unsigned *PredCost = nullptr) const;
12141217
12151218 virtual unsigned getPredicationCost(const MachineInstr &MI) const;
12171220 virtual int getInstrLatency(const InstrItineraryData *ItinData,
12181221 SDNode *Node) const;
12191222
1220 /// Return the default expected latency for a def based on it's opcode.
1223 /// Return the default expected latency for a def based on its opcode.
12211224 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1222 const MachineInstr *DefMI) const;
1225 const MachineInstr &DefMI) const;
12231226
12241227 int computeDefOperandLatency(const InstrItineraryData *ItinData,
1225 const MachineInstr *DefMI) const;
1228 const MachineInstr &DefMI) const;
12261229
12271230 /// Return true if this opcode has high latency to its result.
12281231 virtual bool isHighLatencyDef(int opc) const { return false; }
12321235 /// it 'high'. This is used by optimization passes such as machine LICM to
12331236 /// determine whether it makes sense to hoist an instruction out even in a
12341237 /// high register pressure situation.
1235 virtual
1236 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1237 const MachineRegisterInfo *MRI,
1238 const MachineInstr *DefMI, unsigned DefIdx,
1239 const MachineInstr *UseMI, unsigned UseIdx) const {
1238 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1239 const MachineRegisterInfo *MRI,
1240 const MachineInstr &DefMI, unsigned DefIdx,
1241 const MachineInstr &UseMI,
1242 unsigned UseIdx) const {
12401243 return false;
12411244 }
12421245
12431246 /// Compute operand latency of a def of 'Reg'. Return true
12441247 /// if the target considered it 'low'.
1245 virtual
1246 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1247 const MachineInstr *DefMI, unsigned DefIdx) const;
1248 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1249 const MachineInstr &DefMI,
1250 unsigned DefIdx) const;
12481251
12491252 /// Perform target-specific instruction verification.
1250 virtual
1251 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const {
1253 virtual bool verifyInstruction(const MachineInstr &MI,
1254 StringRef &ErrInfo) const {
12521255 return true;
12531256 }
12541257
12721275 /// execution domain.
12731276 ///
12741277 virtual std::pair
1275 getExecutionDomain(const MachineInstr *MI) const {
1278 getExecutionDomain(const MachineInstr &MI) const {
12761279 return std::make_pair(0, 0);
12771280 }
12781281
12801283 ///
12811284 /// The bit (1 << Domain) must be set in the mask returned from
12821285 /// getExecutionDomain(MI).
1283 virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {}
1286 virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
12841287
12851288 /// Returns the preferred minimum clearance
12861289 /// before an instruction with an unwanted partial register update.
13221325 /// allows the target to insert a dependency breaking instruction.
13231326 ///
13241327 virtual unsigned
1325 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
1328 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
13261329 const TargetRegisterInfo *TRI) const {
13271330 // The default implementation returns 0 for no partial register dependency.
13281331 return 0;
13421345 /// This hook works similarly to getPartialRegUpdateClearance, except that it
13431346 /// does not take an operand index. Instead sets \p OpNum to the index of the
13441347 /// unused register.
1345 virtual unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
1348 virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
13461349 const TargetRegisterInfo *TRI) const {
13471350 // The default implementation returns 0 for no undef register dependency.
13481351 return 0;
13651368 /// An operand should be added to MI if an instruction was
13661369 /// inserted. This ties the instructions together in the post-ra scheduler.
13671370 ///
1368 virtual void
1369 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
1370 const TargetRegisterInfo *TRI) const {}
1371 virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1372 const TargetRegisterInfo *TRI) const {}
13711373
13721374 /// Create machine specific model for scheduling.
13731375 virtual DFAPacketizer *
13801382 // memory addresses. This function returns true if two MIs access different
13811383 // memory addresses and false otherwise.
13821384 virtual bool
1383 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
1385 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
13841386 AliasAnalysis *AA = nullptr) const {
1385 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1387 assert((MIa.mayLoad() || MIa.mayStore()) &&
13861388 "MIa must load from or modify a memory location");
1387 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1389 assert((MIb.mayLoad() || MIb.mayStore()) &&
13881390 "MIb must load from or modify a memory location");
13891391 return false;
13901392 }
635635 // We assume a single instruction only has a spill or reload, not
636636 // both.
637637 const MachineMemOperand *MMO;
638 if (TII->isLoadFromStackSlotPostFE(&MI, FI)) {
638 if (TII->isLoadFromStackSlotPostFE(MI, FI)) {
639639 if (FrameInfo->isSpillSlotObjectIndex(FI)) {
640640 MMO = *MI.memoperands_begin();
641641 CommentOS << MMO->getSize() << "-byte Reload\n";
642642 }
643 } else if (TII->hasLoadFromStackSlot(&MI, MMO, FI)) {
643 } else if (TII->hasLoadFromStackSlot(MI, MMO, FI)) {
644644 if (FrameInfo->isSpillSlotObjectIndex(FI))
645645 CommentOS << MMO->getSize() << "-byte Folded Reload\n";
646 } else if (TII->isStoreToStackSlotPostFE(&MI, FI)) {
646 } else if (TII->isStoreToStackSlotPostFE(MI, FI)) {
647647 if (FrameInfo->isSpillSlotObjectIndex(FI)) {
648648 MMO = *MI.memoperands_begin();
649649 CommentOS << MMO->getSize() << "-byte Spill\n";
650650 }
651 } else if (TII->hasStoreToStackSlot(&MI, MMO, FI)) {
651 } else if (TII->hasStoreToStackSlot(MI, MMO, FI)) {
652652 if (FrameInfo->isSpillSlotObjectIndex(FI))
653653 CommentOS << MMO->getSize() << "-byte Folded Spill\n";
654654 }
120120 }
121121 }
122122
123 if (!TII.isTriviallyReMaterializable(MI, LIS.getAliasAnalysis()))
123 if (!TII.isTriviallyReMaterializable(*MI, LIS.getAliasAnalysis()))
124124 return false;
125125 }
126126 return true;
319319
320320 // Collapse all the instructions.
321321 while (!dv->Instrs.empty())
322 TII->setExecutionDomain(dv->Instrs.pop_back_val(), domain);
322 TII->setExecutionDomain(*dv->Instrs.pop_back_val(), domain);
323323 dv->setSingleDomain(domain);
324324
325325 // If there are multiple users, give them new, unique DomainValues.
459459 return;
460460
461461 // Update instructions with explicit execution domains.
462 std::pair DomP = TII->getExecutionDomain(MI);
462 std::pair DomP = TII->getExecutionDomain(*MI);
463463 if (DomP.first) {
464464 if (DomP.second)
465465 visitSoftInstr(MI, DomP.second);
507507
508508 // Break dependence on undef uses. Do this before updating LiveRegs below.
509509 unsigned OpNum;
510 unsigned Pref = TII->getUndefRegClearance(MI, OpNum, TRI);
510 unsigned Pref = TII->getUndefRegClearance(*MI, OpNum, TRI);
511511 if (Pref) {
512512 if (shouldBreakDependence(MI, OpNum, Pref))
513513 UndefReads.push_back(std::make_pair(MI, OpNum));
530530
531531 // Check clearance before partial register updates.
532532 // Call breakDependence before setting LiveRegs[rx].Def.
533 unsigned Pref = TII->getPartialRegUpdateClearance(MI, i, TRI);
533 unsigned Pref = TII->getPartialRegUpdateClearance(*MI, i, TRI);
534534 if (Pref && shouldBreakDependence(MI, i, Pref))
535 TII->breakPartialRegDependency(MI, i, TRI);
535 TII->breakPartialRegDependency(*MI, i, TRI);
536536
537537 // How many instructions since rx was last written?
538538 LiveRegs[rx].Def = CurInstr;
570570
571571 if (UndefMI == &I) {
572572 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg()))
573 TII->breakPartialRegDependency(UndefMI, OpIdx, TRI);
573 TII->breakPartialRegDependency(*UndefMI, OpIdx, TRI);
574574
575575 UndefReads.pop_back();
576576 if (UndefReads.empty())
644644 // If the collapsed operands force a single domain, propagate the collapse.
645645 if (isPowerOf2_32(available)) {
646646 unsigned domain = countTrailingZeros(available);
647 TII->setExecutionDomain(mi, domain);
647 TII->setExecutionDomain(*mi, domain);
648648 visitHardInstr(mi, domain);
649649 return;
650650 }
191191 mbbi != mbbe; ++mbbi) {
192192 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
193193 mi != me;) {
194 MachineInstr *MI = mi;
194 MachineInstr &MI = *mi;
195195 // Advance iterator here because MI may be erased.
196196 ++mi;
197197
198198 // Only expand pseudos.
199 if (!MI->isPseudo())
199 if (!MI.isPseudo())
200200 continue;
201201
202202 // Give targets a chance to expand even standard pseudos.
206206 }
207207
208208 // Expand standard pseudos.
209 switch (MI->getOpcode()) {
209 switch (MI.getOpcode()) {
210210 case TargetOpcode::SUBREG_TO_REG:
211 MadeChange |= LowerSubregToReg(MI);
211 MadeChange |= LowerSubregToReg(&MI);
212212 break;
213213 case TargetOpcode::COPY:
214 MadeChange |= LowerCopy(MI);
214 MadeChange |= LowerCopy(&MI);
215215 break;
216216 case TargetOpcode::DBG_VALUE:
217217 continue;
420420
421421 for (auto MII = NotNullSucc->begin(), MIE = NotNullSucc->end(); MII != MIE;
422422 ++MII) {
423 MachineInstr *MI = &*MII;
423 MachineInstr &MI = *MII;
424424 unsigned BaseReg;
425425 int64_t Offset;
426426 MachineInstr *Dependency = nullptr;
427427 if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI))
428 if (MI->mayLoad() && !MI->isPredicable() && BaseReg == PointerReg &&
429 Offset < PageSize && MI->getDesc().getNumDefs() <= 1 &&
430 HD.isSafeToHoist(MI, Dependency)) {
428 if (MI.mayLoad() && !MI.isPredicable() && BaseReg == PointerReg &&
429 Offset < PageSize && MI.getDesc().getNumDefs() <= 1 &&
430 HD.isSafeToHoist(&MI, Dependency)) {
431431
432432 auto DependencyOperandIsOk = [&](MachineOperand &MO) {
433433 assert(!(MO.isReg() && MO.isUse()) &&
462462 all_of(Dependency->operands(), DependencyOperandIsOk);
463463
464464 if (DependencyOperandsAreOk) {
465 NullCheckList.emplace_back(MI, MBP.ConditionDef, &MBB, NotNullSucc,
465 NullCheckList.emplace_back(&MI, MBP.ConditionDef, &MBB, NotNullSucc,
466466 NullSucc, Dependency);
467467 return true;
468468 }
469469 }
470470
471 HD.rememberInstruction(MI);
471 HD.rememberInstruction(&MI);
472472 if (HD.isClobbered())
473473 return false;
474474 }
235235
236236 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
237237 /// otherwise return 0.
238 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
239 if (!MI->isFullCopy())
238 static unsigned isFullCopyOf(const MachineInstr &MI, unsigned Reg) {
239 if (!MI.isFullCopy())
240240 return 0;
241 if (MI->getOperand(0).getReg() == Reg)
242 return MI->getOperand(1).getReg();
243 if (MI->getOperand(1).getReg() == Reg)
244 return MI->getOperand(0).getReg();
241 if (MI.getOperand(0).getReg() == Reg)
242 return MI.getOperand(1).getReg();
243 if (MI.getOperand(1).getReg() == Reg)
244 return MI.getOperand(0).getReg();
245245 return 0;
246246 }
247247
267267 for (MachineRegisterInfo::reg_instr_nodbg_iterator
268268 RI = MRI.reg_instr_nodbg_begin(SnipLI.reg),
269269 E = MRI.reg_instr_nodbg_end(); RI != E; ) {
270 MachineInstr *MI = &*(RI++);
270 MachineInstr &MI = *RI++;
271271
272272 // Allow copies to/from Reg.
273273 if (isFullCopyOf(MI, Reg))
283283 continue;
284284
285285 // Allow a single additional instruction.
286 if (UseMI && MI != UseMI)
286 if (UseMI && &MI != UseMI)
287287 return false;
288 UseMI = MI;
288 UseMI = &MI;
289289 }
290290 return true;
291291 }
306306
307307 for (MachineRegisterInfo::reg_instr_iterator
308308 RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end(); RI != E; ) {
309 MachineInstr *MI = &*(RI++);
309 MachineInstr &MI = *RI++;
310310 unsigned SnipReg = isFullCopyOf(MI, Reg);
311311 if (!isSibling(SnipReg))
312312 continue;
313313 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
314314 if (!isSnippet(SnipLI))
315315 continue;
316 SnippetCopies.insert(MI);
316 SnippetCopies.insert(&MI);
317317 if (isRegToSpill(SnipReg))
318318 continue;
319319 RegsToSpill.push_back(SnipReg);
425425 for (MachineRegisterInfo::use_instr_nodbg_iterator
426426 UI = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end();
427427 UI != E; ) {
428 MachineInstr *MI = &*(UI++);
429 if (!MI->isCopy() && !MI->mayStore())
428 MachineInstr &MI = *UI++;
429 if (!MI.isCopy() && !MI.mayStore())
430430 continue;
431 SlotIndex Idx = LIS.getInstructionIndex(*MI);
431 SlotIndex Idx = LIS.getInstructionIndex(MI);
432432 if (LI->getVNInfoAt(Idx) != VNI)
433433 continue;
434434
447447 // Erase spills.
448448 int FI;
449449 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
450 DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << *MI);
450 DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << MI);
451451 // eliminateDeadDefs won't normally remove stores, so switch opcode.
452 MI->setDesc(TII.get(TargetOpcode::KILL));
453 DeadDefs.push_back(MI);
452 MI.setDesc(TII.get(TargetOpcode::KILL));
453 DeadDefs.push_back(&MI);
454454 ++NumSpillsRemoved;
455 if (HSpiller.rmFromMergeableSpills(MI, StackSlot))
455 if (HSpiller.rmFromMergeableSpills(&MI, StackSlot))
456456 --NumSpills;
457457 }
458458 }
655655 /// If MI is a load or store of StackSlot, it can be removed.
656656 bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
657657 int FI = 0;
658 unsigned InstrReg = TII.isLoadFromStackSlot(MI, FI);
658 unsigned InstrReg = TII.isLoadFromStackSlot(*MI, FI);
659659 bool IsLoad = InstrReg;
660660 if (!IsLoad)
661 InstrReg = TII.isStoreToStackSlot(MI, FI);
661 InstrReg = TII.isStoreToStackSlot(*MI, FI);
662662
663663 // We have a stack access. Is it the right register and slot?
664664 if (InstrReg != Reg || FI != StackSlot)
764764 MachineInstrSpan MIS(MI);
765765
766766 MachineInstr *FoldMI =
767 LoadMI ? TII.foldMemoryOperand(MI, FoldOps, LoadMI, &LIS)
768 : TII.foldMemoryOperand(MI, FoldOps, StackSlot, &LIS);
767 LoadMI ? TII.foldMemoryOperand(*MI, FoldOps, *LoadMI, &LIS)
768 : TII.foldMemoryOperand(*MI, FoldOps, StackSlot, &LIS);
769769 if (!FoldMI)
770770 return false;
771771
792792 }
793793
794794 int FI;
795 if (TII.isStoreToStackSlot(MI, FI) && HSpiller.rmFromMergeableSpills(MI, FI))
795 if (TII.isStoreToStackSlot(*MI, FI) && HSpiller.rmFromMergeableSpills(MI, FI))
796796 --NumSpills;
797797 LIS.ReplaceMachineInstrInMaps(*MI, *FoldMI);
798798 MI->eraseFromParent();
912912 Idx = VNI->def;
913913
914914 // Check for a sibling copy.
915 unsigned SibReg = isFullCopyOf(MI, Reg);
915 unsigned SibReg = isFullCopyOf(*MI, Reg);
916916 if (SibReg && isSibling(SibReg)) {
917917 // This may actually be a copy between snippets.
918918 if (isRegToSpill(SibReg)) {
5252 AliasAnalysis *aa) {
5353 assert(DefMI && "Missing instruction");
5454 ScannedRemattable = true;
55 if (!TII.isTriviallyReMaterializable(DefMI, aa))
55 if (!TII.isTriviallyReMaterializable(*DefMI, aa))
5656 return false;
5757 Remattable.insert(VNI);
5858 return true;
129129 DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
130130
131131 // If only cheap remats were requested, bail out early.
132 if (cheapAsAMove && !TII.isAsCheapAsAMove(RM.OrigMI))
132 if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI))
133133 return false;
134134
135135 // Verify that all used registers are available with the same values.
146146 const TargetRegisterInfo &tri,
147147 bool Late) {
148148 assert(RM.OrigMI && "Invalid remat");
149 TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
149 TII.reMaterialize(MBB, MI, DestReg, 0, *RM.OrigMI, tri);
150150 // DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg
151151 // to false anyway in case the isDead flag of RM.OrigMI's dest register
152152 // is true.
204204 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
205205 return false;
206206
207 MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI, &LIS);
207 MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS);
208208 if (!FoldMI)
209209 return false;
210210 DEBUG(dbgs() << " folded: " << *FoldMI);
388388 // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
389389 // an immediate predecessor. We don't want to increase register pressure and
390390 // end up causing other computation to be spilled.
391 if (TII->isAsCheapAsAMove(MI)) {
391 if (TII->isAsCheapAsAMove(*MI)) {
392392 MachineBasicBlock *CSBB = CSMI->getParent();
393393 MachineBasicBlock *BB = MI->getParent();
394394 if (CSBB != BB && !CSBB->isSuccessor(BB))
477477 // Commute commutable instructions.
478478 bool Commuted = false;
479479 if (!FoundCSE && MI->isCommutable()) {
480 MachineInstr *NewMI = TII->commuteInstruction(MI);
481 if (NewMI) {
480 if (MachineInstr *NewMI = TII->commuteInstruction(*MI)) {
482481 Commuted = true;
483482 FoundCSE = VNT.count(NewMI);
484483 if (NewMI != MI) {
487486 Changed = true;
488487 } else if (!FoundCSE)
489488 // MI was changed but it didn't help, commute it back!
490 (void)TII->commuteInstruction(MI);
489 (void)TII->commuteInstruction(*MI);
491490 }
492491 }
493492
427427 if (Def && !RuledOut) {
428428 int FI = INT_MIN;
429429 if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
430 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
430 (TII->isLoadFromStackSlot(*MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
431431 Candidates.push_back(CandidateInfo(MI, Def, FI));
432432 }
433433 }
981981 if (MOReg != Reg)
982982 continue;
983983
984 if (TII->hasHighOperandLatency(SchedModel, MRI, &MI, DefIdx, &UseMI, i))
984 if (TII->hasHighOperandLatency(SchedModel, MRI, MI, DefIdx, UseMI, i))
985985 return true;
986986 }
987987
995995 /// Return true if the instruction is marked "cheap" or the operand latency
996996 /// between its def and a use is one or less.
997997 bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
998 if (TII->isAsCheapAsAMove(&MI) || MI.isCopyLike())
998 if (TII->isAsCheapAsAMove(MI) || MI.isCopyLike())
999999 return true;
10001000
10011001 bool isCheap = false;
10091009 if (TargetRegisterInfo::isPhysicalRegister(Reg))
10101010 continue;
10111011
1012 if (!TII->hasLowDefLatency(SchedModel, &MI, i))
1012 if (!TII->hasLowDefLatency(SchedModel, MI, i))
10131013 return false;
10141014 isCheap = true;
10151015 }
10851085
10861086 // Rematerializable instructions should always be hoisted since the register
10871087 // allocator can just pull them down again when needed.
1088 if (TII->isTriviallyReMaterializable(&MI, AA))
1088 if (TII->isTriviallyReMaterializable(MI, AA))
10891089 return true;
10901090
10911091 // FIXME: If there are long latency loop-invariant instructions inside the
11381138
11391139 // High register pressure situation, only hoist if the instruction is going
11401140 // to be remat'ed.
1141 if (!TII->isTriviallyReMaterializable(&MI, AA) &&
1142 !MI.isInvariantLoad(AA)) {
1141 if (!TII->isTriviallyReMaterializable(MI, AA) && !MI.isInvariantLoad(AA)) {
11431142 DEBUG(dbgs() << "Can't remat / high reg-pressure: " << MI);
11441143 return false;
11451144 }
11761175 unsigned Reg = MRI->createVirtualRegister(RC);
11771176
11781177 SmallVector NewMIs;
1179 bool Success =
1180 TII->unfoldMemoryOperand(MF, MI, Reg,
1181 /*UnfoldLoad=*/true, /*UnfoldStore=*/false,
1182 NewMIs);
1178 bool Success = TII->unfoldMemoryOperand(MF, *MI, Reg,
1179 /*UnfoldLoad=*/true,
1180 /*UnfoldStore=*/false, NewMIs);
11831181 (void)Success;
11841182 assert(Success &&
11851183 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
12201218 MachineLICM::LookForDuplicate(const MachineInstr *MI,
12211219 std::vector &PrevMIs) {
12221220 for (const MachineInstr *PrevMI : PrevMIs)
1223 if (TII->produceSameValue(MI, PrevMI, (PreRegAlloc ? MRI : nullptr)))
1221 if (TII->produceSameValue(*MI, *PrevMI, (PreRegAlloc ? MRI : nullptr)))
12241222 return PrevMI;
12251223
12261224 return nullptr;
405405 MachineBasicBlock *MBB,
406406 MachineFunction *MF,
407407 const TargetInstrInfo *TII) {
408 return MI->isCall() || TII->isSchedulingBoundary(MI, MBB, *MF);
408 return MI->isCall() || TII->isSchedulingBoundary(*MI, MBB, *MF);
409409 }
410410
411411 /// Main driver for both MachineScheduler and PostMachineScheduler.
14011401 SUnit *SU = MemOps[Idx];
14021402 unsigned BaseReg;
14031403 int64_t Offset;
1404 if (TII->getMemOpBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
1404 if (TII->getMemOpBaseRegImmOfs(*SU->getInstr(), BaseReg, Offset, TRI))
14051405 MemOpRecords.push_back(MemOpInfo(SU, BaseReg, Offset));
14061406 }
14071407 if (MemOpRecords.size() < 2)
14171417
14181418 SUnit *SUa = MemOpRecords[Idx].SU;
14191419 SUnit *SUb = MemOpRecords[Idx+1].SU;
1420 if (TII->shouldClusterMemOps(SUa->getInstr(), SUb->getInstr(), ClusterLength)
1421 && DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
1420 if (TII->shouldClusterMemOps(*SUa->getInstr(), *SUb->getInstr(),
1421 ClusterLength) &&
1422 DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
14221423 DEBUG(dbgs() << "Cluster ld/st SU(" << SUa->NodeNum << ") - SU("
14231424 << SUb->NodeNum << ")\n");
14241425 // Copy successor edges from SUa to SUb. Interleaving computation
15281529 if (!HasDataDep(TRI, *Branch, *Pred))
15291530 continue;
15301531
1531 if (!TII.shouldScheduleAdjacent(Pred, Branch))
1532 if (!TII.shouldScheduleAdjacent(*Pred, *Branch))
15321533 continue;
15331534
15341535 // Create a single weak edge from SU to ExitSU. The only effect is to cause
365365 if (!CEBCandidates.insert(std::make_pair(From, To)).second)
366366 return true;
367367
368 if (!MI->isCopy() && !TII->isAsCheapAsAMove(MI))
368 if (!MI->isCopy() && !TII->isAsCheapAsAMove(*MI))
369369 return true;
370370
371371 // MI is cheap, we probably don't want to break the critical edge for it.
699699
700700 unsigned BaseReg;
701701 int64_t Offset;
702 if (!TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI))
702 if (!TII->getMemOpBaseRegImmOfs(*MI, BaseReg, Offset, TRI))
703703 return false;
704704
705705 if (!(MI->mayLoad() && !MI->isPredicable()))
879879 }
880880
881881 StringRef ErrorInfo;
882 if (!TII->verifyInstruction(MI, ErrorInfo))
882 if (!TII->verifyInstruction(*MI, ErrorInfo))
883883 report(ErrorInfo.data(), MI);
884884 }
885885
563563 // physical register, we can try to optimize it.
564564 unsigned SrcReg, SrcReg2;
565565 int CmpMask, CmpValue;
566 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
566 if (!TII->analyzeCompare(*MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
567567 TargetRegisterInfo::isPhysicalRegister(SrcReg) ||
568568 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
569569 return false;
570570
571571 // Attempt to optimize the comparison instruction.
572 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
572 if (TII->optimizeCompareInstr(*MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
573573 ++NumCmps;
574574 return true;
575575 }
584584 unsigned FalseOp = 0;
585585 bool Optimizable = false;
586586 SmallVector Cond;
587 if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable))
587 if (TII->analyzeSelect(*MI, Cond, TrueOp, FalseOp, Optimizable))
588588 return false;
589589 if (!Optimizable)
590590 return false;
591 if (!TII->optimizeSelect(MI, LocalMIs))
591 if (!TII->optimizeSelect(*MI, LocalMIs))
592592 return false;
593593 MI->eraseFromParent();
594594 ++NumSelects;
598598 /// \brief Check if a simpler conditional branch can be
599599 // generated
600600 bool PeepholeOptimizer::optimizeCondBranch(MachineInstr *MI) {
601 return TII->optimizeCondBranch(MI);
601 return TII->optimizeCondBranch(*MI);
602602 }
603603
604604 /// \brief Try to find the next source that share the same register file
13501350 continue;
13511351 DenseMap::iterator II = ImmDefMIs.find(Reg);
13521352 assert(II != ImmDefMIs.end() && "couldn't find immediate definition");
1353 if (TII->FoldImmediate(MI, II->second, Reg, MRI)) {
1353 if (TII->FoldImmediate(*MI, *II->second, Reg, MRI)) {
13541354 ++NumImmFold;
13551355 return true;
13561356 }
16351635 // we need it for markUsesInDebugValueAsUndef().
16361636 unsigned FoldedReg = FoldAsLoadDefReg;
16371637 MachineInstr *DefMI = nullptr;
1638 MachineInstr *FoldMI = TII->optimizeLoadInstr(MI, MRI,
1639 FoldAsLoadDefReg,
1640 DefMI);
1641 if (FoldMI) {
1638 if (MachineInstr *FoldMI =
1639 TII->optimizeLoadInstr(*MI, MRI, FoldAsLoadDefReg, DefMI)) {
16421640 // Update LocalMIs since we replaced MI with FoldMI and deleted
16431641 // DefMI.
16441642 DEBUG(dbgs() << "Replacing: " << *MI);
339339 // Calls are not scheduling boundaries before register allocation, but
340340 // post-ra we don't gain anything by scheduling across calls since we
341341 // don't need to worry about register pressure.
342 if (MI->isCall() || TII->isSchedulingBoundary(MI, &MBB, Fn)) {
342 if (MI->isCall() || TII->isSchedulingBoundary(*MI, &MBB, Fn)) {
343343 Scheduler.enterRegion(&MBB, I, Current, CurrentCount - Count);
344344 Scheduler.setEndIndex(CurrentCount);
345345 Scheduler.schedule();
10551055 if (I->getOpcode() == FrameSetupOpcode ||
10561056 I->getOpcode() == FrameDestroyOpcode) {
10571057 InsideCallSequence = (I->getOpcode() == FrameSetupOpcode);
1058 SPAdj += TII.getSPAdjust(I);
1058 SPAdj += TII.getSPAdjust(*I);
10591059
10601060 I = TFI->eliminateCallFramePseudoInstr(Fn, *BB, I);
10611061 continue;
11341134 // if I itself referred to a frame index, we shouldn't count its own
11351135 // adjustment.
11361136 if (MI && InsideCallSequence)
1137 SPAdj += TII.getSPAdjust(MI);
1137 SPAdj += TII.getSPAdjust(*MI);
11381138
11391139 if (DoIncr && I != BB->end()) ++I;
11401140
683683 // operands then all possible variants (i.e. op#1<->op#2, op#1<->op#3,
684684 // op#2<->op#3) of commute transformation should be considered/tried here.
685685 unsigned NewDstIdx = TargetInstrInfo::CommuteAnyOperandIndex;
686 if (!TII->findCommutedOpIndices(DefMI, UseOpIdx, NewDstIdx))
686 if (!TII->findCommutedOpIndices(*DefMI, UseOpIdx, NewDstIdx))
687687 return false;
688688
689689 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
717717 // transformation. Start by commuting the instruction.
718718 MachineBasicBlock *MBB = DefMI->getParent();
719719 MachineInstr *NewMI =
720 TII->commuteInstruction(DefMI, false, UseOpIdx, NewDstIdx);
720 TII->commuteInstruction(*DefMI, false, UseOpIdx, NewDstIdx);
721721 if (!NewMI)
722722 return false;
723723 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
900900 IsDefCopy = true;
901901 return false;
902902 }
903 if (!TII->isAsCheapAsAMove(DefMI))
904 return false;
905 if (!TII->isTriviallyReMaterializable(DefMI, AA))
903 if (!TII->isAsCheapAsAMove(*DefMI))
904 return false;
905 if (!TII->isTriviallyReMaterializable(*DefMI, AA))
906906 return false;
907907 if (!definesFullReg(*DefMI, SrcReg))
908908 return false;
952952 MachineBasicBlock *MBB = CopyMI->getParent();
953953 MachineBasicBlock::iterator MII =
954954 std::next(MachineBasicBlock::iterator(CopyMI));
955 TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, DefMI, *TRI);
955 TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, *DefMI, *TRI);
956956 MachineInstr *NewMI = std::prev(MII);
957957 NewMI->setDebugLoc(DL);
958958
568568 "Dependency checked between two loads");
569569
570570 // Let the target decide if memory accesses cannot possibly overlap.
571 if (TII->areMemAccessesTriviallyDisjoint(MIa, MIb, AA))
571 if (TII->areMemAccessesTriviallyDisjoint(*MIa, *MIb, AA))
572572 return false;
573573
574574 // To this point analysis is generic. From here on we do need AA.
385385 break;
386386
387387 int FirstSS, SecondSS;
388 if (TII->isStackSlotCopy(I, FirstSS, SecondSS) &&
389 FirstSS == SecondSS &&
388 if (TII->isStackSlotCopy(*I, FirstSS, SecondSS) && FirstSS == SecondSS &&
390389 FirstSS != -1) {
391390 ++NumDead;
392391 changed = true;
399398
400399 unsigned LoadReg = 0;
401400 unsigned StoreReg = 0;
402 if (!(LoadReg = TII->isLoadFromStackSlot(I, FirstSS))) continue;
403 if (!(StoreReg = TII->isStoreToStackSlot(NextMI, SecondSS))) continue;
401 if (!(LoadReg = TII->isLoadFromStackSlot(*I, FirstSS)))
402 continue;
403 if (!(StoreReg = TII->isStoreToStackSlot(*NextMI, SecondSS)))
404 continue;
404405 if (FirstSS != SecondSS || LoadReg != StoreReg || FirstSS == -1) continue;
405406
406407 ++NumDead;
340340 MachineFunction &MF,
341341 DenseMap &LocalVRMap,
342342 const DenseSet &UsedByPhi) {
343 MachineInstr *NewMI = TII->duplicate(MI, MF);
343 MachineInstr *NewMI = TII->duplicate(*MI, MF);
344344 if (PreRegAlloc) {
345345 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
346346 MachineOperand &MO = NewMI->getOperand(i);
118118 MBB->addSuccessor(NewDest);
119119 }
120120
121 MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr *MI,
122 bool NewMI,
123 unsigned Idx1,
121 MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
122 bool NewMI, unsigned Idx1,
124123 unsigned Idx2) const {
125 const MCInstrDesc &MCID = MI->getDesc();
124 const MCInstrDesc &MCID = MI.getDesc();
126125 bool HasDef = MCID.getNumDefs();
127 if (HasDef && !MI->getOperand(0).isReg())
126 if (HasDef && !MI.getOperand(0).isReg())
128127 // No idea how to commute this instruction. Target should implement its own.
129128 return nullptr;
130129
133132 assert(findCommutedOpIndices(MI, CommutableOpIdx1, CommutableOpIdx2) &&
134133 CommutableOpIdx1 == Idx1 && CommutableOpIdx2 == Idx2 &&
135134 "TargetInstrInfo::CommuteInstructionImpl(): not commutable operands.");
136 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
135 assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() &&
137136 "This only knows how to commute register operands so far");
138137
139 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
140 unsigned Reg1 = MI->getOperand(Idx1).getReg();
141 unsigned Reg2 = MI->getOperand(Idx2).getReg();
142 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
143 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
144 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
145 bool Reg1IsKill = MI->getOperand(Idx1).isKill();
146 bool Reg2IsKill = MI->getOperand(Idx2).isKill();
147 bool Reg1IsUndef = MI->getOperand(Idx1).isUndef();
148 bool Reg2IsUndef = MI->getOperand(Idx2).isUndef();
149 bool Reg1IsInternal = MI->getOperand(Idx1).isInternalRead();
150 bool Reg2IsInternal = MI->getOperand(Idx2).isInternalRead();
138 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
139 unsigned Reg1 = MI.getOperand(Idx1).getReg();
140 unsigned Reg2 = MI.getOperand(Idx2).getReg();
141 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;
142 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg();
143 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg();
144 bool Reg1IsKill = MI.getOperand(Idx1).isKill();
145 bool Reg2IsKill = MI.getOperand(Idx2).isKill();
146 bool Reg1IsUndef = MI.getOperand(Idx1).isUndef();
147 bool Reg2IsUndef = MI.getOperand(Idx2).isUndef();
148 bool Reg1IsInternal = MI.getOperand(Idx1).isInternalRead();
149 bool Reg2IsInternal = MI.getOperand(Idx2).isInternalRead();
151150 // If destination is tied to either of the commuted source register, then
152151 // it must be updated.
153152 if (HasDef && Reg0 == Reg1 &&
154 MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
153 MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
155154 Reg2IsKill = false;
156155 Reg0 = Reg2;
157156 SubReg0 = SubReg2;
158157 } else if (HasDef && Reg0 == Reg2 &&
159 MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
158 MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
160159 Reg1IsKill = false;
161160 Reg0 = Reg1;
162161 SubReg0 = SubReg1;
163162 }
164163
164 MachineInstr *CommutedMI = nullptr;
165165 if (NewMI) {
166166 // Create a new instruction.
167 MachineFunction &MF = *MI->getParent()->getParent();
168 MI = MF.CloneMachineInstr(MI);
167 MachineFunction &MF = *MI.getParent()->getParent();
168 CommutedMI = MF.CloneMachineInstr(&MI);
169 } else {
170 CommutedMI = &MI;
169171 }
170172
171173 if (HasDef) {
172 MI->getOperand(0).setReg(Reg0);
173 MI->getOperand(0).setSubReg(SubReg0);
174 }
175 MI->getOperand(Idx2).setReg(Reg1);
176 MI->getOperand(Idx1).setReg(Reg2);
177 MI->getOperand(Idx2).setSubReg(SubReg1);
178 MI->getOperand(Idx1).setSubReg(SubReg2);
179 MI->getOperand(Idx2).setIsKill(Reg1IsKill);
180 MI->getOperand(Idx1).setIsKill(Reg2IsKill);
181 MI->getOperand(Idx2).setIsUndef(Reg1IsUndef);
182 MI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
183 MI->getOperand(Idx2).setIsInternalRead(Reg1IsInternal);
184 MI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal);
185 return MI;
186 }
187
188 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI,
189 bool NewMI,
174 CommutedMI->getOperand(0).setReg(Reg0);
175 CommutedMI->getOperand(0).setSubReg(SubReg0);
176 }
177 CommutedMI->getOperand(Idx2).setReg(Reg1);
178 CommutedMI->getOperand(Idx1).setReg(Reg2);
179 CommutedMI->getOperand(Idx2).setSubReg(SubReg1);
180 CommutedMI->getOperand(Idx1).setSubReg(SubReg2);
181 CommutedMI->getOperand(Idx2).setIsKill(Reg1IsKill);
182 CommutedMI->getOperand(Idx1).setIsKill(Reg2IsKill);
183 CommutedMI->getOperand(Idx2).setIsUndef(Reg1IsUndef);
184 CommutedMI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
185 CommutedMI->getOperand(Idx2).setIsInternalRead(Reg1IsInternal);
186 CommutedMI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal);
187 return CommutedMI;
188 }
189
190 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr &MI, bool NewMI,
190191 unsigned OpIdx1,
191192 unsigned OpIdx2) const {
192193 // If OpIdx1 or OpIdx2 is not specified, then this method is free to choose
194195 // called below.
195196 if ((OpIdx1 == CommuteAnyOperandIndex || OpIdx2 == CommuteAnyOperandIndex) &&
196197 !findCommutedOpIndices(MI, OpIdx1, OpIdx2)) {
197 assert(MI->isCommutable() &&
198 assert(MI.isCommutable() &&
198199 "Precondition violation: MI must be commutable.");
199200 return nullptr;
200201 }
232233 return true;
233234 }
234235
235 bool TargetInstrInfo::findCommutedOpIndices(MachineInstr *MI,
236 bool TargetInstrInfo::findCommutedOpIndices(MachineInstr &MI,
236237 unsigned &SrcOpIdx1,
237238 unsigned &SrcOpIdx2) const {
238 assert(!MI->isBundle() &&
239 assert(!MI.isBundle() &&
239240 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
240241
241 const MCInstrDesc &MCID = MI->getDesc();
242 const MCInstrDesc &MCID = MI.getDesc();
242243 if (!MCID.isCommutable())
243244 return false;
244245
250251 CommutableOpIdx1, CommutableOpIdx2))
251252 return false;
252253
253 if (!MI->getOperand(SrcOpIdx1).isReg() ||
254 !MI->getOperand(SrcOpIdx2).isReg())
254 if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
255255 // No idea.
256256 return false;
257257 return true;
298298 return MadeChange;
299299 }
300300
301 bool TargetInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
301 bool TargetInstrInfo::hasLoadFromStackSlot(const MachineInstr &MI,
302302 const MachineMemOperand *&MMO,
303303 int &FrameIndex) const {
304 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
305 oe = MI->memoperands_end();
306 o != oe;
307 ++o) {
304 for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
305 oe = MI.memoperands_end();
306 o != oe; ++o) {
308307 if ((*o)->isLoad()) {
309308 if (const FixedStackPseudoSourceValue *Value =
310309 dyn_cast_or_null(
318317 return false;
319318 }
320319
321 bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
320 bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr &MI,
322321 const MachineMemOperand *&MMO,
323322 int &FrameIndex) const {
324 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
325 oe = MI->memoperands_end();
326 o != oe;
327 ++o) {
323 for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
324 oe = MI.memoperands_end();
325 o != oe; ++o) {
328326 if ((*o)->isStore()) {
329327 if (const FixedStackPseudoSourceValue *Value =
330328 dyn_cast_or_null(
371369
372370 void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
373371 MachineBasicBlock::iterator I,
374 unsigned DestReg,
375 unsigned SubIdx,
376 const MachineInstr *Orig,
372 unsigned DestReg, unsigned SubIdx,
373 const MachineInstr &Orig,
377374 const TargetRegisterInfo &TRI) const {
378 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
375 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
379376 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
380377 MBB.insert(I, MI);
381378 }
382379
383 bool
384 TargetInstrInfo::produceSameValue(const MachineInstr *MI0,
385 const MachineInstr *MI1,
386 const MachineRegisterInfo *MRI) const {
387 return MI0->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs);
388 }
389
390 MachineInstr *TargetInstrInfo::duplicate(MachineInstr *Orig,
380 bool TargetInstrInfo::produceSameValue(const MachineInstr &MI0,
381 const MachineInstr &MI1,
382 const MachineRegisterInfo *MRI) const {
383 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
384 }
385
386 MachineInstr *TargetInstrInfo::duplicate(MachineInstr &Orig,
391387 MachineFunction &MF) const {
392 assert(!Orig->isNotDuplicable() &&
393 "Instruction cannot be duplicated");
394 return MF.CloneMachineInstr(Orig);
388 assert(!Orig.isNotDuplicable() && "Instruction cannot be duplicated");
389 return MF.CloneMachineInstr(&Orig);
395390 }
396391
397392 // If the COPY instruction in MI can be folded to a stack operation, return
398393 // the register class to use.
399 static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI,
394 static const TargetRegisterClass *canFoldCopy(const MachineInstr &MI,
400395 unsigned FoldIdx) {
401 assert(MI->isCopy() && "MI must be a COPY instruction");
402 if (MI->getNumOperands() != 2)
396 assert(MI.isCopy() && "MI must be a COPY instruction");
397 if (MI.getNumOperands() != 2)
403398 return nullptr;
404399 assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
405400
406 const MachineOperand &FoldOp = MI->getOperand(FoldIdx);
407 const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx);
401 const MachineOperand &FoldOp = MI.getOperand(FoldIdx);
402 const MachineOperand &LiveOp = MI.getOperand(1 - FoldIdx);
408403
409404 if (FoldOp.getSubReg() || LiveOp.getSubReg())
410405 return nullptr;
415410 assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
416411 "Cannot fold physregs");
417412
418 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
413 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
419414 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
420415
421416 if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
432427 llvm_unreachable("Not a MachO target");
433428 }
434429
435 static MachineInstr *foldPatchpoint(MachineFunction &MF, MachineInstr *MI,
430 static MachineInstr *foldPatchpoint(MachineFunction &MF, MachineInstr &MI,
436431 ArrayRef Ops, int FrameIndex,
437432 const TargetInstrInfo &TII) {
438433 unsigned StartIdx = 0;
439 switch (MI->getOpcode()) {
434 switch (MI.getOpcode()) {
440435 case TargetOpcode::STACKMAP:
441436 StartIdx = 2; // Skip ID, nShadowBytes.
442437 break;
443438 case TargetOpcode::PATCHPOINT: {
444439 // For PatchPoint, the call args are not foldable.
445 PatchPointOpers opers(MI);
440 PatchPointOpers opers(&MI);
446441 StartIdx = opers.getVarIdx();
447442 break;
448443 }
458453 }
459454
460455 MachineInstr *NewMI =
461 MF.CreateMachineInstr(TII.get(MI->getOpcode()), MI->getDebugLoc(), true);
456 MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
462457 MachineInstrBuilder MIB(MF, NewMI);
463458
464459 // No need to fold return, the meta data, and function arguments
465460 for (unsigned i = 0; i < StartIdx; ++i)
466 MIB.addOperand(MI->getOperand(i));
467
468 for (unsigned i = StartIdx; i < MI->getNumOperands(); ++i) {
469 MachineOperand &MO = MI->getOperand(i);
461 MIB.addOperand(MI.getOperand(i));
462
463 for (unsigned i = StartIdx; i < MI.getNumOperands(); ++i) {
464 MachineOperand &MO = MI.getOperand(i);
470465 if (std::find(Ops.begin(), Ops.end(), i) != Ops.end()) {
471466 unsigned SpillSize;
472467 unsigned SpillOffset;
494489 /// operand folded, otherwise NULL is returned. The client is responsible for
495490 /// removing the old instruction and adding the new one in the instruction
496491 /// stream.
497 MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
498 ArrayRef Ops,
499 int FI,
492 MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
493 ArrayRef Ops, int FI,
500494 LiveIntervals *LIS) const {
501495 unsigned Flags = 0;
502496 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
503 if (MI->getOperand(Ops[i]).isDef())
497 if (MI.getOperand(Ops[i]).isDef())
504498 Flags |= MachineMemOperand::MOStore;
505499 else
506500 Flags |= MachineMemOperand::MOLoad;
507501
508 MachineBasicBlock *MBB = MI->getParent();
502 MachineBasicBlock *MBB = MI.getParent();
509503 assert(MBB && "foldMemoryOperand needs an inserted instruction");
510504 MachineFunction &MF = *MBB->getParent();
511505
512506 MachineInstr *NewMI = nullptr;
513507
514 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
515 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
508 if (MI.getOpcode() == TargetOpcode::STACKMAP ||
509 MI.getOpcode() == TargetOpcode::PATCHPOINT) {
516510 // Fold stackmap/patchpoint.
517511 NewMI = foldPatchpoint(MF, MI, Ops, FI, *this);
518512 if (NewMI)
523517 }
524518
525519 if (NewMI) {
526 NewMI->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
520 NewMI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
527521 // Add a memory operand, foldMemoryOperandImpl doesn't do that.
528522 assert((!(Flags & MachineMemOperand::MOStore) ||
529523 NewMI->mayStore()) &&
542536 }
543537
544538 // Straight COPY may fold as load/store.
545 if (!MI->isCopy() || Ops.size() != 1)
539 if (!MI.isCopy() || Ops.size() != 1)
546540 return nullptr;
547541
548542 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
549543 if (!RC)
550544 return nullptr;
551545
552 const MachineOperand &MO = MI->getOperand(1-Ops[0]);
546 const MachineOperand &MO = MI.getOperand(1 - Ops[0]);
553547 MachineBasicBlock::iterator Pos = MI;
554548 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
555549
776770 /// foldMemoryOperand - Same as the previous version except it allows folding
777771 /// of any load and store from / to any address, not just from a specific
778772 /// stack slot.
779 MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
773 MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
780774 ArrayRef Ops,
781 MachineInstr *LoadMI,
775 MachineInstr &LoadMI,
782776 LiveIntervals *LIS) const {
783 assert(LoadMI->canFoldAsLoad() && "LoadMI isn't foldable!");
777 assert(LoadMI.canFoldAsLoad() && "LoadMI isn't foldable!");
784778 #ifndef NDEBUG
785779 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
786 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
780 assert(MI.getOperand(Ops[i]).isUse() && "Folding load into def!");
787781 #endif
788 MachineBasicBlock &MBB = *MI->getParent();
782 MachineBasicBlock &MBB = *MI.getParent();
789783 MachineFunction &MF = *MBB.getParent();
790784
791785 // Ask the target to do the actual folding.
792786 MachineInstr *NewMI = nullptr;
793787 int FrameIndex = 0;
794788
795 if ((MI->getOpcode() == TargetOpcode::STACKMAP ||
796 MI->getOpcode() == TargetOpcode::PATCHPOINT) &&
789 if ((MI.getOpcode() == TargetOpcode::STACKMAP ||
790 MI.getOpcode() == TargetOpcode::PATCHPOINT) &&
797791 isLoadFromStackSlot(LoadMI, FrameIndex)) {
798792 // Fold stackmap/patchpoint.
799793 NewMI = foldPatchpoint(MF, MI, Ops, FrameIndex, *this);
807801 if (!NewMI) return nullptr;
808802
809803 // Copy the memoperands from the load to the folded instruction.
810 if (MI->memoperands_empty()) {
811 NewMI->setMemRefs(LoadMI->memoperands_begin(),
812 LoadMI->memoperands_end());
804 if (MI.memoperands_empty()) {
805 NewMI->setMemRefs(LoadMI.memoperands_begin(), LoadMI.memoperands_end());
813806 }
814807 else {
815808 // Handle the rare case of folding multiple loads.
816 NewMI->setMemRefs(MI->memoperands_begin(),
817 MI->memoperands_end());
818 for (MachineInstr::mmo_iterator I = LoadMI->memoperands_begin(),
819 E = LoadMI->memoperands_end(); I != E; ++I) {
809 NewMI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
810 for (MachineInstr::mmo_iterator I = LoadMI.memoperands_begin(),
811 E = LoadMI.memoperands_end();
812 I != E; ++I) {
820813 NewMI->addMemOperand(MF, *I);
821814 }
822815 }
823816 return NewMI;
824817 }
825818
826 bool TargetInstrInfo::
827 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
828 AliasAnalysis *AA) const {
829 const MachineFunction &MF = *MI->getParent()->getParent();
819 bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
820 const MachineInstr &MI, AliasAnalysis *AA) const {
821 const MachineFunction &MF = *MI.getParent()->getParent();
830822 const MachineRegisterInfo &MRI = MF.getRegInfo();
831823
832824 // Remat clients assume operand 0 is the defined register.
833 if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
825 if (!MI.getNumOperands() || !MI.getOperand(0).isReg())
834826 return false;
835 unsigned DefReg = MI->getOperand(0).getReg();
827 unsigned DefReg = MI.getOperand(0).getReg();
836828
837829 // A sub-register definition can only be rematerialized if the instruction
838830 // doesn't read the other parts of the register. Otherwise it is really a
839831 // read-modify-write operation on the full virtual register which cannot be
840832 // moved safely.
841833 if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
842 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
834 MI.getOperand(0).getSubReg() && MI.readsVirtualRegister(DefReg))
843835 return false;
844836
845837 // A load from a fixed stack slot can be rematerialized. This may be
851843 return true;
852844
853845 // Avoid instructions obviously unsafe for remat.
854 if (MI->isNotDuplicable() || MI->mayStore() ||
855 MI->hasUnmodeledSideEffects())
846 if (MI.isNotDuplicable() || MI.mayStore() || MI.hasUnmodeledSideEffects())
856847 return false;
857848
858849 // Don't remat inline asm. We have no idea how expensive it is
859850 // even if it's side effect free.
860 if (MI->isInlineAsm())
851 if (MI.isInlineAsm())
861852 return false;
862853
863854 // Avoid instructions which load from potentially varying memory.
864 if (MI->mayLoad() && !MI->isInvariantLoad(AA))
855 if (MI.mayLoad() && !MI.isInvariantLoad(AA))
865856 return false;
866857
867858 // If any of the registers accessed are non-constant, conservatively assume
868859 // the instruction is not rematerializable.
869 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
870 const MachineOperand &MO = MI->getOperand(i);
860 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
861 const MachineOperand &MO = MI.getOperand(i);
871862 if (!MO.isReg()) continue;
872863 unsigned Reg = MO.getReg();
873864 if (Reg == 0)
904895 return true;
905896 }
906897
907 int TargetInstrInfo::getSPAdjust(const MachineInstr *MI) const {
908 const MachineFunction *MF = MI->getParent()->getParent();
898 int TargetInstrInfo::getSPAdjust(const MachineInstr &MI) const {
899 const MachineFunction *MF = MI.getParent()->getParent();
909900 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
910901 bool StackGrowsDown =
911902 TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
913904 unsigned FrameSetupOpcode = getCallFrameSetupOpcode();
914905 unsigned FrameDestroyOpcode = getCallFrameDestroyOpcode();
915906
916 if (MI->getOpcode() != FrameSetupOpcode &&
917 MI->getOpcode() != FrameDestroyOpcode)
907 if (MI.getOpcode() != FrameSetupOpcode &&
908 MI.getOpcode() != FrameDestroyOpcode)
918909 return 0;
919
920 int SPAdj = MI->getOperand(0).getImm();
910
911 int SPAdj = MI.getOperand(0).getImm();
921912 SPAdj = TFI->alignSPAdjust(SPAdj);
922913
923 if ((!StackGrowsDown && MI->getOpcode() == FrameSetupOpcode) ||
924 (StackGrowsDown && MI->getOpcode() == FrameDestroyOpcode))
914 if ((!StackGrowsDown && MI.getOpcode() == FrameSetupOpcode) ||
915 (StackGrowsDown && MI.getOpcode() == FrameDestroyOpcode))
925916 SPAdj = -SPAdj;
926917
927918 return SPAdj;
930921 /// isSchedulingBoundary - Test if the given instruction should be
931922 /// considered a scheduling boundary. This primarily includes labels
932923 /// and terminators.
933 bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
924 bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
934925 const MachineBasicBlock *MBB,
935926 const MachineFunction &MF) const {
936927 // Terminators and labels can't be scheduled around.
937 if (MI->isTerminator() || MI->isPosition())
928 if (MI.isTerminator() || MI.isPosition())
938929 return true;
939930
940931 // Don't attempt to schedule around any instruction that defines
944935 // modification.
945936 const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
946937 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
947 return MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI);
938 return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI);
948939 }
949940
950941 // Provide a global flag for disabling the PreRA hazard recognizer that targets
10131004 // MachineInstr latency interface.
10141005 //===----------------------------------------------------------------------===//
10151006
1016 unsigned
1017 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1018 const MachineInstr *MI) const {
1007 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1008 const MachineInstr &MI) const {
10191009 if (!ItinData || ItinData->isEmpty())
10201010 return 1;
10211011
1022 unsigned Class = MI->getDesc().getSchedClass();
1012 unsigned Class = MI.getDesc().getSchedClass();
10231013 int UOps = ItinData->Itineraries[Class].NumMicroOps;
10241014 if (UOps >= 0)
10251015 return UOps;
10311021
10321022 /// Return the default expected latency for a def based on it's opcode.
10331023 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel,
1034 const MachineInstr *DefMI) const {
1035 if (DefMI->isTransient())
1024 const MachineInstr &DefMI) const {
1025 if (DefMI.isTransient())
10361026 return 0;
1037 if (DefMI->mayLoad())
1027 if (DefMI.mayLoad())
10381028 return SchedModel.LoadLatency;
1039 if (isHighLatencyDef(DefMI->getOpcode()))
1029 if (isHighLatencyDef(DefMI.getOpcode()))
10401030 return SchedModel.HighLatency;
10411031 return 1;
10421032 }
10451035 return 0;
10461036 }
10471037
1048 unsigned TargetInstrInfo::
1049 getInstrLatency(const InstrItineraryData *ItinData,
1050 const MachineInstr *MI,
1051 unsigned *PredCost) const {
1038 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1039 const MachineInstr &MI,
1040 unsigned *PredCost) const {
10521041 // Default to one cycle for no itinerary. However, an "empty" itinerary may
10531042 // still have a MinLatency property, which getStageLatency checks.
10541043 if (!ItinData)
1055 return MI->mayLoad() ? 2 : 1;
1056
1057 return ItinData->getStageLatency(MI->getDesc().getSchedClass());
1044 return MI.mayLoad() ? 2 : 1;
1045
1046 return ItinData->getStageLatency(MI.getDesc().getSchedClass());
10581047 }
10591048
10601049 bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
1061 const MachineInstr *DefMI,
1050 const MachineInstr &DefMI,
10621051 unsigned DefIdx) const {
10631052 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
10641053 if (!ItinData || ItinData->isEmpty())
10651054 return false;
10661055
1067 unsigned DefClass = DefMI->getDesc().getSchedClass();
1056 unsigned DefClass = DefMI.getDesc().getSchedClass();
10681057 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
10691058 return (DefCycle != -1 && DefCycle <= 1);
10701059 }
10711060
10721061 /// Both DefMI and UseMI must be valid. By default, call directly to the
10731062 /// itinerary. This may be overriden by the target.
1074 int TargetInstrInfo::
1075 getOperandLatency(const InstrItineraryData *ItinData,
1076 const MachineInstr *DefMI, unsigned DefIdx,
1077 const MachineInstr *UseMI, unsigned UseIdx) const {
1078 unsigned DefClass = DefMI->getDesc().getSchedClass();
1079 unsigned UseClass = UseMI->getDesc().getSchedClass();
1063 int TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
1064 const MachineInstr &DefMI,
1065 unsigned DefIdx,
1066 const MachineInstr &UseMI,
1067 unsigned UseIdx) const {
1068 unsigned DefClass = DefMI.getDesc().getSchedClass();
1069 unsigned UseClass = UseMI.getDesc().getSchedClass();
10801070 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
10811071 }
10821072
10831073 /// If we can determine the operand latency from the def only, without itinerary
10841074 /// lookup, do so. Otherwise return -1.
10851075 int TargetInstrInfo::computeDefOperandLatency(
1086 const InstrItineraryData *ItinData,
1087 const MachineInstr *DefMI) const {
1076 const InstrItineraryData *ItinData, const MachineInstr &DefMI) const {
10881077
10891078 // Let the target hook getInstrLatency handle missing itineraries.
10901079 if (!ItinData)
10971086 return -1;
10981087 }
10991088
1100 /// computeOperandLatency - Compute and return the latency of the given data
1101 /// dependent def and use when the operand indices are already known. UseMI may
1102 /// be NULL for an unknown use.
1103 ///
1104 /// FindMin may be set to get the minimum vs. expected latency. Minimum
1105 /// latency is used for scheduling groups, while expected latency is for
1106 /// instruction cost and critical path.
1107 ///
1108 /// Depending on the subtarget's itinerary properties, this may or may not need
1109 /// to call getOperandLatency(). For most subtargets, we don't need DefIdx or
1110 /// UseIdx to compute min latency.
1111 unsigned TargetInstrInfo::
1112 computeOperandLatency(const InstrItineraryData *ItinData,
1113 const MachineInstr *DefMI, unsigned DefIdx,
1114 const MachineInstr *UseMI, unsigned UseIdx) const {
1089 unsigned TargetInstrInfo::computeOperandLatency(
1090 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
1091 unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const {
11151092
11161093 int DefLatency = computeDefOperandLatency(ItinData, DefMI);
11171094 if (DefLatency >= 0)
11211098
11221099 int OperLatency = 0;
11231100 if (UseMI)
1124 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
1101 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, *UseMI, UseIdx);
11251102 else {
1126 unsigned DefClass = DefMI->getDesc().getSchedClass();
1103 unsigned DefClass = DefMI.getDesc().getSchedClass();
11271104 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx);
11281105 }
11291106 if (OperLatency >= 0)
7676 const MCSchedClassDesc *SC) const {
7777 if (hasInstrItineraries()) {
7878 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
79 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
79 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI);
8080 }
8181 if (hasInstrSchedModel()) {
8282 if (!SC)
155155 const MachineInstr *UseMI, unsigned UseOperIdx) const {
156156
157157 if (!hasInstrSchedModel() && !hasInstrItineraries())
158 return TII->defaultDefLatency(SchedModel, DefMI);
158 return TII->defaultDefLatency(SchedModel, *DefMI);
159159
160160 if (hasInstrItineraries()) {
161161 int OperLatency = 0;
162162 if (UseMI) {
163 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx,
164 UseMI, UseOperIdx);
163 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx,
164 *UseMI, UseOperIdx);
165165 }
166166 else {
167167 unsigned DefClass = DefMI->getDesc().getSchedClass();
171171 return OperLatency;
172172
173173 // No operand latency was found.
174 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
174 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI);
175175
176176 // Expected latency is the max of the stage latency and itinerary props.
177177 // Rather than directly querying InstrItins stage latency, we call a TII
178178 // hook to allow subtargets to specialize latency. This hook is only
179179 // applicable to the InstrItins model. InstrSchedModel should model all
180180 // special cases without TII hooks.
181 InstrLatency = std::max(InstrLatency,
182 TII->defaultDefLatency(SchedModel, DefMI));
181 InstrLatency =
182 std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI));
183183 return InstrLatency;
184184 }
185185 // hasInstrSchedModel()
218218 // FIXME: Automatically giving all implicit defs defaultDefLatency is
219219 // undesirable. We should only do it for defs that are known to the MC
220220 // desc like flags. Truly implicit defs should get 1 cycle latency.
221 return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, DefMI);
221 return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, *DefMI);
222222 }
223223
224224 unsigned
253253 // Allow subtargets to compute Bundle latencies outside the machine model.
254254 if (hasInstrItineraries() || MI->isBundle() ||
255255 (!hasInstrSchedModel() && !UseDefaultDefLatency))
256 return TII->getInstrLatency(&InstrItins, MI);
256 return TII->getInstrLatency(&InstrItins, *MI);
257257
258258 if (hasInstrSchedModel()) {
259259 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
260260 if (SCDesc->isValid())
261261 return computeInstrLatency(*SCDesc);
262262 }
263 return TII->defaultDefLatency(SchedModel, MI);
263 return TII->defaultDefLatency(SchedModel, *MI);
264264 }
265265
266266 unsigned TargetSchedModel::
646646 unsigned Dist) {
647647 unsigned RegC = MI->getOperand(RegCIdx).getReg();
648648 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
649 MachineInstr *NewMI = TII->commuteInstruction(MI, false, RegBIdx, RegCIdx);
649 MachineInstr *NewMI = TII->commuteInstruction(*MI, false, RegBIdx, RegCIdx);
650650
651651 if (NewMI == nullptr) {
652652 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
694694 unsigned Dist) {
695695 // FIXME: Why does convertToThreeAddress() need an iterator reference?
696696 MachineFunction::iterator MFI = MBB->getIterator();
697 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV);
697 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, *mi, LV);
698698 assert(MBB->getIterator() == MFI &&
699699 "convertToThreeAddress changed iterator reference");
700700 if (!NewMI)
860860 if (!MI->isSafeToMove(AA, SeenStore))
861861 return false;
862862
863 if (TII->getInstrLatency(InstrItins, MI) > 1)
863 if (TII->getInstrLatency(InstrItins, *MI) > 1)
864864 // FIXME: Needs more sophisticated heuristics.
865865 return false;
866866
992992 return true; // Below MI
993993 unsigned DefDist = DDI->second;
994994 assert(Dist > DefDist && "Visited def already?");
995 if (TII->getInstrLatency(InstrItins, &DefMI) > (Dist - DefDist))
995 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
996996 return true;
997997 }
998998 return false;
11731173 // other commutable operands and does not change the values of passed
11741174 // variables.
11751175 if (OtherOpIdx == BaseOpIdx ||
1176 !TII->findCommutedOpIndices(MI, BaseOpIdx, OtherOpIdx))
1176 !TII->findCommutedOpIndices(*MI, BaseOpIdx, OtherOpIdx))
11771177 continue;
11781178
11791179 unsigned OtherOpReg = MI->getOperand(OtherOpIdx).getReg();
13061306 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
13071307 unsigned Reg = MRI->createVirtualRegister(RC);
13081308 SmallVector NewMIs;
1309 if (!TII->unfoldMemoryOperand(*MF, &MI, Reg,
1310 /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
1311 NewMIs)) {
1309 if (!TII->unfoldMemoryOperand(*MF, MI, Reg,
1310 /*UnfoldLoad=*/true,
1311 /*UnfoldStore=*/false, NewMIs)) {
13121312 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
13131313 return false;
13141314 }
176176 void AArch64BranchRelaxation::computeBlockSize(const MachineBasicBlock &MBB) {
177177 unsigned Size = 0;
178178 for (const MachineInstr &MI : MBB)
179 Size += TII->GetInstSizeInBytes(&MI);
179 Size += TII->GetInstSizeInBytes(MI);
180180 BlockInfo[MBB.getNumber()].Size = Size;
181181 }
182182
194194 // Sum instructions before MI in MBB.
195195 for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
196196 assert(I != MBB->end() && "Didn't find MI in its own basic block?");
197 Offset += TII->GetInstSizeInBytes(I);
197 Offset += TII->GetInstSizeInBytes(*I);
198198 }
199199 return Offset;
200200 }
419419 MachineBasicBlock *NewBB = splitBlockBeforeInstr(MI);
420420 // No need for the branch to the next block. We're adding an unconditional
421421 // branch to the destination.
422 int delta = TII->GetInstSizeInBytes(&MBB->back());
422 int delta = TII->GetInstSizeInBytes(MBB->back());
423423 BlockInfo[MBB->getNumber()].Size -= delta;
424424 MBB->back().eraseFromParent();
425425 // BlockInfo[SplitBB].Offset is wrong temporarily, fixed below
445445 if (MI->getOpcode() == AArch64::Bcc)
446446 invertBccCondition(MIB);
447447 MIB.addMBB(NextBB);
448 BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
448 BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
449449 BuildMI(MBB, DebugLoc(), TII->get(AArch64::B)).addMBB(DestBB);
450 BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
450 BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
451451
452452 // Remove the old conditional branch. It may or may not still be in MBB.
453 BlockInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(MI);
453 BlockInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI);
454454 MI->eraseFromParent();
455455
456456 // Finally, keep the block offsets up to date.
3434
3535 /// GetInstSize - Return the number of bytes of code the specified
3636 /// instruction may be. This returns the maximum number of bytes.
37 unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
38 const MachineBasicBlock &MBB = *MI->getParent();
37 unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
38 const MachineBasicBlock &MBB = *MI.getParent();
3939 const MachineFunction *MF = MBB.getParent();
4040 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4141
42 if (MI->getOpcode() == AArch64::INLINEASM)
43 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
44
45 const MCInstrDesc &Desc = MI->getDesc();
42 if (MI.getOpcode() == AArch64::INLINEASM)
43 return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
44
45 const MCInstrDesc &Desc = MI.getDesc();
4646 switch (Desc.getOpcode()) {
4747 default:
4848 // Anything not explicitly designated otherwise is a nomal 4-byte insn.
535535 }
536536
537537 /// Returns true if a MOVi32imm or MOVi64imm can be expanded to an ORRxx.
538 static bool canBeExpandedToORR(const MachineInstr *MI, unsigned BitSize) {
539 uint64_t Imm = MI->getOperand(1).getImm();
538 static bool canBeExpandedToORR(const MachineInstr &MI, unsigned BitSize) {
539 uint64_t Imm = MI.getOperand(1).getImm();
540540 uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
541541 uint64_t Encoding;
542542 return AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding);
544544
545545 // FIXME: this implementation should be micro-architecture dependent, so a
546546 // micro-architecture target hook should be introduced here in future.
547 bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr *MI) const {
547 bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
548548 if (!Subtarget.hasCustomCheapAsMoveHandling())
549 return MI->isAsCheapAsAMove();
549 return MI.isAsCheapAsAMove();
550550
551551 unsigned Imm;
552552
553 switch (MI->getOpcode()) {
553 switch (MI.getOpcode()) {
554554 default:
555555 return false;
556556
560560 case AArch64::SUBWri:
561561 case AArch64::SUBXri:
562562 return (Subtarget.getProcFamily() == AArch64Subtarget::ExynosM1 ||
563 MI->getOperand(3).getImm() == 0);
563 MI.getOperand(3).getImm() == 0);
564564
565565 // add/sub on register with shift
566566 case AArch64::ADDWrs:
567567 case AArch64::ADDXrs:
568568 case AArch64::SUBWrs:
569569 case AArch64::SUBXrs:
570 Imm = MI->getOperand(3).getImm();
570 Imm = MI.getOperand(3).getImm();
571571 return (Subtarget.getProcFamily() == AArch64Subtarget::ExynosM1 &&
572572 AArch64_AM::getArithShiftValue(Imm) < 4);
573573
608608 case AArch64::ORNXrs:
609609 case AArch64::ORRWrs:
610610 case AArch64::ORRXrs:
611 Imm = MI->getOperand(3).getImm();
611 Imm = MI.getOperand(3).getImm();
612612 return (Subtarget.getProcFamily() == AArch64Subtarget::ExynosM1 &&
613613 AArch64_AM::getShiftValue(Imm) < 4 &&
614614 AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL);
644644 }
645645 }
646646
647 bool
648 AArch64InstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
649 MachineInstr *MIb,
650 AliasAnalysis *AA) const {
647 bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint(
648 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const {
651649 const TargetRegisterInfo *TRI = &getRegisterInfo();
652650 unsigned BaseRegA = 0, BaseRegB = 0;
653651 int64_t OffsetA = 0, OffsetB = 0;
654652 unsigned WidthA = 0, WidthB = 0;
655653
656 assert(MIa && MIa->mayLoadOrStore() && "MIa must be a load or store.");
657 assert(MIb && MIb->mayLoadOrStore() && "MIb must be a load or store.");
658
659 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() ||
660 MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
654 assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
655 assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
656
657 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
658 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
661659 return false;
662660
663661 // Retrieve the base register, offset from the base register and width. Width
681679 /// analyzeCompare - For a comparison instruction, return the source registers
682680 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
683681 /// Return true if the comparison instruction can be analyzed.
684 bool AArch64InstrInfo::analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
682 bool AArch64InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
685683 unsigned &SrcReg2, int &CmpMask,
686684 int &CmpValue) const {
687 switch (MI->getOpcode()) {
685 switch (MI.getOpcode()) {
688686 default:
689687 break;
690688 case AArch64::SUBSWrr:
700698 case AArch64::ADDSXrs:
701699 case AArch64::ADDSXrx:
702700 // Replace SUBSWrr with SUBWrr if NZCV is not used.
703 SrcReg = MI->getOperand(1).getReg();
704 SrcReg2 = MI->getOperand(2).getReg();
701 SrcReg = MI.getOperand(1).getReg();
702 SrcReg2 = MI.getOperand(2).getReg();
705703 CmpMask = ~0;
706704 CmpValue = 0;
707705 return true;
709707 case AArch64::ADDSWri:
710708 case AArch64::SUBSXri:
711709 case AArch64::ADDSXri:
712 SrcReg = MI->getOperand(1).getReg();
710 SrcReg = MI.getOperand(1).getReg();
713711 SrcReg2 = 0;
714712 CmpMask = ~0;
715713 // FIXME: In order to convert CmpValue to 0 or 1
716 CmpValue = (MI->getOperand(2).getImm() != 0);
714 CmpValue = MI.getOperand(2).getImm() != 0;
717715 return true;
718716 case AArch64::ANDSWri:
719717 case AArch64::ANDSXri:
720718 // ANDS does not use the same encoding scheme as the others xxxS
721719 // instructions.
722 SrcReg = MI->getOperand(1).getReg();
720 SrcReg = MI.getOperand(1).getReg();
723721 SrcReg2 = 0;
724722 CmpMask = ~0;
725723 // FIXME:The return val type of decodeLogicalImmediate is uint64_t,
727725 // the high 32 bits of uint64_t will be lost.
728726 // In fact it causes a bug in spec2006-483.xalancbmk
729727 // CmpValue is only used to compare with zero in OptimizeCompareInstr
730 CmpValue = (AArch64_AM::decodeLogicalImmediate(
731 MI->getOperand(2).getImm(),
732 MI->getOpcode() == AArch64::ANDSWri ? 32 : 64) != 0);
728 CmpValue = AArch64_AM::decodeLogicalImmediate(
729 MI.getOperand(2).getImm(),
730 MI.getOpcode() == AArch64::ANDSWri ? 32 : 64) != 0;
733731 return true;
734732 }
735733
736734 return false;
737735 }
738736
739 static bool UpdateOperandRegClass(MachineInstr *Instr) {
740 MachineBasicBlock *MBB = Instr->getParent();
737 static bool UpdateOperandRegClass(MachineInstr &Instr) {
738 MachineBasicBlock *MBB = Instr.getParent();
741739 assert(MBB && "Can't get MachineBasicBlock here");
742740 MachineFunction *MF = MBB->getParent();
743741 assert(MF && "Can't get MachineFunction here");
745743 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
746744 MachineRegisterInfo *MRI = &MF->getRegInfo();
747745
748 for (unsigned OpIdx = 0, EndIdx = Instr->getNumOperands(); OpIdx < EndIdx;
746 for (unsigned OpIdx = 0, EndIdx = Instr.getNumOperands(); OpIdx < EndIdx;
749747 ++OpIdx) {
750 MachineOperand &MO = Instr->getOperand(OpIdx);
748 MachineOperand &MO = Instr.getOperand(OpIdx);
751749 const TargetRegisterClass *OpRegCstraints =
752 Instr->getRegClassConstraint(OpIdx, TII, TRI);
750 Instr.getRegClassConstraint(OpIdx, TII, TRI);
753751
754752 // If there's no constraint, there's nothing to do.
755753 if (!OpRegCstraints)
777775 /// \brief Return the opcode that does not set flags when possible - otherwise
778776 /// return the original opcode. The caller is responsible to do the actual
779777 /// substitution and legality checking.
780 static unsigned convertFlagSettingOpcode(const MachineInstr *MI) {
778 static unsigned convertFlagSettingOpcode(const MachineInstr &MI) {
781779 // Don't convert all compare instructions, because for some the zero register
782780 // encoding becomes the sp register.
783781 bool MIDefinesZeroReg = false;
784 if (MI->definesRegister(AArch64::WZR) || MI->definesRegister(AArch64::XZR))
782 if (MI.definesRegister(AArch64::WZR) || MI.definesRegister(AArch64::XZR))
785783 MIDefinesZeroReg = true;
786784
787 switch (MI->getOpcode()) {
785 switch (MI.getOpcode()) {
788786 default:
789 return MI->getOpcode();
787 return MI.getOpcode();
790788 case AArch64::ADDSWrr:
791789 return AArch64::ADDWrr;
792790 case AArch64::ADDSWri:
833831 ///
834832 /// Note: If From and To are from different blocks it's assumed CC are accessed
835833 /// on the path.
836 static bool areCFlagsAccessedBetweenInstrs(MachineInstr *From, MachineInstr *To,
837 const TargetRegisterInfo *TRI,
838 const AccessKind AccessToCheck = AK_All) {
839 // We iterate backward starting \p To until we hit \p From
840 MachineBasicBlock::iterator I = To, E = From, B = To->getParent()->begin();
841
834 static bool areCFlagsAccessedBetweenInstrs(
835 MachineBasicBlock::iterator From, MachineBasicBlock::iterator To,
836 const TargetRegisterInfo *TRI, const AccessKind AccessToCheck = AK_All) {
842837 // Early exit if To is at the beginning of the BB.
843 if (I == B)
838 if (To == To->getParent()->begin())
844839 return true;
845840
846841 // Check whether the instructions are in the same basic block
855850 return &MI == From;
856851 }) != To->getParent()->rend());
857852
858 for (--I; I != E; --I) {
859 const MachineInstr &Instr = *I;
853 // We iterate backward starting \p To until we hit \p From.
854 for (--To; To != From; --To) {
855 const MachineInstr &Instr = *To;
860856
861857 if ( ((AccessToCheck & AK_Write) && Instr.modifiesRegister(AArch64::NZCV, TRI)) ||
862858 ((AccessToCheck & AK_Read) && Instr.readsRegister(AArch64::NZCV, TRI)))
875871 /// condition code or an instruction which can be converted into such an instruction.
876872 /// Only comparison with zero is supported.
877873 bool AArch64InstrInfo::optimizeCompareInstr(
878 MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
874 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
879875 int CmpValue, const MachineRegisterInfo *MRI) const {
880 assert(CmpInstr);
881 assert(CmpInstr->getParent());
876 assert(CmpInstr.getParent());
882877 assert(MRI);
883878
884879 // Replace SUBSWrr with SUBWrr if NZCV is not used.
885 int DeadNZCVIdx = CmpInstr->findRegisterDefOperandIdx(AArch64::NZCV, true);
880 int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true);
886881 if (DeadNZCVIdx != -1) {
887 if (CmpInstr->definesRegister(AArch64::WZR) ||
888 CmpInstr->definesRegister(AArch64::XZR)) {
889 CmpInstr->eraseFromParent();
882 if (CmpInstr.definesRegister(AArch64::WZR) ||
883 CmpInstr.definesRegister(AArch64::XZR)) {
884 CmpInstr.eraseFromParent();
890885 return true;
891886 }
892 unsigned Opc = CmpInstr->getOpcode();
887 unsigned Opc = CmpInstr.getOpcode();
893888 unsigned NewOpc = convertFlagSettingOpcode(CmpInstr);
894889 if (NewOpc == Opc)
895890 return false;
896891 const MCInstrDesc &MCID = get(NewOpc);
897 CmpInstr->setDesc(MCID);
898 CmpInstr->RemoveOperand(DeadNZCVIdx);
892 CmpInstr.setDesc(MCID);
893 CmpInstr.RemoveOperand(DeadNZCVIdx);
899894 bool succeeded = UpdateOperandRegClass(CmpInstr);
900895 (void)succeeded;
901896 assert(succeeded && "Some operands reg class are incompatible!");
910905 return false;
911906
912907 // CmpInstr is a Compare instruction if destination register is not used.
913 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
908 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
914909 return false;
915910
916911 return substituteCmpToZero(CmpInstr, SrcReg, MRI);
11111106 /// which produces needed condition flags.
11121107 ///
11131108 /// Return true on success.
1114 bool AArch64InstrInfo::substituteCmpToZero(MachineInstr *CmpInstr,
1115 unsigned SrcReg, const MachineRegisterInfo *MRI) const {
1116 assert(CmpInstr);
1109 bool AArch64InstrInfo::substituteCmpToZero(
1110 MachineInstr &CmpInstr, unsigned SrcReg,
1111 const MachineRegisterInfo *MRI) const {
11171112 assert(MRI);
11181113 // Get the unique definition of SrcReg.
11191114 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
11261121 if (NewOpc == AArch64::INSTRUCTION_LIST_END)
11271122 return false;
11281123
1129 if (!canInstrSubstituteCmpInstr(MI, CmpInstr, TRI))
1124 if (!canInstrSubstituteCmpInstr(MI, &CmpInstr, TRI))
11301125 return false;
11311126
11321127 // Update the instruction to set NZCV.
11331128 MI->setDesc(get(NewOpc));
1134 CmpInstr->eraseFromParent();
1135 bool succeeded = UpdateOperandRegClass(MI);
1129 CmpInstr.eraseFromParent();
1130 bool succeeded = UpdateOperandRegClass(*MI);
11361131 (void)succeeded;
11371132 assert(succeeded && "Some operands reg class are incompatible!");
11381133 MI->addRegisterDefined(AArch64::NZCV, TRI);
11391134 return true;
11401135 }
11411136
1142 bool
1143 AArch64InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1144 if (MI->getOpcode() != TargetOpcode::LOAD_STACK_GUARD)
1145 return false;
1146
1147 MachineBasicBlock &MBB = *MI->getParent();
1148 DebugLoc DL = MI->getDebugLoc();
1149 unsigned Reg = MI->getOperand(0).getReg();
1137 bool AArch64InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1138 if (MI.getOpcode() != TargetOpcode::LOAD_STACK_GUARD)
1139 return false;
1140
1141 MachineBasicBlock &MBB = *MI.getParent();
1142 DebugLoc DL = MI.getDebugLoc();
1143 unsigned Reg = MI.getOperand(0).getReg();
11501144 const GlobalValue *GV =
1151 cast((*MI->memoperands_begin())->getValue());
1145 cast((*MI.memoperands_begin())->getValue());
11521146 const TargetMachine &TM = MBB.getParent()->getTarget();
11531147 unsigned char OpFlags = Subtarget.ClassifyGlobalReference(GV, TM);
11541148 const unsigned char MO_NC = AArch64II::MO_NC;
11571151 BuildMI(MBB, MI, DL, get(AArch64::LOADgot), Reg)
11581152 .addGlobalAddress(GV, 0, AArch64II::MO_GOT);
11591153 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1160 .addReg(Reg, RegState::Kill).addImm(0)
1161 .addMemOperand(*MI->memoperands_begin());
1154 .addReg(Reg, RegState::Kill)
1155 .addImm(0)
1156 .addMemOperand(*MI.memoperands_begin());
11621157 } else if (TM.getCodeModel() == CodeModel::Large) {
11631158 BuildMI(MBB, MI, DL, get(AArch64::MOVZXi), Reg)
11641159 .addGlobalAddress(GV, 0, AArch64II::MO_G3).addImm(48);
11721167 .addReg(Reg, RegState::Kill)
11731168 .addGlobalAddress(GV, 0, AArch64II::MO_G0 | MO_NC).addImm(0);
11741169 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1175 .addReg(Reg, RegState::Kill).addImm(0)
1176 .addMemOperand(*MI->memoperands_begin());
1170 .addReg(Reg, RegState::Kill)
1171 .addImm(0)
1172 .addMemOperand(*MI.memoperands_begin());
11771173 } else {
11781174 BuildMI(MBB, MI, DL, get(AArch64::ADRP), Reg)
11791175 .addGlobalAddress(GV, 0, OpFlags | AArch64II::MO_PAGE);
11811177 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
11821178 .addReg(Reg, RegState::Kill)
11831179 .addGlobalAddress(GV, 0, LoFlags)
1184 .addMemOperand(*MI->memoperands_begin());
1180 .addMemOperand(*MI.memoperands_begin());
11851181 }
11861182
11871183 MBB.erase(MI);
11901186 }
11911187
11921188 /// Return true if this is this instruction has a non-zero immediate
1193 bool AArch64InstrInfo::hasShiftedReg(const MachineInstr *MI) const {
1194 switch (MI->getOpcode()) {
1189 bool AArch64InstrInfo::hasShiftedReg(const MachineInstr &MI) const {
1190 switch (MI.getOpcode()) {
11951191 default:
11961192 break;
11971193 case AArch64::ADDSWrs:
12261222 case AArch64::SUBSXrs:
12271223 case AArch64::SUBWrs:
12281224 case AArch64::SUBXrs:
1229 if (MI->getOperand(3).isImm()) {
1230 unsigned val = MI->getOperand(3).getImm();
1225 if (MI.getOperand(3).isImm()) {
1226 unsigned val = MI.getOperand(3).getImm();
12311227 return (val != 0);
12321228 }
12331229 break;
12361232 }
12371233
12381234 /// Return true if this is this instruction has a non-zero immediate
1239 bool AArch64InstrInfo::hasExtendedReg(const MachineInstr *MI) const {
1240 switch (MI->getOpcode()) {
1235 bool AArch64InstrInfo::hasExtendedReg(const MachineInstr &MI) const {
1236 switch (MI.getOpcode()) {
12411237 default:
12421238 break;
12431239 case AArch64::ADDSWrx:
12521248 case AArch64::SUBWrx:
12531249 case AArch64::SUBXrx:
12541250 case AArch64::SUBXrx64:
1255 if (MI->getOperand(3).isImm()) {
1256 unsigned val = MI->getOperand(3).getImm();
1251 if (MI.getOperand(3).isImm()) {
1252 unsigned val = MI.getOperand(3).getImm();
12571253 return (val != 0);
12581254 }
12591255 break;
12641260
12651261 // Return true if this instruction simply sets its single destination register
12661262 // to zero. This is equivalent to a register rename of the zero-register.
1267 bool AArch64InstrInfo::isGPRZero(const MachineInstr *MI) const {
1268 switch (MI->getOpcode()) {
1263 bool AArch64InstrInfo::isGPRZero(const MachineInstr &MI) const {
1264 switch (MI.getOpcode()) {
12691265 default:
12701266 break;
12711267 case AArch64::MOVZWi:
12721268 case AArch64::MOVZXi: // movz Rd, #0 (LSL #0)
1273 if (MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0) {
1274 assert(MI->getDesc().getNumOperands() == 3 &&
1275 MI->getOperand(2).getImm() == 0 && "invalid MOVZi operands");
1269 if (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) {
1270 assert(MI.getDesc().getNumOperands() == 3 &&
1271 MI.getOperand(2).getImm() == 0 && "invalid MOVZi operands");
12761272 return true;
12771273 }
12781274 break;
12791275 case AArch64::ANDWri: // and Rd, Rzr, #imm
1280 return MI->getOperand(1).getReg() == AArch64::WZR;
1276 return MI.getOperand(1).getReg() == AArch64::WZR;
12811277 case AArch64::ANDXri:
1282 return MI->getOperand(1).getReg() == AArch64::XZR;
1278 return MI.getOperand(1).getReg() == AArch64::XZR;
12831279 case TargetOpcode::COPY:
1284 return MI->getOperand(1).getReg() == AArch64::WZR;
1280 return MI.getOperand(1).getReg() == AArch64::WZR;
12851281 }
12861282 return false;
12871283 }
12881284
12891285 // Return true if this instruction simply renames a general register without
12901286 // modifying bits.
1291 bool AArch64InstrInfo::isGPRCopy(const MachineInstr *MI) const {
1292 switch (MI->getOpcode()) {
1287 bool AArch64InstrInfo::isGPRCopy(const MachineInstr &MI) const {
1288 switch (MI.getOpcode()) {
12931289 default:
12941290 break;
12951291 case TargetOpcode::COPY: {
12961292 // GPR32 copies will by lowered to ORRXrs
1297 unsigned DstReg = MI->getOperand(0).getReg();
1293 unsigned DstReg = MI.getOperand(0).getReg();
12981294 return (AArch64::GPR32RegClass.contains(DstReg) ||
12991295 AArch64::GPR64RegClass.contains(DstReg));
13001296 }
13011297 case AArch64::ORRXrs: // orr Xd, Xzr, Xm (LSL #0)
1302 if (MI->getOperand(1).getReg() == AArch64::XZR) {
1303 assert(MI->getDesc().getNumOperands() == 4 &&
1304 MI->getOperand(3).getImm() == 0 && "invalid ORRrs operands");
1298 if (MI.getOperand(1).getReg() == AArch64::XZR) {
1299 assert(MI.getDesc().getNumOperands() == 4 &&
1300 MI.getOperand(3).getImm() == 0 && "invalid ORRrs operands");
13051301 return true;
13061302 }
13071303 break;
13081304 case AArch64::ADDXri: // add Xd, Xn, #0 (LSL #0)
1309 if (MI->getOperand(2).getImm() == 0) {
1310 assert(MI->getDesc().getNumOperands() == 4 &&
1311 MI->getOperand(3).getImm() == 0 && "invalid ADDXri operands");
1305 if (MI.getOperand(2).getImm() == 0) {
1306 assert(MI.getDesc().getNumOperands() == 4 &&
1307 MI.getOperand(3).getImm() == 0 && "invalid ADDXri operands");
13121308 return true;
13131309 }
13141310 break;
13181314
13191315 // Return true if this instruction simply renames a general register without
13201316 // modifying bits.
1321 bool AArch64InstrInfo::isFPRCopy(const MachineInstr *MI) const {
1322 switch (MI->getOpcode()) {
1317 bool AArch64InstrInfo::isFPRCopy(const MachineInstr &MI) const {
1318 switch (MI.getOpcode()) {
13231319 default:
13241320 break;
13251321 case TargetOpcode::COPY: {
13261322 // FPR64 copies will by lowered to ORR.16b
1327 unsigned DstReg = MI->getOperand(0).getReg();
1323 unsigned DstReg = MI.getOperand(0).getReg();
13281324 return (AArch64::FPR64RegClass.contains(DstReg) ||
13291325 AArch64::FPR128RegClass.contains(DstReg));
13301326 }
13311327 case AArch64::ORRv16i8:
1332 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
1333 assert(MI->getDesc().getNumOperands() == 3 && MI->getOperand(0).isReg() &&
1328 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
1329 assert(MI.getDesc().getNumOperands() == 3 && MI.getOperand(0).isReg() &&
13341330 "invalid ORRv16i8 operands");
13351331 return true;
13361332 }
13391335 return false;
13401336 }
13411337
1342 unsigned AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1338 unsigned AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
13431339 int &FrameIndex) const {
1344 switch (MI->getOpcode()) {
1340 switch (MI.getOpcode()) {
13451341 default:
13461342 break;
13471343 case AArch64::LDRWui:
13511347 case AArch64::LDRSui:
13521348 case AArch64::LDRDui:
13531349 case AArch64::LDRQui:
1354 if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() &&
1355 MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) {
1356 FrameIndex = MI->getOperand(1).getIndex();
1357 return MI->getOperand(0).getReg();
1350 if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
1351 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
1352 FrameIndex = MI.getOperand(1).getIndex();
1353 return MI.getOperand(0).getReg();
13581354 }
13591355 break;
13601356 }
13621358 return 0;
13631359 }
13641360
1365 unsigned AArch64InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1361 unsigned AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
13661362 int &FrameIndex) const {
1367 switch (MI->getOpcode()) {
1363 switch (MI.getOpcode()) {
13681364 default:
13691365 break;
13701366 case AArch64::STRWui:
13741370 case AArch64::STRSui:
13751371 case AArch64::STRDui:
13761372 case AArch64::STRQui:
1377 if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() &&
1378 MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) {
1379 FrameIndex = MI->getOperand(1).getIndex();
1380 return MI->getOperand(0).getReg();
1373 if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
1374 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
1375 FrameIndex = MI.getOperand(1).getIndex();
1376 return MI.getOperand(0).getReg();
13811377 }
13821378 break;
13831379 }
13871383 /// Return true if this is load/store scales or extends its register offset.
13881384 /// This refers to scaling a dynamic index as opposed to scaled immediates.
13891385 /// MI should be a memory op that allows scaled addressing.
1390 bool AArch64InstrInfo::isScaledAddr(const MachineInstr *MI) const {
1391 switch (MI->getOpcode()) {
1386 bool AArch64InstrInfo::isScaledAddr(const MachineInstr &MI) const {
1387 switch (MI.getOpcode()) {
13921388 default:
13931389 break;
13941390 case AArch64::LDRBBroW:
14381434 case AArch64::STRWroX:
14391435 case AArch64::STRXroX:
14401436
1441 unsigned Val = MI->getOperand(3).getImm();
1437 unsigned Val = MI.getOperand(3).getImm();
14421438 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getMemExtendType(Val);
14431439 return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val);
14441440 }
14461442 }
14471443
14481444 /// Check all MachineMemOperands for a hint to suppress pairing.
1449 bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr *MI) const {
1445 bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr &MI) const {
14501446 static_assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits),
14511447 "Too many target MO flags");
1452 for (auto *MM : MI->memoperands()) {
1448 for (auto *MM : MI.memoperands()) {
14531449 if (MM->getFlags() &
14541450 (MOSuppressPair << MachineMemOperand::MOTargetStartBit)) {
14551451 return true;
14591455 }
14601456
14611457 /// Set a flag on the first MachineMemOperand to suppress pairing.
1462 void AArch64InstrInfo::suppressLdStPair(MachineInstr *MI) const {
1463 if (MI->memoperands_empty())
1458 void AArch64InstrInfo::suppressLdStPair(MachineInstr &MI) const {
1459 if (MI.memoperands_empty())
14641460 return;
14651461
14661462 static_assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits),
14671463 "Too many target MO flags");
1468 (*MI->memoperands_begin())
1464 (*MI.memoperands_begin())
14691465 ->setFlags(MOSuppressPair << MachineMemOperand::MOTargetStartBit);
14701466 }
14711467
14941490 }
14951491 }
14961492
1497 bool AArch64InstrInfo::isUnscaledLdSt(MachineInstr *MI) const {
1498 return isUnscaledLdSt(MI->getOpcode());
1493 bool AArch64InstrInfo::isUnscaledLdSt(MachineInstr &MI) const {
1494 return isUnscaledLdSt(MI.getOpcode());
14991495 }
15001496
15011497 // Is this a candidate for ld/st merging or pairing? For example, we don't
15021498 // touch volatiles or load/stores that have a hint to avoid pair formation.
1503 bool AArch64InstrInfo::isCandidateToMergeOrPair(MachineInstr *MI) const {
1499 bool AArch64InstrInfo::isCandidateToMergeOrPair(MachineInstr &MI) const {
15041500 // If this is a volatile load/store, don't mess with it.
1505 if (MI->hasOrderedMemoryRef())
1501 if (MI.hasOrderedMemoryRef())
15061502 return false;
15071503
15081504 // Make sure this is a reg+imm (as opposed to an address reloc).
1509 assert(MI->getOperand(1).isReg() && "Expected a reg operand.");
1510 if (!MI->getOperand(2).isImm())
1505 assert(MI.getOperand(1).isReg() && "Expected a reg operand.");
1506 if (!MI.getOperand(2).isImm())
15111507 return false;
15121508
15131509 // Can't merge/pair if the instruction modifies the base register.
15141510 // e.g., ldr x0, [x0]
1515 unsigned BaseReg = MI->getOperand(1).getReg();
1511 unsigned BaseReg = MI.getOperand(1).getReg();
15161512 const TargetRegisterInfo *TRI = &getRegisterInfo();
1517 if (MI->modifiesRegister(BaseReg, TRI))
1513 if (MI.modifiesRegister(BaseReg, TRI))
15181514 return false;
15191515
15201516 // Check if this load/store has a hint to avoid pair formation.
15241520
15251521 // On some CPUs quad load/store pairs are slower than two single load/stores.
15261522 if (Subtarget.avoidQuadLdStPairs()) {
1527 switch (MI->getOpcode()) {
1523 switch (MI.getOpcode()) {
15281524 default:
15291525 break;
15301526
15401536 }
15411537
15421538 bool AArch64InstrInfo::getMemOpBaseRegImmOfs(
1543 MachineInstr *LdSt, unsigned &BaseReg, int64_t &Offset,
1539 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset,
15441540 const TargetRegisterInfo *TRI) const {
1545 switch (LdSt->getOpcode()) {
1541 switch (LdSt.getOpcode()) {
15461542 default:
15471543 return false;
15481544 // Scaled instructions.
15751571 }
15761572
15771573 bool AArch64InstrInfo::getMemOpBaseRegImmOfsWidth(
1578 MachineInstr *LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width,
1574 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width,
15791575 const TargetRegisterInfo *TRI) const {
1580 assert(LdSt->mayLoadOrStore() && "Expected a memory operation.");
1576 assert(LdSt.mayLoadOrStore() && "Expected a memory operation.");
15811577 // Handle only loads/stores with base register followed by immediate offset.
1582 if (LdSt->getNumExplicitOperands() == 3) {
1578 if (LdSt.getNumExplicitOperands() == 3) {
15831579 // Non-paired instruction (e.g., ldr x1, [x0, #8]).
1584 if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm())
1580 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm())
15851581 return false;
1586 } else if (LdSt->getNumExplicitOperands() == 4) {
1582 } else if (LdSt.getNumExplicitOperands() == 4) {
15871583 // Paired instruction (e.g., ldp x1, x2, [x0, #8]).
1588 if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isReg() || !LdSt->getOperand(3).isImm())
1584 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isReg() ||
1585 !LdSt.getOperand(3).isImm())
15891586 return false;
15901587 } else
15911588 return false;
15931590 // Offset is calculated as the immediate operand multiplied by the scaling factor.
15941591 // Unscaled instructions have scaling factor set to 1.
15951592 unsigned Scale = 0;
1596 switch (LdSt->getOpcode()) {
1593 switch (LdSt.getOpcode()) {
15971594 default:
15981595 return false;
15991596 case AArch64::LDURQi:
16941691 break;
16951692 }
16961693
1697 if (LdSt->getNumExplicitOperands() == 3) {
1698 BaseReg = LdSt->getOperand(1).getReg();
1699 Offset = LdSt->getOperand(2).getImm() * Scale;
1694 if (LdSt.getNumExplicitOperands() == 3) {
1695 BaseReg = LdSt.getOperand(1).getReg();
1696 Offset = LdSt.getOperand(2).getImm() * Scale;
17001697 } else {
1701 assert(LdSt->getNumExplicitOperands() == 4 && "invalid number of operands");
1702 BaseReg = LdSt->getOperand(2).getReg();
1703 Offset = LdSt->getOperand(3).getImm() * Scale;
1698 assert(LdSt.getNumExplicitOperands() == 4 && "invalid number of operands");
1699 BaseReg = LdSt.getOperand(2).getReg();
1700 Offset = LdSt.getOperand(3).getImm() * Scale;
17041701 }
17051702 return true;
17061703 }
17621759 /// Detect opportunities for ldp/stp formation.
17631760 ///
17641761 /// Only called for LdSt for which getMemOpBaseRegImmOfs returns true.
1765 bool AArch64InstrInfo::shouldClusterMemOps(MachineInstr *FirstLdSt,
1766 MachineInstr *SecondLdSt,
1762 bool AArch64InstrInfo::shouldClusterMemOps(MachineInstr &FirstLdSt,
1763 MachineInstr &SecondLdSt,
17671764 unsigned NumLoads) const {
17681765 // Only cluster up to a single pair.
17691766 if (NumLoads > 1)
17701767 return false;
17711768
17721769 // Can we pair these instructions based on their opcodes?
1773 unsigned FirstOpc = FirstLdSt->getOpcode();
1774 unsigned SecondOpc = SecondLdSt->getOpcode();
1770 unsigned FirstOpc = FirstLdSt.getOpcode();
1771 unsigned SecondOpc = SecondLdSt.getOpcode();
17751772 if (!canPairLdStOpc(FirstOpc, SecondOpc))
17761773 return false;
17771774
17821779 return false;
17831780
17841781 // isCandidateToMergeOrPair guarantees that operand 2 is an immediate.
1785 int64_t Offset1 = FirstLdSt->getOperand(2).getImm();
1782 int64_t Offset1 = FirstLdSt.getOperand(2).getImm();
17861783 if (isUnscaledLdSt(FirstOpc) && !scaleOffset(FirstOpc, Offset1))
17871784 return false;
17881785
1789 int64_t Offset2 = SecondLdSt->getOperand(2).getImm();
1786 int64_t Offset2 = SecondLdSt.getOperand(2).getImm();
17901787 if (isUnscaledLdSt(SecondOpc) && !scaleOffset(SecondOpc, Offset2))
17911788 return false;
17921789
17991796 return Offset1 + 1 == Offset2;
18001797 }
18011798
1802 bool AArch64InstrInfo::shouldScheduleAdjacent(MachineInstr *First,
1803 MachineInstr *Second) const {
1799 bool AArch64InstrInfo::shouldScheduleAdjacent(MachineInstr &First,
1800 MachineInstr &Second) const {
18041801 if (Subtarget.hasMacroOpFusion()) {
18051802 // Fuse CMN, CMP, TST followed by Bcc.
1806 unsigned SecondOpcode = Second->getOpcode();
1803 unsigned SecondOpcode = Second.getOpcode();
18071804 if (SecondOpcode == AArch64::Bcc) {
1808 switch (First->getOpcode()) {
1805 switch (First.getOpcode()) {
18091806 default:
18101807 return false;
18111808 case AArch64::SUBSWri:
18201817 // Fuse ALU operations followed by CBZ/CBNZ.
18211818 if (SecondOpcode == AArch64::CBNZW || SecondOpcode == AArch64::CBNZX ||
18221819 SecondOpcode == AArch64::CBZW || SecondOpcode == AArch64::CBZX) {
1823 switch (First->getOpcode()) {
1820 switch (First.getOpcode()) {
18241821 default:
18251822 return false;
18261823 case AArch64::ADDWri:
24472444 }
24482445
24492446 MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
2450 MachineFunction &MF, MachineInstr *MI, ArrayRef Ops,
2447 MachineFunction &MF, MachineInstr &MI, ArrayRef Ops,
24512448 MachineBasicBlock::iterator InsertPt, int FrameIndex,
24522449 LiveIntervals *LIS) const {
24532450 // This is a bit of a hack. Consider this instruction:
24632460 //
24642461 //
24652462 //
2466 if (MI->isCopy()) {
2467 unsigned DstReg = MI->getOperand(0).getReg();
2468 unsigned SrcReg = MI->getOperand(1).getReg();
2463 if (MI.isCopy()) {
2464 unsigned DstReg = MI.getOperand(0).getReg();
2465 unsigned SrcReg = MI.getOperand(1).getReg();
24692466 if (SrcReg == AArch64::SP &&
24702467 TargetRegisterInfo::isVirtualRegister(DstReg)) {
24712468 MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass);
29332930 // When NZCV is live bail out.
29342931 if (Cmp_NZCV == -1)
29352932 return false;
2936 unsigned NewOpc = convertFlagSettingOpcode(&Root);
2933 unsigned NewOpc = convertFlagSettingOpcode(Root);
29372934 // When opcode can't change bail out.
29382935 // CHECKME: do we miss any cases for opcode conversion?
29392936 if (NewOpc == Opc)
38293826 /// \param MI Conditional Branch
38303827 /// \return True when the simple conditional branch is generated
38313828 ///
3832 bool AArch64InstrInfo::optimizeCondBranch(MachineInstr *MI) const {
3829 bool AArch64InstrInfo::optimizeCondBranch(MachineInstr &MI) const {
38333830 bool IsNegativeBranch = false;
38343831 bool IsTestAndBranch = false;
38353832 unsigned TargetBBInMI = 0;
3836 switch (MI->getOpcode()) {
3833 switch (MI.getOpcode()) {
38373834 default:
38383835 llvm_unreachable("Unknown branch instruction?");
38393836 case AArch64::Bcc:
38623859 // So we increment a zero register and test for bits other
38633860 // than bit 0? Conservatively bail out in case the verifier
38643861 // missed this case.
3865 if (IsTestAndBranch && MI->getOperand(1).getImm())
3862 if (IsTestAndBranch && MI.getOperand(1).getImm())
38663863 return false;
38673864
38683865 // Find Definition.
3869 assert(MI->getParent() && "Incomplete machine instruciton\n");
3870 MachineBasicBlock *MBB = MI->getParent();
3866 assert(MI.getParent() && "Incomplete machine instruciton\n");
3867 MachineBasicBlock *MBB = MI.getParent();
38713868 MachineFunction *MF = MBB->getParent();
38723869 MachineRegisterInfo *MRI = &MF->getRegInfo();
3873 unsigned VReg = MI->getOperand(0).getReg();
3870 unsigned VReg = MI.getOperand(0).getReg();
38743871 if (!TargetRegisterInfo::isVirtualRegister(VReg))
38753872 return false;
38763873
39133910 assert(!MRI->def_empty(NewReg) && "Register must be defined.");
39143911
39153912 MachineBasicBlock &RefToMBB = *MBB;
3916 MachineBasicBlock *TBB = MI->getOperand(1).getMBB();
3917 DebugLoc DL = MI->getDebugLoc();
3913 MachineBasicBlock *TBB = MI.getOperand(1).getMBB();
3914 DebugLoc DL = MI.getDebugLoc();
39183915 unsigned Imm = Log2_64(Mask);
39193916 unsigned Opc = (Imm < 32)
39203917 ? (IsNegativeBranch ? AArch64::TBNZW : AArch64::TBZW)
39333930 // 32-bit sub-part.
39343931 if (!Is32Bit && Imm < 32)
39353932 NewMI->getOperand(0).setSubReg(AArch64::sub_32);
3936 MI->eraseFromParent();
3933 MI.eraseFromParent();
39373934 return true;
39383935 }
39393936 // Look for CSINC
39553952 if (areCFlagsAccessedBetweenInstrs(DefMI, MI, &getRegisterInfo(), AK_Write))
39563953 return false;
39573954 MachineBasicBlock &RefToMBB = *MBB;
3958 MachineBasicBlock *TBB = MI->getOperand(TargetBBInMI).getMBB();
3959 DebugLoc DL = MI->getDebugLoc();
3955 MachineBasicBlock *TBB = MI.getOperand(TargetBBInMI).getMBB();
3956 DebugLoc DL = MI.getDebugLoc();
39603957 if (IsNegativeBranch)
39613958 CC = AArch64CC::getInvertedCondCode(CC);
39623959 BuildMI(RefToMBB, MI, DL, get(AArch64::Bcc)).addImm(CC).addMBB(TBB);
3963 MI->eraseFromParent();
3960 MI.eraseFromParent();
39643961 return true;
39653962 }
39663963 }
4444 /// always be able to get register info as well (through this method).
4545 const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
4646
47 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
48
49 bool isAsCheapAsAMove(const MachineInstr *MI) const override;
47 unsigned GetInstSizeInBytes(const MachineInstr &MI) const;
48
49 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
5050
5151 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
5252 unsigned &DstReg, unsigned &SubIdx) const override;
5353
5454 bool
55 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
55 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
5656 AliasAnalysis *AA = nullptr) const override;
5757
58 unsigned isLoadFromStackSlot(const MachineInstr *MI,
58 unsigned isLoadFromStackSlot(const MachineInstr &MI,
5959 int &FrameIndex) const override;
60 unsigned isStoreToStackSlot(const MachineInstr *MI,
60 unsigned isStoreToStackSlot(const MachineInstr &MI,
6161 int &FrameIndex) const override;
6262
6363 /// Returns true if there is a shiftable register and that the shift value
6464 /// is non-zero.
65 bool hasShiftedReg(const MachineInstr *MI) const;
65 bool hasShiftedReg(const MachineInstr &MI) const;
6666
6767 /// Returns true if there is an extendable register and that the extending
6868 /// value is non-zero.
69 bool hasExtendedReg(const MachineInstr *MI) const;
69 bool hasExtendedReg(const MachineInstr &MI) const;
7070
7171 /// \brief Does this instruction set its full destination register to zero?
72 bool isGPRZero(const MachineInstr *MI) const;
72 bool isGPRZero(const MachineInstr &MI) const;
7373
7474 /// \brief Does this instruction rename a GPR without modifying bits?
75 bool isGPRCopy(const MachineInstr *MI) const;
75 bool isGPRCopy(const MachineInstr &MI) const;
7676
7777 /// \brief Does this instruction rename an FPR without modifying bits?
78 bool isFPRCopy(const MachineInstr *MI) const;
78 bool isFPRCopy(const MachineInstr &MI) const;
7979
8080 /// Return true if this is load/store scales or extends its register offset.
8181 /// This refers to scaling a dynamic index as opposed to scaled immediates.
8282 /// MI should be a memory op that allows scaled addressing.
83 bool isScaledAddr(const MachineInstr *MI) const;
83 bool isScaledAddr(const MachineInstr &MI) const;
8484
8585 /// Return true if pairing the given load or store is hinted to be
8686 /// unprofitable.
87 bool isLdStPairSuppressed(const MachineInstr *MI) const;
87 bool isLdStPairSuppressed(const MachineInstr &MI) const;
8888
8989 /// Return true if this is an unscaled load/store.
9090 bool isUnscaledLdSt(unsigned Opc) const;
9191
9292 /// Return true if this is an unscaled load/store.
93 bool isUnscaledLdSt(MachineInstr *MI) const;
93 bool isUnscaledLdSt(MachineInstr &MI) const;
9494
9595 /// Return true if this is a load/store that can be potentially paired/merged.
96 bool isCandidateToMergeOrPair(MachineInstr *MI) const;
96 bool isCandidateToMergeOrPair(MachineInstr &MI) const;
9797
9898 /// Hint that pairing the given load or store is unprofitable.
99 void suppressLdStPair(MachineInstr *MI) const;
100
101 bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
99 void suppressLdStPair(MachineInstr &MI) const;
100
101 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
102102 int64_t &Offset,
103103 const TargetRegisterInfo *TRI) const override;
104104
105 bool getMemOpBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg,
105 bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
106106 int64_t &Offset, unsigned &Width,
107107 const TargetRegisterInfo *TRI) const;
108108
110110
111111 bool enableClusterStores() const override { return true; }
112112
113 bool shouldClusterMemOps(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt,
114 unsigned NumLoads) const override;
115
116 bool shouldScheduleAdjacent(MachineInstr *First,
117 MachineInstr *Second) const override;
113 bool shouldClusterMemOps(MachineInstr &FirstLdSt, MachineInstr &SecondLdSt,
114 unsigned NumLoads) const override;
115
116 bool shouldScheduleAdjacent(MachineInstr &First,
117 MachineInstr &Second) const override;
118118
119119 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
120120 uint64_t Offset, const MDNode *Var,
140140 const TargetRegisterInfo *TRI) const override;
141141
142142 using TargetInstrInfo::foldMemoryOperandImpl;
143 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
144 ArrayRef Ops,
145 MachineBasicBlock::iterator InsertPt,
146 int FrameIndex,
147 LiveIntervals *LIS = nullptr) const override;
143 MachineInstr *
144 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
145 ArrayRef Ops,
146 MachineBasicBlock::iterator InsertPt, int FrameIndex,
147 LiveIntervals *LIS = nullptr) const override;
148148
149149 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
150150 MachineBasicBlock *&FBB,
167167 /// analyzeCompare - For a comparison instruction, return the source registers
168168 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
169169 /// Return true if the comparison instruction can be analyzed.
170 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
170 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
171171 unsigned &SrcReg2, int &CmpMask,
172172 int &CmpValue) const override;
173173 /// optimizeCompareInstr - Convert the instruction supplying the argument to
174174 /// the comparison into one that sets the zero bit in the flags register.
175 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
175 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
176176 unsigned SrcReg2, int CmpMask, int CmpValue,
177177 const MachineRegisterInfo *MRI) const override;
178 bool optimizeCondBranch(MachineInstr *MI) const override;
178 bool optimizeCondBranch(MachineInstr &MI) const override;
179179
180180 /// Return true when a code sequence can improve throughput. It
181181 /// should be called only for instructions in loops.
200200 /// AArch64 supports MachineCombiner.
201201 bool useMachineCombiner() const override;
202202
203 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
203 bool expandPostRAPseudo(MachineInstr &MI) const override;
204204
205205 std::pair
206206 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
213213 void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
214214 MachineBasicBlock *TBB,
215215 ArrayRef Cond) const;
216 bool substituteCmpToZero(MachineInstr *CmpInstr,
217 unsigned SrcReg, const MachineRegisterInfo *MRI) const;
216 bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
217 const MachineRegisterInfo *MRI) const;
218218 };
219219
220220 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
603603 assert(isMatchingStore(LoadInst, StoreInst) && "Expect only matched ld/st.");
604604 int LoadSize = getMemScale(LoadInst);
605605 int StoreSize = getMemScale(StoreInst);
606 int UnscaledStOffset = TII->isUnscaledLdSt(StoreInst)
606 int UnscaledStOffset = TII->isUnscaledLdSt(*StoreInst)
607607 ? getLdStOffsetOp(StoreInst).getImm()
608608 : getLdStOffsetOp(StoreInst).getImm() * StoreSize;
609 int UnscaledLdOffset = TII->isUnscaledLdSt(LoadInst)
609 int UnscaledLdOffset = TII->isUnscaledLdSt(*LoadInst)
610610 ? getLdStOffsetOp(LoadInst).getImm()
611611 : getLdStOffsetOp(LoadInst).getImm() * LoadSize;
612612 return (UnscaledStOffset <= UnscaledLdOffset) &&
962962 // performance and correctness are verified only in little-endian.
963963 if (!Subtarget->isLittleEndian())
964964 return NextI;
965 bool IsUnscaled = TII->isUnscaledLdSt(LoadI);
966 assert(IsUnscaled == TII->isUnscaledLdSt(StoreI) &&
965 bool IsUnscaled = TII->isUnscaledLdSt(*LoadI);
966 assert(IsUnscaled == TII->isUnscaledLdSt(*StoreI) &&
967967 "Unsupported ld/st match");
968968 assert(LoadSize <= StoreSize && "Invalid load size");
969969 int UnscaledLdOffset = IsUnscaled
10711071 return (Num + PowOf2 - 1) & ~(PowOf2 - 1);
10721072 }
10731073
1074 static bool mayAlias(MachineInstr *MIa, MachineInstr *MIb,
1074 static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb,
10751075 const AArch64InstrInfo *TII) {
10761076 // One of the instructions must modify memory.
1077 if (!MIa->mayStore() && !MIb->mayStore())
1077 if (!MIa.mayStore() && !MIb.mayStore())
10781078 return false;
10791079
10801080 // Both instructions must be memory operations.
1081 if (!MIa->mayLoadOrStore() && !MIb->mayLoadOrStore())
1081 if (!MIa.mayLoadOrStore() && !MIb.mayLoadOrStore())
10821082 return false;
10831083
10841084 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb);
10851085 }
10861086
1087 static bool mayAlias(MachineInstr *MIa,
1087 static bool mayAlias(MachineInstr &MIa,
10881088 SmallVectorImpl &MemInsns,
10891089 const AArch64InstrInfo *TII) {
1090 for (auto &MIb : MemInsns)
1091 if (mayAlias(MIa, MIb, TII))
1090 for (MachineInstr *MIb : MemInsns)
1091 if (mayAlias(MIa, *MIb, TII))
10921092 return true;
10931093
10941094 return false;
11451145 return false;
11461146
11471147 // If we encounter a store aliased with the load, return early.
1148 if (MI->mayStore() && mayAlias(LoadMI, MI, TII))
1148 if (MI->mayStore() && mayAlias(*LoadMI, *MI, TII))
11491149 return false;
11501150 } while (MBBI != B && Count < Limit);
11511151 return false;
11571157 LdStPairFlags &Flags,
11581158 const AArch64InstrInfo *TII) {
11591159 // If this is volatile or if pairing is suppressed, not a candidate.
1160 if (MI->hasOrderedMemoryRef() || TII->isLdStPairSuppressed(MI))
1160 if (MI->hasOrderedMemoryRef() || TII->isLdStPairSuppressed(*MI))
11611161 return false;
11621162
11631163 // We should have already checked FirstMI for pair suppression and volatility.
11641164 assert(!FirstMI->hasOrderedMemoryRef() &&
1165 !TII->isLdStPairSuppressed(FirstMI) &&
1165 !TII->isLdStPairSuppressed(*FirstMI) &&
11661166 "FirstMI shouldn't get here if either of these checks are true.");
11671167
11681168 unsigned OpcA = FirstMI->getOpcode();
12111211 ++MBBI;
12121212
12131213 bool MayLoad = FirstMI->mayLoad();
1214 bool IsUnscaled = TII->isUnscaledLdSt(FirstMI);
1214 bool IsUnscaled = TII->isUnscaledLdSt(*FirstMI);
12151215 unsigned Reg = getLdStRegOp(FirstMI).getReg();
12161216 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
12171217 int Offset = getLdStOffsetOp(FirstMI).getImm();
12481248 // a relocation.
12491249 unsigned MIBaseReg = getLdStBaseOp(MI).getReg();
12501250 int MIOffset = getLdStOffsetOp(MI).getImm();
1251 bool MIIsUnscaled = TII->isUnscaledLdSt(MI);
1251 bool MIIsUnscaled = TII->isUnscaledLdSt(*MI);
12521252 if (IsUnscaled != MIIsUnscaled) {
12531253 // We're trying to pair instructions that differ in how they are scaled.
12541254 // If FirstMI is scaled then scale the offset of MI accordingly.
13131313 // first.
13141314 if (!ModifiedRegs[getLdStRegOp(MI).getReg()] &&
13151315 !(MI->mayLoad() && UsedRegs[getLdStRegOp(MI).getReg()]) &&
1316 !mayAlias(MI, MemInsns, TII)) {
1316 !mayAlias(*MI, MemInsns, TII)) {
13171317 Flags.setMergeForward(false);
13181318