llvm.org GIT mirror llvm / 564fbf6
Add all codegen passes to the PassManager via TargetPassConfig. This is a preliminary step toward having TargetPassConfig be able to start and stop the compilation at specified passes for unit testing and debugging. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159567 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 8 years ago
14 changed file(s) with 116 addition(s) and 103 deletion(s). Raw diff Collapse all Expand all
5454 /// optimization after regalloc.
5555 static char PostRAMachineLICMID;
5656
57 private:
58 PassManagerBase *PM;
59
5760 protected:
5861 TargetMachine *TM;
59 PassManagerBase *PM;
6062 PassConfigImpl *Impl; // Internal data structures
6163 bool Initialized; // Flagged after all passes are configured.
6264
120122 /// Add common target configurable passes that perform LLVM IR to IR
121123 /// transforms following machine independent optimization.
122124 virtual void addIRPasses();
125
126 /// Add passes to lower exception handling for the code generator.
127 void addPassesToHandleExceptions();
123128
124129 /// Add common passes that perform LLVM IR to IR transforms in preparation for
125130 /// instruction selection.
234239 /// Return the pass that was added, or NoPassID.
235240 AnalysisID addPass(char &ID);
236241
242 /// Add a pass to the PassManager.
243 void addPass(Pass *P);
244
237245 /// addMachinePasses helper to create the target-selected or overriden
238246 /// regalloc pass.
239247 FunctionPass *createRegAllocPass(bool Optimized);
241249 /// printAndVerify - Add a pass to dump then verify the machine function, if
242250 /// those steps are enabled.
243251 ///
244 void printAndVerify(const char *Banner) const;
252 void printAndVerify(const char *Banner);
245253 };
246254 } // namespace llvm
247255
7777 "and that InitializeAllTargetMCs() is being invoked!");
7878 }
7979
80 /// Turn exception handling constructs into something the code generators can
81 /// handle.
82 static void addPassesToHandleExceptions(TargetMachine *TM,
83 PassManagerBase &PM) {
84 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
85 case ExceptionHandling::SjLj:
86 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
87 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
88 // catch info can get misplaced when a selector ends up more than one block
89 // removed from the parent invoke(s). This could happen when a landing
90 // pad is shared by multiple invokes and is also a target of a normal
91 // edge from elsewhere.
92 PM.add(createSjLjEHPreparePass(TM->getTargetLowering()));
93 // FALLTHROUGH
94 case ExceptionHandling::DwarfCFI:
95 case ExceptionHandling::ARM:
96 case ExceptionHandling::Win64:
97 PM.add(createDwarfEHPass(TM));
98 break;
99 case ExceptionHandling::None:
100 PM.add(createLowerInvokePass(TM->getTargetLowering()));
101
102 // The lower invoke pass may create unreachable code. Remove it.
103 PM.add(createUnreachableBlockEliminationPass());
104 break;
105 }
106 }
107
10880 /// addPassesToX helper drives creation and initialization of TargetPassConfig.
10981 static MCContext *addPassesToGenerateCode(LLVMTargetMachine *TM,
11082 PassManagerBase &PM,
11991
12092 PassConfig->addIRPasses();
12193
122 addPassesToHandleExceptions(TM, PM);
94 PassConfig->addPassesToHandleExceptions();
12395
12496 PassConfig->addISelPrepare();
12597
2121 #include "llvm/CodeGen/RegAllocRegistry.h"
2222 #include "llvm/Target/TargetLowering.h"
2323 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/MC/MCAsmInfo.h"
2425 #include "llvm/Assembly/PrintModulePass.h"
2526 #include "llvm/Support/CommandLine.h"
2627 #include "llvm/Support/Debug.h"
214215 // Out of line constructor provides default values for pass options and
215216 // registers all common codegen passes.
216217 TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
217 : ImmutablePass(ID), TM(tm), PM(&pm), Impl(0), Initialized(false),
218 : ImmutablePass(ID), PM(&pm), TM(tm), Impl(0), Initialized(false),
218219 DisableVerify(false),
219220 EnableTailMerge(true) {
220221
271272 return I->second;
272273 }
273274
275 /// Add a pass to the PassManager.
276 void TargetPassConfig::addPass(Pass *P) {
277 PM->add(P);
278 }
279
274280 /// Add a CodeGen pass at this point in the pipeline after checking for target
275281 /// and command line overrides.
276282 AnalysisID TargetPassConfig::addPass(char &ID) {
284290 Pass *P = Pass::createPass(FinalID);
285291 if (!P)
286292 llvm_unreachable("Pass ID not registered");
287 PM->add(P);
293 addPass(P);
288294 // Add the passes after the pass P if there is any.
289295 for (SmallVector, 4>::iterator
290296 I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end();
293299 assert((*I).second && "Illegal Pass ID!");
294300 Pass *NP = Pass::createPass((*I).second);
295301 assert(NP && "Pass ID not registered");
296 PM->add(NP);
302 addPass(NP);
297303 }
298304 }
299305 return FinalID;
300306 }
301307
302 void TargetPassConfig::printAndVerify(const char *Banner) const {
308 void TargetPassConfig::printAndVerify(const char *Banner) {
303309 if (TM->shouldPrintMachineCode())
304 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
310 addPass(createMachineFunctionPrinterPass(dbgs(), Banner));
305311
306312 if (VerifyMachineCode)
307 PM->add(createMachineVerifierPass(Banner));
313 addPass(createMachineVerifierPass(Banner));
308314 }
309315
310316 /// Add common target configurable passes that perform LLVM IR to IR transforms
314320 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
315321 // BasicAliasAnalysis wins if they disagree. This is intended to help
316322 // support "obvious" type-punning idioms.
317 PM->add(createTypeBasedAliasAnalysisPass());
318 PM->add(createBasicAliasAnalysisPass());
323 addPass(createTypeBasedAliasAnalysisPass());
324 addPass(createBasicAliasAnalysisPass());
319325
320326 // Before running any passes, run the verifier to determine if the input
321327 // coming from the front-end and/or optimizer is valid.
322328 if (!DisableVerify)
323 PM->add(createVerifierPass());
329 addPass(createVerifierPass());
324330
325331 // Run loop strength reduction before anything else.
326332 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
327 PM->add(createLoopStrengthReducePass(getTargetLowering()));
333 addPass(createLoopStrengthReducePass(getTargetLowering()));
328334 if (PrintLSR)
329 PM->add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
330 }
331
332 PM->add(createGCLoweringPass());
335 addPass(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
336 }
337
338 addPass(createGCLoweringPass());
333339
334340 // Make sure that no unreachable blocks are instruction selected.
335 PM->add(createUnreachableBlockEliminationPass());
341 addPass(createUnreachableBlockEliminationPass());
342 }
343
344 /// Turn exception handling constructs into something the code generators can
345 /// handle.
346 void TargetPassConfig::addPassesToHandleExceptions() {
347 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
348 case ExceptionHandling::SjLj:
349 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
350 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
351 // catch info can get misplaced when a selector ends up more than one block
352 // removed from the parent invoke(s). This could happen when a landing
353 // pad is shared by multiple invokes and is also a target of a normal
354 // edge from elsewhere.
355 addPass(createSjLjEHPreparePass(TM->getTargetLowering()));
356 // FALLTHROUGH
357 case ExceptionHandling::DwarfCFI:
358 case ExceptionHandling::ARM:
359 case ExceptionHandling::Win64:
360 addPass(createDwarfEHPass(TM));
361 break;
362 case ExceptionHandling::None:
363 addPass(createLowerInvokePass(TM->getTargetLowering()));
364
365 // The lower invoke pass may create unreachable code. Remove it.
366 addPass(createUnreachableBlockEliminationPass());
367 break;
368 }
336369 }
337370
338371 /// Add common passes that perform LLVM IR to IR transforms in preparation for
339372 /// instruction selection.
340373 void TargetPassConfig::addISelPrepare() {
341374 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
342 PM->add(createCodeGenPreparePass(getTargetLowering()));
343
344 PM->add(createStackProtectorPass(getTargetLowering()));
375 addPass(createCodeGenPreparePass(getTargetLowering()));
376
377 addPass(createStackProtectorPass(getTargetLowering()));
345378
346379 addPreISel();
347380
348381 if (PrintISelInput)
349 PM->add(createPrintFunctionPass("\n\n"
382 addPass(createPrintFunctionPass("\n\n"
350383 "*** Final LLVM Code input to ISel ***\n",
351384 &dbgs()));
352385
353386 // All passes which modify the LLVM IR are now complete; run the verifier
354387 // to ensure that the IR is valid.
355388 if (!DisableVerify)
356 PM->add(createVerifierPass());
389 addPass(createVerifierPass());
357390 }
358391
359392 /// Add the complete set of target-independent postISel code generator passes.
446479 // GC
447480 addPass(GCMachineCodeAnalysisID);
448481 if (PrintGCInfo)
449 PM->add(createGCInfoPrinter(dbgs()));
482 addPass(createGCInfoPrinter(dbgs()));
450483
451484 // Basic block placement.
452485 if (getOptLevel() != CodeGenOpt::None)
563596 addPass(PHIEliminationID);
564597 addPass(TwoAddressInstructionPassID);
565598
566 PM->add(RegAllocPass);
599 addPass(RegAllocPass);
567600 printAndVerify("After Register Allocation");
568601 }
569602
601634 printAndVerify("After Machine Scheduling");
602635
603636 // Add the selected register allocation pass.
604 PM->add(RegAllocPass);
637 addPass(RegAllocPass);
605638 printAndVerify("After Register Allocation, before rewriter");
606639
607640 // Allow targets to change the register assignments before rewriting.
135135
136136 bool ARMPassConfig::addPreISel() {
137137 if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
138 PM->add(createGlobalMergePass(TM->getTargetLowering()));
138 addPass(createGlobalMergePass(TM->getTargetLowering()));
139139
140140 return false;
141141 }
142142
143143 bool ARMPassConfig::addInstSelector() {
144 PM->add(createARMISelDag(getARMTargetMachine(), getOptLevel()));
144 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
145145 return false;
146146 }
147147
148148 bool ARMPassConfig::addPreRegAlloc() {
149149 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
150150 if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
151 PM->add(createARMLoadStoreOptimizationPass(true));
151 addPass(createARMLoadStoreOptimizationPass(true));
152152 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
153 PM->add(createMLxExpansionPass());
153 addPass(createMLxExpansionPass());
154154 return true;
155155 }
156156
158158 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
159159 if (getOptLevel() != CodeGenOpt::None) {
160160 if (!getARMSubtarget().isThumb1Only()) {
161 PM->add(createARMLoadStoreOptimizationPass());
161 addPass(createARMLoadStoreOptimizationPass());
162162 printAndVerify("After ARM load / store optimizer");
163163 }
164164 if (getARMSubtarget().hasNEON())
165 PM->add(createExecutionDependencyFixPass(&ARM::DPRRegClass));
165 addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
166166 }
167167
168168 // Expand some pseudo instructions into multiple instructions to allow
169169 // proper scheduling.
170 PM->add(createARMExpandPseudoPass());
170 addPass(createARMExpandPseudoPass());
171171
172172 if (getOptLevel() != CodeGenOpt::None) {
173173 if (!getARMSubtarget().isThumb1Only())
174174 addPass(IfConverterID);
175175 }
176176 if (getARMSubtarget().isThumb2())
177 PM->add(createThumb2ITBlockPass());
177 addPass(createThumb2ITBlockPass());
178178
179179 return true;
180180 }
182182 bool ARMPassConfig::addPreEmitPass() {
183183 if (getARMSubtarget().isThumb2()) {
184184 if (!getARMSubtarget().prefers32BitThumb())
185 PM->add(createThumb2SizeReductionPass());
185 addPass(createThumb2SizeReductionPass());
186186
187187 // Constant island pass work on unbundled instructions.
188188 addPass(UnpackMachineBundlesID);
189189 }
190190
191 PM->add(createARMConstantIslandPass());
191 addPass(createARMConstantIslandPass());
192192
193193 return true;
194194 }
7171
7272 bool SPUPassConfig::addInstSelector() {
7373 // Install an instruction selector.
74 PM->add(createSPUISelDag(getSPUTargetMachine()));
74 addPass(createSPUISelDag(getSPUTargetMachine()));
7575 return false;
7676 }
7777
8484 (BuilderFunc)(intptr_t)sys::DynamicLibrary::SearchForAddressOfSymbol(
8585 "createTCESchedulerPass");
8686 if (schedulerCreator != NULL)
87 PM->add(schedulerCreator("cellspu"));
87 addPass(schedulerCreator("cellspu"));
8888
8989 //align instructions with nops/lnops for dual issue
90 PM->add(createSPUNopFillerPass(getSPUTargetMachine()));
90 addPass(createSPUNopFillerPass(getSPUTargetMachine()));
9191 return true;
9292 }
101101 }
102102
103103 bool HexagonPassConfig::addInstSelector() {
104 PM->add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
105 PM->add(createHexagonISelDag(getHexagonTargetMachine()));
106 PM->add(createHexagonPeephole());
104 addPass(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
105 addPass(createHexagonISelDag(getHexagonTargetMachine()));
106 addPass(createHexagonPeephole());
107107 return false;
108108 }
109109
110110
111111 bool HexagonPassConfig::addPreRegAlloc() {
112112 if (!DisableHardwareLoops) {
113 PM->add(createHexagonHardwareLoops());
113 addPass(createHexagonHardwareLoops());
114114 }
115115 return false;
116116 }
117117
118118 bool HexagonPassConfig::addPostRegAlloc() {
119 PM->add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
119 addPass(createHexagonCFGOptimizer(getHexagonTargetMachine()));
120120 return true;
121121 }
122122
129129 bool HexagonPassConfig::addPreEmitPass() {
130130
131131 if (!DisableHardwareLoops) {
132 PM->add(createHexagonFixupHwLoops());
132 addPass(createHexagonFixupHwLoops());
133133 }
134134
135 PM->add(createHexagonNewValueJump());
135 addPass(createHexagonNewValueJump());
136136
137137 // Expand Spill code for predicate registers.
138 PM->add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
138 addPass(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
139139
140140 // Split up TFRcondsets into conditional transfers.
141 PM->add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
141 addPass(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
142142
143143 // Create Packets.
144 PM->add(createHexagonPacketizer());
144 addPass(createHexagonPacketizer());
145145
146146 return false;
147147 }
6767 // Install an instruction selector pass using
6868 // the ISelDag to gen MBlaze code.
6969 bool MBlazePassConfig::addInstSelector() {
70 PM->add(createMBlazeISelDag(getMBlazeTargetMachine()));
70 addPass(createMBlazeISelDag(getMBlazeTargetMachine()));
7171 return false;
7272 }
7373
7575 // machine code is emitted. return true if -print-machineinstrs should
7676 // print out the code after the passes.
7777 bool MBlazePassConfig::addPreEmitPass() {
78 PM->add(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine()));
78 addPass(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine()));
7979 return true;
8080 }
5959
6060 bool MSP430PassConfig::addInstSelector() {
6161 // Install an instruction selector.
62 PM->add(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
62 addPass(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
6363 return false;
6464 }
6565
6666 bool MSP430PassConfig::addPreEmitPass() {
6767 // Must run branch selection immediately preceding the asm printer.
68 PM->add(createMSP430BranchSelectionPass());
68 addPass(createMSP430BranchSelectionPass());
6969 return false;
7070 }
115115 // Install an instruction selector pass using
116116 // the ISelDag to gen Mips code.
117117 bool MipsPassConfig::addInstSelector() {
118 PM->add(createMipsISelDag(getMipsTargetMachine()));
118 addPass(createMipsISelDag(getMipsTargetMachine()));
119119 return false;
120120 }
121121
124124 // print out the code after the passes.
125125 bool MipsPassConfig::addPreEmitPass() {
126126 MipsTargetMachine &TM = getMipsTargetMachine();
127 PM->add(createMipsDelaySlotFillerPass(TM));
127 addPass(createMipsDelaySlotFillerPass(TM));
128128
129129 // NOTE: long branch has not been implemented for mips16.
130130 if (TM.getSubtarget().hasStandardEncoding())
131 PM->add(createMipsLongBranchPass(TM));
131 addPass(createMipsLongBranchPass(TM));
132132
133133 return true;
134134 }
119119 }
120120
121121 bool NVPTXPassConfig::addInstSelector() {
122 PM->add(createLowerAggrCopies());
123 PM->add(createSplitBBatBarPass());
124 PM->add(createAllocaHoisting());
125 PM->add(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
126 PM->add(createVectorElementizePass(getNVPTXTargetMachine()));
122 addPass(createLowerAggrCopies());
123 addPass(createSplitBBatBarPass());
124 addPass(createAllocaHoisting());
125 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
126 addPass(createVectorElementizePass(getNVPTXTargetMachine()));
127127 return false;
128128 }
129129
9797
9898 bool PPCPassConfig::addPreRegAlloc() {
9999 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
100 PM->add(createPPCCTRLoops());
100 addPass(createPPCCTRLoops());
101101
102102 return false;
103103 }
104104
105105 bool PPCPassConfig::addInstSelector() {
106106 // Install an instruction selector.
107 PM->add(createPPCISelDag(getPPCTargetMachine()));
107 addPass(createPPCISelDag(getPPCTargetMachine()));
108108 return false;
109109 }
110110
111111 bool PPCPassConfig::addPreEmitPass() {
112112 // Must run branch selection immediately preceding the asm printer.
113 PM->add(createPPCBranchSelectionPass());
113 addPass(createPPCBranchSelectionPass());
114114 return false;
115115 }
116116
5959 }
6060
6161 bool SparcPassConfig::addInstSelector() {
62 PM->add(createSparcISelDag(getSparcTargetMachine()));
62 addPass(createSparcISelDag(getSparcTargetMachine()));
6363 return false;
6464 }
6565
6767 /// passes immediately before machine code is emitted. This should return
6868 /// true if -print-machineinstrs should print out the code after the passes.
6969 bool SparcPassConfig::addPreEmitPass(){
70 PM->add(createSparcFPMoverPass(getSparcTargetMachine()));
71 PM->add(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
70 addPass(createSparcFPMoverPass(getSparcTargetMachine()));
71 addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
7272 return true;
7373 }
7474
144144
145145 bool X86PassConfig::addInstSelector() {
146146 // Install an instruction selector.
147 PM->add(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
147 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
148148
149149 // For ELF, cleanup any local-dynamic TLS accesses.
150150 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
151 PM->add(createCleanupLocalDynamicTLSPass());
151 addPass(createCleanupLocalDynamicTLSPass());
152152
153153 // For 32-bit, prepend instructions to set the "global base reg" for PIC.
154154 if (!getX86Subtarget().is64Bit())
155 PM->add(createGlobalBaseRegPass());
155 addPass(createGlobalBaseRegPass());
156156
157157 return false;
158158 }
159159
160160 bool X86PassConfig::addPreRegAlloc() {
161 PM->add(createX86MaxStackAlignmentHeuristicPass());
161 addPass(createX86MaxStackAlignmentHeuristicPass());
162162 return false; // -print-machineinstr shouldn't print after this.
163163 }
164164
165165 bool X86PassConfig::addPostRegAlloc() {
166 PM->add(createX86FloatingPointStackifierPass());
166 addPass(createX86FloatingPointStackifierPass());
167167 return true; // -print-machineinstr should print after this.
168168 }
169169
170170 bool X86PassConfig::addPreEmitPass() {
171171 bool ShouldPrint = false;
172172 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
173 PM->add(createExecutionDependencyFixPass(&X86::VR128RegClass));
173 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
174174 ShouldPrint = true;
175175 }
176176
177177 if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
178 PM->add(createX86IssueVZeroUpperPass());
178 addPass(createX86IssueVZeroUpperPass());
179179 ShouldPrint = true;
180180 }
181181
5454 }
5555
5656 bool XCorePassConfig::addInstSelector() {
57 PM->add(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
57 addPass(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
5858 return false;
5959 }
6060