llvm.org GIT mirror llvm / 561fa2f
Revert "ARM: sort register lists by encoding in push/pop instructions." This reverts commit 286866. It broke a bot, something to do with exactly which templates std::sort accepts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286867 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 3 years ago
4 changed file(s) with 6 addition(s) and 32 deletion(s). Raw diff Collapse all Expand all
892892 unsigned MIFlags) const {
893893 MachineFunction &MF = *MBB.getParent();
894894 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
895 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
896895
897896 DebugLoc DL;
898897
899 typedef std::pair RegAndKill;
900 SmallVector<RegAndKill, 4> Regs;
898 SmallVector<std::pair, 4> Regs;
901899 unsigned i = CSI.size();
902900 while (i != 0) {
903901 unsigned LastReg = 0;
928926
929927 if (Regs.empty())
930928 continue;
931
932 std::sort(Regs.begin(), Regs.end(), [&](RegAndKill &LHS, RegAndKill &RHS) {
933 return TRI.getEncodingValue(LHS.first) < TRI.getEncodingValue(RHS.first);
934 });
935
936929 if (Regs.size() > 1 || StrOpc== 0) {
937930 MachineInstrBuilder MIB =
938931 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
966959 unsigned NumAlignedDPRCS2Regs) const {
967960 MachineFunction &MF = *MBB.getParent();
968961 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
969 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
970962 ARMFunctionInfo *AFI = MF.getInfo();
971963 DebugLoc DL;
972964 bool isTailCall = false;
10191011
10201012 if (Regs.empty())
10211013 continue;
1022
1023 std::sort(Regs.begin(), Regs.end(), [&](unsigned &LHS, unsigned &RHS) {
1024 return TRI.getEncodingValue(LHS) < TRI.getEncodingValue(RHS);
1025 });
1026
10271014 if (Regs.size() > 1 || LdrOpc == 0) {
10281015 MachineInstrBuilder MIB =
10291016 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
725725 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
726726 const MCSubtargetInfo &STI,
727727 raw_ostream &O) {
728 assert(std::is_sorted(MI->begin() + OpNum, MI->end(),
729 [&](const MCOperand &LHS, const MCOperand &RHS) {
730 return MRI.getEncodingValue(LHS.getReg()) <
731 MRI.getEncodingValue(RHS.getReg());
732 }));
733
734728 O << "{";
735729 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
736730 if (i != OpNum)
15441544 else
15451545 Binary |= NumRegs * 2;
15461546 } else {
1547 const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
1548 assert(std::is_sorted(MI.begin() + Op, MI.end(),
1549 [&](const MCOperand &LHS, const MCOperand &RHS) {
1550 return MRI.getEncodingValue(LHS.getReg()) <
1551 MRI.getEncodingValue(RHS.getReg());
1552 }));
1553
15541547 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1555 unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
1548 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
15561549 Binary |= 1 << RegNo;
15571550 }
15581551 }
414414
415415 ; CHECK-ARMV7-LABEL: _params_in_reg
416416 ; Store callee saved registers excluding swifterror.
417 ; CHECK-ARMV7: push {r4, r5, r7, r8, r10, r11, lr}
417 ; CHECK-ARMV7: push {r8, r10, r11, r4, r5, r7, lr}
418418 ; Store swiftself (r10) and swifterror (r6).
419419 ; CHECK-ARMV7-DAG: str r6, [s[[STK1:.*]]]
420420 ; CHECK-ARMV7-DAG: str r10, [s[[STK2:.*]]]
439439 ; CHECK-ARMV7: mov r2, r5
440440 ; CHECK-ARMV7: mov r3, r4
441441 ; CHECK-ARMV7: bl _params_in_reg2
442 ; CHECK-ARMV7: pop {r4, r5, r7, r8, r10, r11, pc}
442 ; CHECK-ARMV7: pop {r8, r10, r11, r4, r5, r7, pc}
443443 define swiftcc void @params_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
444444 %error_ptr_ref = alloca swifterror %swift_error*, align 8
445445 store %swift_error* null, %swift_error** %error_ptr_ref
450450 declare swiftcc void @params_in_reg2(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err)
451451
452452 ; CHECK-ARMV7-LABEL: params_and_return_in_reg
453 ; CHECK-ARMV7: push {r4, r5, r7, r8, r10, r11, lr}
453 ; CHECK-ARMV7: push {r8, r10, r11, r4, r5, r7, lr}
454454 ; Store swifterror and swiftself
455455 ; CHECK-ARMV7: mov r4, r6
456456 ; CHECK-ARMV7: str r10, [s[[STK1:.*]]]
501501 ; CHECK-ARMV7: mov r1, r4
502502 ; CHECK-ARMV7: mov r2, r8
503503 ; CHECK-ARMV7: mov r3, r11
504 ; CHECK-ARMV7: pop {r4, r5, r7, r8, r10, r11, pc}
504 ; CHECK-ARMV7: pop {r8, r10, r11, r4, r5, r7, pc}
505505 define swiftcc { i32, i32, i32, i32} @params_and_return_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
506506 %error_ptr_ref = alloca swifterror %swift_error*, align 8
507507 store %swift_error* null, %swift_error** %error_ptr_ref