llvm.org GIT mirror llvm / 55c0268
Reduce the size of MCRelaxableFragment. MCRelaxableFragment previously kept a copy of MCSubtargetInfo and MCInst to enable re-encoding the MCInst later during relaxation. A copy of MCSubtargetInfo (instead of a reference or pointer) was needed because the feature bits could be modified by the parser. This commit replaces the MCSubtargetInfo copy in MCRelaxableFragment with a constant reference to MCSubtargetInfo. The copies of MCSubtargetInfo are kept in MCContext, and the target parsers are now responsible for asking MCContext to provide a copy whenever the feature bits of MCSubtargetInfo have to be toggled. With this patch, I saw a 4% reduction in peak memory usage when I compiled verify-uselistorder.lto.bc using llc. rdar://problem/21736951 Differential Revision: http://reviews.llvm.org/D14346 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253127 91177308-0d34-0410-b5e6-96231b3b80d8 Akira Hatanaka 4 years ago
19 changed file(s) with 75 addition(s) and 47 deletion(s). Raw diff Collapse all Expand all
265265 MCInst Inst;
266266
267267 /// STI - The MCSubtargetInfo in effect when the instruction was encoded.
268 /// Keep a copy instead of a reference to make sure that updates to STI
269 /// in the assembler are not seen here.
270 const MCSubtargetInfo STI;
268 const MCSubtargetInfo &STI;
271269
272270 public:
273271 MCRelaxableFragment(const MCInst &Inst, const MCSubtargetInfo &STI,
1616 #include "llvm/ADT/StringMap.h"
1717 #include "llvm/ADT/Twine.h"
1818 #include "llvm/MC/MCDwarf.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
1920 #include "llvm/MC/SectionKind.h"
2021 #include "llvm/Support/Allocator.h"
2122 #include "llvm/Support/Compiler.h"
206207 std::map COFFUniquingMap;
207208 StringMap ELFRelSecNames;
208209
210 SpecificBumpPtrAllocator MCSubtargetAllocator;
211
209212 /// Do automatic reset in destructor
210213 bool AutoReset;
211214
378381 /// as Sec and the function symbol as KeySym.
379382 MCSectionCOFF *getAssociativeCOFFSection(MCSectionCOFF *Sec,
380383 const MCSymbol *KeySym);
384
385 // Create and save a copy of STI and return a reference to the copy.
386 MCSubtargetInfo &getSubtargetCopy(const MCSubtargetInfo &STI);
381387
382388 /// @}
383389
9292 MCTargetAsmParser(const MCTargetAsmParser &) = delete;
9393 void operator=(const MCTargetAsmParser &) = delete;
9494 protected: // Can only create subclasses.
95 MCTargetAsmParser(MCTargetOptions const &, MCSubtargetInfo &STI);
95 MCTargetAsmParser(MCTargetOptions const &, const MCSubtargetInfo &STI);
96
97 /// Create a copy of STI and return a non-const reference to it.
98 MCSubtargetInfo ©STI();
9699
97100 /// AvailableFeatures - The current set of available features.
98101 uint64_t AvailableFeatures;
108111 MCTargetOptions MCOptions;
109112
110113 /// Current STI.
111 MCSubtargetInfo &STI;
114 const MCSubtargetInfo *STI;
112115
113116 public:
114117 ~MCTargetAsmParser() override;
114114 const MCRegisterInfo &MRI,
115115 const Triple &TT, StringRef CPU);
116116 typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(
117 MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
117 const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
118118 const MCTargetOptions &Options);
119119 typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T,
120120 const MCSubtargetInfo &STI,
381381 ///
382382 /// \param Parser The target independent parser implementation to use for
383383 /// parsing and lexing.
384 MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI,
384 MCTargetAsmParser *createMCAsmParser(const MCSubtargetInfo &STI,
385385 MCAsmParser &Parser,
386386 const MCInstrInfo &MII,
387387 const MCTargetOptions &Options) const {
11321132 }
11331133
11341134 private:
1135 static MCTargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &P,
1136 const MCInstrInfo &MII,
1135 static MCTargetAsmParser *Allocator(const MCSubtargetInfo &STI,
1136 MCAsmParser &P, const MCInstrInfo &MII,
11371137 const MCTargetOptions &Options) {
11381138 return new MCAsmParserImpl(STI, P, MII, Options);
11391139 }
234234 TM.getTargetFeatureString()));
235235 OutStreamer->AddComment("Start of file scope inline assembly");
236236 OutStreamer->AddBlankLine();
237 EmitInlineAsm(M.getModuleInlineAsm()+"\n", *STI, TM.Options.MCOptions);
237 EmitInlineAsm(M.getModuleInlineAsm()+"\n",
238 OutContext.getSubtargetCopy(*STI), TM.Options.MCOptions);
238239 OutStreamer->AddComment("End of file scope inline assembly");
239240 OutStreamer->AddBlankLine();
240241 }
126126 std::unique_ptr Parser(
127127 createMCAsmParser(SrcMgr, OutContext, *OutStreamer, *MAI));
128128
129 // Create a temporary copy of the original STI because the parser may modify
130 // it. For example, when switching between arm and thumb mode. If the target
131 // needs to emit code to return to the original state it can do so in
132 // emitInlineAsmEnd().
133 MCSubtargetInfo TmpSTI = STI;
134
135129 // We create a new MCInstrInfo here since we might be at the module level
136130 // and not have a MachineFunction to initialize the TargetInstrInfo from and
137131 // we only need MCInstrInfo for asm parsing. We create one unconditionally
138132 // because it's not subtarget dependent.
139133 std::unique_ptr MII(TM.getTarget().createMCInstrInfo());
140134 std::unique_ptr TAP(TM.getTarget().createMCAsmParser(
141 TmpSTI, *Parser, *MII, MCOptions));
135 STI, *Parser, *MII, MCOptions));
142136 if (!TAP)
143137 report_fatal_error("Inline asm not supported by this streamer because"
144138 " we don't have an asm parser for this target\n");
153147 // Don't implicitly switch to the text section before the asm.
154148 int Res = Parser->Run(/*NoInitialTextSection*/ true,
155149 /*NoFinalize*/ true);
156 emitInlineAsmEnd(STI, &TmpSTI);
150 emitInlineAsmEnd(STI, &TAP->getSTI());
157151 if (Res && !HasDiagHandler)
158152 report_fatal_error("Error parsing inline asm\n");
159153 }
7777 ELFAllocator.DestroyAll();
7878 MachOAllocator.DestroyAll();
7979
80 MCSubtargetAllocator.DestroyAll();
8081 UsedNames.clear();
8182 Symbols.clear();
8283 SectionSymbols.clear();
438439 COFF::IMAGE_COMDAT_SELECT_ASSOCIATIVE);
439440 }
440441
442 MCSubtargetInfo &MCContext::getSubtargetCopy(const MCSubtargetInfo &STI) {
443 return *new (MCSubtargetAllocator.Allocate()) MCSubtargetInfo(STI);
444 }
445
441446 //===----------------------------------------------------------------------===//
442447 // Dwarf Management
443448 //===----------------------------------------------------------------------===//
1111 using namespace llvm;
1212
1313 MCTargetAsmParser::MCTargetAsmParser(MCTargetOptions const &MCOptions,
14 MCSubtargetInfo &STI)
14 const MCSubtargetInfo &STI)
1515 : AvailableFeatures(0), ParsingInlineAsm(false), MCOptions(MCOptions),
16 STI(STI)
16 STI(&STI)
1717 {
1818 }
1919
2020 MCTargetAsmParser::~MCTargetAsmParser() {
2121 }
2222
23 MCSubtargetInfo &MCTargetAsmParser::copySTI() {
24 MCSubtargetInfo &STICopy = getContext().getSubtargetCopy(getSTI());
25 STI = &STICopy;
26 return STICopy;
27 }
28
2329 const MCSubtargetInfo &MCTargetAsmParser::getSTI() const {
24 return STI;
30 return *STI;
2531 }
113113 #define GET_OPERAND_DIAGNOSTIC_TYPES
114114 #include "AArch64GenAsmMatcher.inc"
115115 };
116 AArch64AsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser,
116 AArch64AsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
117117 const MCInstrInfo &MII, const MCTargetOptions &Options)
118118 : MCTargetAsmParser(Options, STI) {
119119 MCAsmParserExtension::Initialize(Parser);
363363 Match_PreferE32 = FIRST_TARGET_MATCH_RESULT_TY
364364 };
365365
366 AMDGPUAsmParser(MCSubtargetInfo &STI, MCAsmParser &_Parser,
366 AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
367367 const MCInstrInfo &MII,
368368 const MCTargetOptions &Options)
369369 : MCTargetAsmParser(Options, STI), MII(MII), Parser(_Parser),
370370 ForcedEncodingSize(0) {
371 MCAsmParserExtension::Initialize(Parser);
372
371373 if (getSTI().getFeatureBits().none()) {
372374 // Set default features.
373 STI.ToggleFeature("SOUTHERN_ISLANDS");
375 copySTI().ToggleFeature("SOUTHERN_ISLANDS");
374376 }
375377
376378 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
282282 }
283283
284284 void SwitchMode() {
285 MCSubtargetInfo &STI = copySTI();
285286 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
286287 setAvailableFeatures(FB);
287288 }
347348
348349 };
349350
350 ARMAsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser,
351 ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
351352 const MCInstrInfo &MII, const MCTargetOptions &Options)
352353 : MCTargetAsmParser(Options, STI), MII(MII), UC(Parser) {
353354 MCAsmParserExtension::Initialize(Parser);
90379038 }
90389039
90399040 Triple T;
9041 MCSubtargetInfo &STI = copySTI();
90409042 STI.setDefaultFeatures(T.getARMCPUForArch(Arch));
90419043 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
90429044
91699171 return false;
91709172 }
91719173
9174 MCSubtargetInfo &STI = copySTI();
91729175 STI.setDefaultFeatures(CPU);
91739176 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
91749177
91879190 return false;
91889191 }
91899192
9193 MCSubtargetInfo &STI = copySTI();
91909194 for (auto Feature : Features)
91919195 STI.ApplyFeatureFlag(Feature);
91929196 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
99679971 return false;
99689972 }
99699973
9974 MCSubtargetInfo &STI = copySTI();
99709975 FeatureBitset ToggleFeatures = EnableFeature
99719976 ? (~STI.getFeatureBits() & Extension.Features)
99729977 : ( STI.getFeatureBits() & Extension.Features);
132132 /// }
133133
134134 public:
135 HexagonAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
135 HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser,
136136 const MCInstrInfo &MII, const MCTargetOptions &Options)
137137 : MCTargetAsmParser(Options, _STI), Parser(_Parser),
138138 MCII (MII), MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) {
345345 // FeatureMipsGP64 | FeatureMips1)
346346 // Clearing Mips3 is equivalent to clear (FeatureMips3 | FeatureMips4).
347347 void selectArch(StringRef ArchFeature) {
348 MCSubtargetInfo &STI = copySTI();
348349 FeatureBitset FeatureBits = STI.getFeatureBits();
349350 FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask;
350351 STI.setFeatureBits(FeatureBits);
355356
356357 void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
357358 if (!(getSTI().getFeatureBits()[Feature])) {
359 MCSubtargetInfo &STI = copySTI();
358360 setAvailableFeatures(
359361 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
360362 AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
363365
364366 void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
365367 if (getSTI().getFeatureBits()[Feature]) {
368 MCSubtargetInfo &STI = copySTI();
366369 setAvailableFeatures(
367370 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
368371 AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
387390 #undef GET_OPERAND_DIAGNOSTIC_TYPES
388391 };
389392
390 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
393 MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
391394 const MCInstrInfo &MII, const MCTargetOptions &Options)
392395 : MCTargetAsmParser(Options, sti),
393396 ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()),
47454748 if (AssemblerOptions.size() == 2)
47464749 return reportParseError(Loc, ".set pop with no .set push");
47474750
4751 MCSubtargetInfo &STI = copySTI();
47484752 AssemblerOptions.pop_back();
47494753 setAvailableFeatures(
47504754 ComputeAvailableFeatures(AssemblerOptions.back()->getFeatures()));
48184822 return reportParseError("unexpected token, expected end of statement");
48194823
48204824 // Reset assembler options to their initial values.
4825 MCSubtargetInfo &STI = copySTI();
48214826 setAvailableFeatures(
48224827 ComputeAvailableFeatures(AssemblerOptions.front()->getFeatures()));
48234828 STI.setFeatureBits(AssemblerOptions.front()->getFeatures());
289289
290290
291291 public:
292 PPCAsmParser(MCSubtargetInfo &STI, MCAsmParser &,
292 PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
293293 const MCInstrInfo &MII, const MCTargetOptions &Options)
294294 : MCTargetAsmParser(Options, STI), MII(MII) {
295295 // Check for 64-bit vs. 32-bit pointer mode.
8787 SmallVectorImpl &Instructions);
8888
8989 public:
90 SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
90 SparcAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
9191 const MCInstrInfo &MII,
9292 const MCTargetOptions &Options)
9393 : MCTargetAsmParser(Options, sti), Parser(parser) {
384384 bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
385385
386386 public:
387 SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
387 SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
388388 const MCInstrInfo &MII,
389389 const MCTargetOptions &Options)
390390 : MCTargetAsmParser(Options, sti), Parser(parser) {
181181 std::vector BusyRegs;
182182 };
183183
184 X86AddressSanitizer(const MCSubtargetInfo &STI)
184 X86AddressSanitizer(const MCSubtargetInfo *&STI)
185185 : X86AsmInstrumentation(STI), RepPrefix(false), OrigSPOffset(0) {}
186186
187187 ~X86AddressSanitizer() override {}
260260 MCContext &Ctx, int64_t *Residue);
261261
262262 bool is64BitMode() const {
263 return STI.getFeatureBits()[X86::Mode64Bit];
263 return STI->getFeatureBits()[X86::Mode64Bit];
264264 }
265265 bool is32BitMode() const {
266 return STI.getFeatureBits()[X86::Mode32Bit];
266 return STI->getFeatureBits()[X86::Mode32Bit];
267267 }
268268 bool is16BitMode() const {
269 return STI.getFeatureBits()[X86::Mode16Bit];
269 return STI->getFeatureBits()[X86::Mode16Bit];
270270 }
271271
272272 unsigned getPointerWidth() {
502502 public:
503503 static const long kShadowOffset = 0x20000000;
504504
505 X86AddressSanitizer32(const MCSubtargetInfo &STI)
505 X86AddressSanitizer32(const MCSubtargetInfo *&STI)
506506 : X86AddressSanitizer(STI) {}
507507
508508 ~X86AddressSanitizer32() override {}
759759 public:
760760 static const long kShadowOffset = 0x7fff8000;
761761
762 X86AddressSanitizer64(const MCSubtargetInfo &STI)
762 X86AddressSanitizer64(const MCSubtargetInfo *&STI)
763763 : X86AddressSanitizer(STI) {}
764764
765765 ~X86AddressSanitizer64() override {}
10291029
10301030 } // End anonymous namespace
10311031
1032 X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo &STI)
1032 X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo *&STI)
10331033 : STI(STI), InitialFrameReg(0) {}
10341034
10351035 X86AsmInstrumentation::~X86AsmInstrumentation() {}
10421042
10431043 void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out,
10441044 const MCInst &Inst) {
1045 Out.EmitInstruction(Inst, STI);
1045 Out.EmitInstruction(Inst, *STI);
10461046 }
10471047
10481048 unsigned X86AsmInstrumentation::GetFrameRegGeneric(const MCContext &Ctx,
10661066
10671067 X86AsmInstrumentation *
10681068 CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
1069 const MCContext &Ctx, const MCSubtargetInfo &STI) {
1070 Triple T(STI.getTargetTriple());
1069 const MCContext &Ctx, const MCSubtargetInfo *&STI) {
1070 Triple T(STI->getTargetTriple());
10711071 const bool hasCompilerRTSupport = T.isOSLinux();
10721072 if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
10731073 MCOptions.SanitizeAddress) {
1074 if (STI.getFeatureBits()[X86::Mode32Bit] != 0)
1074 if (STI->getFeatureBits()[X86::Mode32Bit] != 0)
10751075 return new X86AddressSanitizer32(STI);
1076 if (STI.getFeatureBits()[X86::Mode64Bit] != 0)
1076 if (STI->getFeatureBits()[X86::Mode64Bit] != 0)
10771077 return new X86AddressSanitizer64(STI);
10781078 }
10791079 return new X86AsmInstrumentation(STI);
2727
2828 X86AsmInstrumentation *
2929 CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
30 const MCContext &Ctx, const MCSubtargetInfo &STI);
30 const MCContext &Ctx,
31 const MCSubtargetInfo *&STI);
3132
3233 class X86AsmInstrumentation {
3334 public:
4748 protected:
4849 friend X86AsmInstrumentation *
4950 CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
50 const MCContext &Ctx, const MCSubtargetInfo &STI);
51 const MCContext &Ctx,
52 const MCSubtargetInfo *&STI);
5153
52 X86AsmInstrumentation(const MCSubtargetInfo &STI);
54 X86AsmInstrumentation(const MCSubtargetInfo *&STI);
5355
5456 unsigned GetFrameRegGeneric(const MCContext &Ctx, MCStreamer &Out);
5557
5658 void EmitInstruction(MCStreamer &Out, const MCInst &Inst);
5759
58 const MCSubtargetInfo &STI;
60 const MCSubtargetInfo *&STI;
5961
6062 unsigned InitialFrameReg;
6163 };
769769 return getSTI().getFeatureBits()[X86::Mode16Bit];
770770 }
771771 void SwitchMode(unsigned mode) {
772 MCSubtargetInfo &STI = copySTI();
772773 FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
773774 FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
774775 unsigned FB = ComputeAvailableFeatures(
798799 /// }
799800
800801 public:
801 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &Parser,
802 X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
802803 const MCInstrInfo &mii, const MCTargetOptions &Options)
803804 : MCTargetAsmParser(Options, sti), MII(mii), InstInfo(nullptr) {
804805