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Merging r243984: ------------------------------------------------------------------------ r243984 | vkalintiris | 2015-08-04 07:26:35 -0700 (Tue, 04 Aug 2015) | 11 lines Revert r229675 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions. It introduced two regressions on 64-bit big-endian targets running under N32 (MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4, and MultiSource/Applications/kimwitu++/kc) The issue is that on 64-bit targets comparisons such as BEQ compare the whole GPR64 but incorrectly tell the instruction selector that they operate on GPR32's. This leads to the elimination of i32->i64 extensions that are actually required by comparisons to work correctly. There's currently a patch under review that fixes this problem. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@244096 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 5 years ago
5 changed file(s) with 15 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
498498 (EXTRACT_SUBREG GPR64:$src, sub_32)>;
499499 def : MipsPat<(i32 (trunc GPR64:$src)),
500500 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
501
502 // Bypass trunc nodes for bitwise ops.
503 def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))),
504 (EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
505 def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))),
506 (EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
507 def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))),
508 (EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
509501
510502 // variable shift instructions patterns
511503 def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))),
0 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s
1 ; We have to XFAIL this temporarily because of the reversion of r229675.
2 ; XFAIL: *
13
24 ; Currently, the following IR assembly generates a KILL instruction between
35 ; the bitwise-and instruction and the return instruction. We verify that the
5858 entry:
5959 ; ALL-LABEL: and_i32:
6060
61 ; ALL: and $2, $4, $5
61 ; GP32: and $2, $4, $5
62
63 ; GP64: and $[[T0:[0-9]+]], $4, $5
64 ; GP64: sll $2, $[[T0]], 0
6265
6366 %r = and i32 %a, %b
6467 ret i32 %r
5858 entry:
5959 ; ALL-LABEL: or_i32:
6060
61 ; ALL: or $2, $4, $5
61 ; GP32: or $2, $4, $5
62
63 ; GP64: or $[[T0:[0-9]+]], $4, $5
64 ; FIXME: The sll instruction below is redundant.
65 ; GP64: sll $2, $[[T0]], 0
6266
6367 %r = or i32 %a, %b
6468 ret i32 %r
5858 entry:
5959 ; ALL-LABEL: xor_i32:
6060
61 ; ALL: xor $2, $4, $5
61 ; GP32: xor $2, $4, $5
62
63 ; GP64: xor $[[T0:[0-9]+]], $4, $5
64 ; GP64: sll $2, $[[T0]], 0
6265
6366 %r = xor i32 %a, %b
6467 ret i32 %r