llvm.org GIT mirror llvm / 5548755
Make the 'x' constraint work for AVX registers as well. Fixes rdar://10614894 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147704 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 8 years ago
2 changed file(s) with 22 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
1509715097 break;
1509815098 case 'x':
1509915099 case 'Y':
15100 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
15100 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM()) ||
15101 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
1510115102 weight = CW_Register;
1510215103 break;
1510315104 case 'I':
1537715378 case 'Y': // SSE_REGS if SSE2 allowed
1537815379 if (!Subtarget->hasXMMInt()) break;
1537915380 // FALL THROUGH.
15380 case 'x': // SSE_REGS if SSE1 allowed
15381 if (!Subtarget->hasXMM()) break;
15381 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15382 if (!Subtarget->hasXMM() && !Subtarget->hasAVX()) break;
1538215383
1538315384 switch (VT.getSimpleVT().SimpleTy) {
1538415385 default: break;
1539715398 case MVT::v4f32:
1539815399 case MVT::v2f64:
1539915400 return std::make_pair(0U, X86::VR128RegisterClass);
15401 // AVX types.
15402 case MVT::v32i8:
15403 case MVT::v16i16:
15404 case MVT::v8i32:
15405 case MVT::v4i64:
15406 case MVT::v8f32:
15407 case MVT::v4f64:
15408 return std::make_pair(0U, X86::VR256RegisterClass);
15409
1540015410 }
1540115411 break;
1540215412 }
None ; RUN: llc < %s -march=x86-64
0 ; RUN: llc < %s -march=x86-64 -mattr=+avx
11 ; rdar://7066579
22
33 %0 = type { i64, i64, i64, i64, i64 } ; type %0
2626 %0 = tail call { i8, i8, i8, i8, i8 } asm "foo $1, $2, $3, $4, $1\0Axchgb ${0:b}, ${0:h}", "=q,={ax},={bx},={cx},={dx},0,1,2,3,4,~{dirflag},~{fpsr},~{flags}"(i8 %val, i8 %a, i8 %b, i8 %c, i8 %d) nounwind
2727 ret void
2828 }
29
30 ; rdar://10614894
31 define <8 x float> @test5(<8 x float> %a, <8 x float> %b) nounwind {
32 entry:
33 %0 = tail call <8 x float> asm "vperm2f128 $3, $2, $1, $0", "=x,x,x,i,~{dirflag},~{fpsr},~{flags}"(<8 x float> %a, <8 x float> %b, i32 16) nounwind
34 ret <8 x float> %0
35 }
36