llvm.org GIT mirror llvm / 54e4c36
Rewrite the SDep class, and simplify some of the related code. The Cost field is removed. It was only being used in a very limited way, to indicate when the scheduler should attempt to protect a live register, and it isn't really needed to do that. If we ever want the scheduler to start inserting copies in non-prohibitive situations, we'll have to rethink some things anyway. A Latency field is added. Instead of giving each node a single fixed latency, each edge can have its own latency. This will eventually be used to model various micro-architecture properties more accurately. The PointerIntPair class and an internal union are now used, which reduce the overall size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60806 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 11 years ago
12 changed file(s) with 537 addition(s) and 387 deletion(s). Raw diff Collapse all Expand all
1919 #include "llvm/ADT/BitVector.h"
2020 #include "llvm/ADT/GraphTraits.h"
2121 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/PointerIntPair.h"
2223
2324 namespace llvm {
2425 struct SUnit;
3839 class TargetRegisterClass;
3940 template class GraphWriter;
4041
41 /// SDep - Scheduling dependency. It keeps track of dependent nodes,
42 /// cost of the depdenency, etc.
43 struct SDep {
44 SUnit *Dep; // Dependent - either a predecessor or a successor.
45 unsigned Reg; // If non-zero, this dep is a physreg dependency.
46 int Cost; // Cost of the dependency.
47 bool isCtrl : 1; // True iff it's a control dependency.
48 bool isArtificial : 1; // True iff it's an artificial ctrl dep added
49 // during sched that may be safely deleted if
50 // necessary.
51 bool isAntiDep : 1; // True iff it's an anti-dependency (on a physical
52 // register.
53 SDep(SUnit *d, unsigned r, int t, bool c, bool a, bool anti)
54 : Dep(d), Reg(r), Cost(t), isCtrl(c), isArtificial(a), isAntiDep(anti) {}
42 /// SDep - Scheduling dependency. This represents one direction of an
43 /// edge in the scheduling DAG.
44 class SDep {
45 public:
46 /// Kind - These are the different kinds of scheduling dependencies.
47 enum Kind {
48 Data, ///< Regular data dependence (aka true-dependence).
49 Anti, ///< A register anti-dependedence (aka WAR).
50 Output, ///< A register output-dependence (aka WAW).
51 Order ///< Any other ordering dependency.
52 };
53
54 private:
55 /// Dep - A pointer to the depending/depended-on SUnit, and an enum
56 /// indicating the kind of the dependency.
57 PointerIntPair Dep;
58
59 /// Contents - A union discriminated by the dependence kind.
60 union {
61 /// Reg - For Data, Anti, and Output dependencies, the associated
62 /// register. For Data dependencies that don't currently have a register
63 /// assigned, this is set to zero.
64 unsigned Reg;
65
66 /// Order - Additional information about Order dependencies.
67 struct {
68 /// isNormalMemory - True if both sides of the dependence
69 /// access memory in non-volatile and fully modeled ways.
70 bool isNormalMemory : 1;
71
72 /// isMustAlias - True if both sides of the dependence are known to
73 /// access the same memory.
74 bool isMustAlias : 1;
75
76 /// isArtificial - True if this is an artificial dependency, meaning
77 /// it is not necessary for program correctness, and may be safely
78 /// deleted if necessary.
79 bool isArtificial : 1;
80 } Order;
81 } Contents;
82
83 /// Latency - The time associated with this edge. Often this is just
84 /// the value of the Latency field of the predecessor, however advanced
85 /// models may provide additional information about specific edges.
86 unsigned Latency;
87
88 public:
89 /// SDep - Construct a null SDep. This is only for use by container
90 /// classes which require default constructors. SUnits may not
91 /// have null SDep edges.
92 SDep() : Dep(0, Data) {}
93
94 /// SDep - Construct an SDep with the specified values.
95 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0,
96 bool isNormalMemory = false, bool isMustAlias = false,
97 bool isArtificial = false)
98 : Dep(S, kind), Contents(), Latency(latency) {
99 switch (kind) {
100 case Anti:
101 case Output:
102 assert(Reg != 0 &&
103 "SDep::Anti and SDep::Output must use a non-zero Reg!");
104 // fall through
105 case Data:
106 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
107 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
108 Contents.Reg = Reg;
109 break;
110 case Order:
111 assert(Reg == 0 && "Reg given for non-register dependence!");
112 Contents.Order.isNormalMemory = isNormalMemory;
113 Contents.Order.isMustAlias = isMustAlias;
114 Contents.Order.isArtificial = isArtificial;
115 break;
116 }
117 }
118
119 bool operator==(const SDep &Other) const {
120 if (Dep != Other.Dep) return false;
121 switch (Dep.getInt()) {
122 case Data:
123 case Anti:
124 case Output:
125 return Contents.Reg == Other.Contents.Reg;
126 case Order:
127 return Contents.Order.isNormalMemory ==
128 Other.Contents.Order.isNormalMemory &&
129 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias &&
130 Contents.Order.isArtificial == Other.Contents.Order.isArtificial;
131 }
132 assert(0 && "Invalid dependency kind!");
133 return false;
134 }
135
136 bool operator!=(const SDep &Other) const {
137 return !operator==(Other);
138 }
139
140 /// getLatency - Return the latency value for this edge, which roughly
141 /// means the minimum number of cycles that must elapse between the
142 /// predecessor and the successor, given that they have this edge
143 /// between them.
144 unsigned getLatency() const {
145 return Latency;
146 }
147
148 //// getSUnit - Return the SUnit to which this edge points.
149 SUnit *getSUnit() const {
150 return Dep.getPointer();
151 }
152
153 //// setSUnit - Assign the SUnit to which this edge points.
154 void setSUnit(SUnit *SU) {
155 Dep.setPointer(SU);
156 }
157
158 /// getKind - Return an enum value representing the kind of the dependence.
159 Kind getKind() const {
160 return Dep.getInt();
161 }
162
163 /// isCtrl - Shorthand for getKind() != SDep::Data.
164 bool isCtrl() const {
165 return getKind() != Data;
166 }
167
168 /// isArtificial - Test if this is an Order dependence that is marked
169 /// as "artificial", meaning it isn't necessary for correctness.
170 bool isArtificial() const {
171 return getKind() == Order && Contents.Order.isArtificial;
172 }
173
174 /// isMustAlias - Test if this is an Order dependence that is marked
175 /// as "must alias", meaning that the SUnits at either end of the edge
176 /// have a memory dependence on a known memory location.
177 bool isMustAlias() const {
178 return getKind() == Order && Contents.Order.isMustAlias;
179 }
180
181 /// isAssignedRegDep - Test if this is a Data dependence that is
182 /// associated with a register.
183 bool isAssignedRegDep() const {
184 return getKind() == Data && Contents.Reg != 0;
185 }
186
187 /// getReg - Return the register associated with this edge. This is
188 /// only valid on Data, Anti, and Output edges. On Data edges, this
189 /// value may be zero, meaning there is no associated register.
190 unsigned getReg() const {
191 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
192 "getReg called on non-register dependence edge!");
193 return Contents.Reg;
194 }
195
196 /// setReg - Assign the associated register for this edge. This is
197 /// only valid on Data, Anti, and Output edges. On Anti and Output
198 /// edges, this value must not be zero. On Data edges, the value may
199 /// be zero, which would mean that no specific register is associated
200 /// with this edge.
201 void setReg(unsigned Reg) {
202 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
203 "setReg called on non-register dependence edge!");
204 assert((getKind() != Anti || Reg != 0) &&
205 "SDep::Anti edge cannot use the zero register!");
206 assert((getKind() != Output || Reg != 0) &&
207 "SDep::Output edge cannot use the zero register!");
208 Contents.Reg = Reg;
209 }
55210 };
56211
57212 /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
76231 unsigned NodeNum; // Entry # of node in the node vector.
77232 unsigned NodeQueueId; // Queue id of node.
78233 unsigned short Latency; // Node latency.
79 short NumPreds; // # of non-control preds.
80 short NumSuccs; // # of non-control sucss.
234 short NumPreds; // # of SDep::Data preds.
235 short NumSuccs; // # of SDep::Data sucss.
81236 short NumPredsLeft; // # of preds not scheduled.
82237 short NumSuccsLeft; // # of succs not scheduled.
83238 bool isTwoAddress : 1; // Is a two-address instruction.
141296 return Instr;
142297 }
143298
144 /// addPred - This adds the specified node as a pred of the current node if
299 /// addPred - This adds the specified edge as a pred of the current node if
145300 /// not already. It also adds the current node as a successor of the
146301 /// specified node. This returns true if this is a new pred.
147 bool addPred(SUnit *N, bool isCtrl, bool isArtificial,
148 unsigned PhyReg = 0, int Cost = 1, bool isAntiDep = false) {
302 bool addPred(const SDep &D) {
303 // If this node already has this depenence, don't add a redundant one.
149304 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
150 if (Preds[i].Dep == N &&
151 Preds[i].isCtrl == isCtrl &&
152 Preds[i].isArtificial == isArtificial &&
153 Preds[i].isAntiDep == isAntiDep)
305 if (Preds[i] == D)
154306 return false;
155 Preds.push_back(SDep(N, PhyReg, Cost, isCtrl, isArtificial, isAntiDep));
156 N->Succs.push_back(SDep(this, PhyReg, Cost, isCtrl,
157 isArtificial, isAntiDep));
158 if (!isCtrl) {
307 // Add a pred to this SUnit.
308 Preds.push_back(D);
309 // Now add a corresponding succ to N.
310 SDep P = D;
311 P.setSUnit(this);
312 SUnit *N = D.getSUnit();
313 N->Succs.push_back(P);
314 // Update the bookkeeping.
315 if (D.getKind() == SDep::Data) {
159316 ++NumPreds;
160317 ++N->NumSuccs;
161318 }
166323 return true;
167324 }
168325
169 bool removePred(SUnit *N, bool isCtrl, bool isArtificial, bool isAntiDep) {
326 /// removePred - This removes the specified edge as a pred of the current
327 /// node if it exists. It also removes the current node as a successor of
328 /// the specified node. This returns true if the edge existed and was
329 /// removed.
330 bool removePred(const SDep &D) {
331 // Find the matching predecessor.
170332 for (SmallVector::iterator I = Preds.begin(), E = Preds.end();
171333 I != E; ++I)
172 if (I->Dep == N &&
173 I->isCtrl == isCtrl &&
174 I->isArtificial == isArtificial &&
175 I->isAntiDep == isAntiDep) {
334 if (*I == D) {
176335 bool FoundSucc = false;
336 // Find the corresponding successor in N.
337 SDep P = D;
338 P.setSUnit(this);
339 SUnit *N = D.getSUnit();
177340 for (SmallVector::iterator II = N->Succs.begin(),
178341 EE = N->Succs.end(); II != EE; ++II)
179 if (II->Dep == this &&
180 II->isCtrl == isCtrl && II->isArtificial == isArtificial &&
181 II->isAntiDep == isAntiDep) {
342 if (*II == P) {
182343 FoundSucc = true;
183344 N->Succs.erase(II);
184345 break;
185346 }
186347 assert(FoundSucc && "Mismatching preds / succs lists!");
187348 Preds.erase(I);
188 if (!isCtrl) {
349 // Update the bookkeeping;
350 if (D.getKind() == SDep::Data) {
189351 --NumPreds;
190352 --N->NumSuccs;
191353 }
200362
201363 bool isPred(SUnit *N) {
202364 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
203 if (Preds[i].Dep == N)
365 if (Preds[i].getSUnit() == N)
204366 return true;
205367 return false;
206368 }
207369
208370 bool isSucc(SUnit *N) {
209371 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
210 if (Succs[i].Dep == N)
372 if (Succs[i].getSUnit() == N)
211373 return true;
212374 return false;
213375 }
365527 }
366528
367529 pointer operator*() const {
368 return Node->Preds[Operand].Dep;
530 return Node->Preds[Operand].getSUnit();
369531 }
370532 pointer operator->() const { return operator*(); }
371533
384546
385547 unsigned getOperand() const { return Operand; }
386548 const SUnit *getNode() const { return Node; }
387 bool isCtrlDep() const { return Node->Preds[Operand].isCtrl; }
388 bool isArtificialDep() const { return Node->Preds[Operand].isArtificial; }
549 /// isCtrlDep - Test if this is not an SDep::Data dependence.
550 bool isCtrlDep() const {
551 return Node->Preds[Operand].isCtrl();
552 }
553 bool isArtificialDep() const {
554 return Node->Preds[Operand].isArtificial();
555 }
389556 };
390557
391558 template <> struct GraphTraits {
1717 #include "llvm/CodeGen/ScheduleDAG.h"
1818
1919 namespace llvm {
20 struct SUnit;
21 class MachineConstantPool;
22 class MachineFunction;
23 class MachineModuleInfo;
24 class MachineRegisterInfo;
25 class MachineInstr;
26 class TargetRegisterInfo;
27 class ScheduleDAG;
28 class SelectionDAG;
29 class SelectionDAGISel;
30 class TargetInstrInfo;
31 class TargetInstrDesc;
32 class TargetLowering;
33 class TargetMachine;
34 class TargetRegisterClass;
35
3620 class ScheduleDAGInstrs : public ScheduleDAG {
3721 public:
3822 ScheduleDAGInstrs(MachineBasicBlock *bb,
1919 #include "llvm/ADT/SmallSet.h"
2020
2121 namespace llvm {
22 struct SUnit;
23 class MachineConstantPool;
24 class MachineFunction;
25 class MachineModuleInfo;
26 class MachineRegisterInfo;
27 class MachineInstr;
28 class TargetRegisterInfo;
29 class ScheduleDAG;
30 class SelectionDAG;
31 class SelectionDAGISel;
32 class TargetInstrInfo;
33 class TargetInstrDesc;
34 class TargetLowering;
35 class TargetMachine;
36 class TargetRegisterClass;
37
3822 /// HazardRecognizer - This determines whether or not an instruction can be
3923 /// issued this cycle, and whether or not a noop needs to be inserted to handle
4024 /// the hazard.
5656 unsigned MaxSuccLatency = 0;
5757 for (SUnit::const_succ_iterator I = Cur->Succs.begin(),E = Cur->Succs.end();
5858 I != E; ++I) {
59 int SuccLatency = Latencies[I->Dep->NodeNum];
59 int SuccLatency = Latencies[I->getSUnit()->NodeNum];
6060 if (SuccLatency == -1) {
6161 AllDone = false;
62 WorkList.push_back(I->Dep);
62 WorkList.push_back(I->getSUnit());
6363 } else {
6464 // This assumes that there's no delay for reusing registers.
65 unsigned NewLatency =
66 SuccLatency + ((I->isCtrl && I->Reg != 0) ? 1 : CurLatency);
65 unsigned NewLatency = SuccLatency + CurLatency;
6766 MaxSuccLatency = std::max(MaxSuccLatency, NewLatency);
6867 }
6968 }
9897 Latency = SU->Latency + SuccLat;
9998 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
10099 I != E; ++I)
101 WorkList.push_back(std::make_pair(I->Dep, Latency));
100 WorkList.push_back(std::make_pair(I->getSUnit(), Latency));
102101 }
103102 }
104103 }
109108 SUnit *OnlyAvailablePred = 0;
110109 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
111110 I != E; ++I) {
112 SUnit &Pred = *I->Dep;
111 SUnit &Pred = *I->getSUnit();
113112 if (!Pred.isScheduled) {
114113 // We found an available, but not scheduled, predecessor. If it's the
115114 // only one we have found, keep track of it... otherwise give up.
128127 unsigned NumNodesBlocking = 0;
129128 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
130129 I != E; ++I)
131 if (getSingleUnscheduledPred(I->Dep) == SU)
130 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
132131 ++NumNodesBlocking;
133132 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking;
134133
143142 void LatencyPriorityQueue::ScheduledNode(SUnit *SU) {
144143 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
145144 I != E; ++I)
146 AdjustPriorityOfUnscheduledPreds(I->Dep);
145 AdjustPriorityOfUnscheduledPreds(I->getSUnit());
147146 }
148147
149148 /// AdjustPriorityOfUnscheduledPreds - One of the predecessors of SU was just
7777 void Schedule();
7878
7979 private:
80 void ReleaseSucc(SUnit *SU, SUnit *SuccSU, bool isChain);
80 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
8181 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
8282 void ListScheduleTopDown();
8383 bool BreakAntiDependencies();
159159 SUnit *SU = &SUnits[*I];
160160 for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
161161 P != PE; ++P) {
162 SUnit *PredSU = P->Dep;
162 SUnit *PredSU = P->getSUnit();
163163 // This assumes that there's no delay for reusing registers.
164 unsigned PredLatency = (P->isCtrl && P->Reg != 0) ? 1 : PredSU->Latency;
164 unsigned PredLatency = P->getLatency();
165165 unsigned PredTotalLatency = PredSU->CycleBound + PredLatency;
166166 if (SU->CycleBound < PredTotalLatency ||
167 (SU->CycleBound == PredTotalLatency && !P->isAntiDep)) {
167 (SU->CycleBound == PredTotalLatency &&
168 P->getKind() == SDep::Anti)) {
168169 SU->CycleBound = PredTotalLatency;
169170 CriticalPath[*I] = &*P;
170171 }
194195 BitVector AllocatableSet = TRI->getAllocatableSet(*MF);
195196 DenseMap CriticalAntiDeps;
196197 for (SUnit *SU = Max; CriticalPath[SU->NodeNum];
197 SU = CriticalPath[SU->NodeNum]->Dep) {
198 SU = CriticalPath[SU->NodeNum]->getSUnit()) {
198199 SDep *Edge = CriticalPath[SU->NodeNum];
199 SUnit *NextSU = Edge->Dep;
200 unsigned AntiDepReg = Edge->Reg;
200 SUnit *NextSU = Edge->getSUnit();
201201 // Only consider anti-dependence edges.
202 if (!Edge->isAntiDep)
202 if (Edge->getKind() != SDep::Anti)
203203 continue;
204 unsigned AntiDepReg = Edge->getReg();
204205 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
205206 // Don't break anti-dependencies on non-allocatable registers.
206207 if (!AllocatableSet.test(AntiDepReg))
212213 // break it.
213214 for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
214215 P != PE; ++P)
215 if (P->Dep == NextSU ?
216 (!P->isAntiDep || P->Reg != AntiDepReg) :
217 (!P->isCtrl && !P->isAntiDep && P->Reg == AntiDepReg)) {
216 if (P->getSUnit() == NextSU ?
217 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
218 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
218219 AntiDepReg = 0;
219220 break;
220221 }
538539
539540 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
540541 /// the PendingQueue if the count reaches zero. Also update its cycle bound.
541 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SUnit *SuccSU, bool isChain) {
542 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
543 SUnit *SuccSU = SuccEdge->getSUnit();
542544 --SuccSU->NumPredsLeft;
543545
544546 #ifndef NDEBUG
553555 // Compute how many cycles it will be before this actually becomes
554556 // available. This is the max of the start time of all predecessors plus
555557 // their latencies.
556 // If this is a token edge, we don't need to wait for the latency of the
557 // preceeding instruction (e.g. a long-latency load) unless there is also
558 // some other data dependence.
559 unsigned PredDoneCycle = SU->Cycle;
560 if (!isChain)
561 PredDoneCycle += SU->Latency;
562 else if (SU->Latency)
563 PredDoneCycle += 1;
558 unsigned PredDoneCycle = SU->Cycle + SuccEdge->getLatency();
564559 SuccSU->CycleBound = std::max(SuccSU->CycleBound, PredDoneCycle);
565560
566561 if (SuccSU->NumPredsLeft == 0) {
581576 // Top down: release successors.
582577 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
583578 I != E; ++I)
584 ReleaseSucc(SU, I->Dep, I->isCtrl);
579 ReleaseSucc(SU, &*I);
585580
586581 SU->isScheduled = true;
587582 AvailableQueue.ScheduledNode(SU);
615610 PendingQueue.pop_back();
616611 --i; --e;
617612 } else {
618 assert(PendingQueue[i]->CycleBound > CurCycle && "Negative latency?");
613 assert(PendingQueue[i]->CycleBound > CurCycle && "Non-positive latency?");
619614 }
620615 }
621616
6666 // So, just iterate over all predecessors and take the longest path
6767 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
6868 I != E; ++I) {
69 unsigned PredDepth = I->Dep->Depth;
69 unsigned PredDepth = I->getSUnit()->Depth;
7070 if (PredDepth+1 > SUDepth) {
7171 SUDepth = PredDepth + 1;
7272 }
7777 // Update degrees of all nodes depending on current SUnit
7878 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
7979 I != E; ++I) {
80 SUnit *SU = I->Dep;
80 SUnit *SU = I->getSUnit();
8181 if (!--SU->Depth)
8282 // If all dependencies of the node are processed already,
8383 // then the longest path for the node can be computed now
121121 // So, just iterate over all successors and take the longest path
122122 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
123123 I != E; ++I) {
124 unsigned SuccHeight = I->Dep->Height;
124 unsigned SuccHeight = I->getSUnit()->Height;
125125 if (SuccHeight+1 > SUHeight) {
126126 SUHeight = SuccHeight + 1;
127127 }
132132 // Update degrees of all nodes depending on current SUnit
133133 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
134134 I != E; ++I) {
135 SUnit *SU = I->Dep;
135 SUnit *SU = I->getSUnit();
136136 if (!--SU->Height)
137137 // If all dependencies of the node are processed already,
138138 // then the longest path for the node can be computed now
182182 cerr << " Predecessors:\n";
183183 for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
184184 I != E; ++I) {
185 if (I->isCtrl)
186 cerr << " ch #";
187 else
188 cerr << " val #";
189 cerr << I->Dep << " - SU(" << I->Dep->NodeNum << ")";
190 if (I->isArtificial)
185 cerr << " ";
186 switch (I->getKind()) {
187 case SDep::Data: cerr << "val "; break;
188 case SDep::Anti: cerr << "anti"; break;
189 case SDep::Output: cerr << "out "; break;
190 case SDep::Order: cerr << "ch "; break;
191 }
192 cerr << "#";
193 cerr << I->getSUnit() << " - SU(" << I->getSUnit()->NodeNum << ")";
194 if (I->isArtificial())
191195 cerr << " *";
192196 cerr << "\n";
193197 }
196200 cerr << " Successors:\n";
197201 for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
198202 I != E; ++I) {
199 if (I->isCtrl)
200 cerr << " ch #";
201 else
202 cerr << " val #";
203 cerr << I->Dep << " - SU(" << I->Dep->NodeNum << ")";
204 if (I->isArtificial)
203 cerr << " ";
204 switch (I->getKind()) {
205 case SDep::Data: cerr << "val "; break;
206 case SDep::Anti: cerr << "anti"; break;
207 case SDep::Output: cerr << "out "; break;
208 case SDep::Order: cerr << "ch "; break;
209 }
210 cerr << "#";
211 cerr << I->getSUnit() << " - SU(" << I->getSUnit()->NodeNum << ")";
212 if (I->isArtificial())
205213 cerr << " *";
206214 cerr << "\n";
207215 }
323331 Allocate(SU->NodeNum, --Id);
324332 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
325333 I != E; ++I) {
326 SUnit *SU = I->Dep;
334 SUnit *SU = I->getSUnit();
327335 if (!--Node2Index[SU->NodeNum])
328336 // If all dependencies of the node are processed already,
329337 // then the node can be computed now.
339347 SUnit *SU = &SUnits[i];
340348 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
341349 I != E; ++I) {
342 assert(Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] &&
350 assert(Node2Index[SU->NodeNum] > Node2Index[I->getSUnit()->NodeNum] &&
343351 "Wrong topological sorting");
344352 }
345353 }
385393 WorkList.pop_back();
386394 Visited.set(SU->NodeNum);
387395 for (int I = SU->Succs.size()-1; I >= 0; --I) {
388 int s = SU->Succs[I].Dep->NodeNum;
396 int s = SU->Succs[I].getSUnit()->NodeNum;
389397 if (Node2Index[s] == UpperBound) {
390398 HasLoop = true;
391399 return;
392400 }
393401 // Visit successors if not already and in affected region.
394402 if (!Visited.test(s) && Node2Index[s] < UpperBound) {
395 WorkList.push_back(SU->Succs[I].Dep);
403 WorkList.push_back(SU->Succs[I].getSUnit());
396404 }
397405 }
398406 }
433441 return true;
434442 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
435443 I != E; ++I)
436 if (I->Cost < 0 && IsReachable(TargetSU, I->Dep))
444 if (I->isAssignedRegDep() &&
445 IsReachable(TargetSU, I->getSUnit()))
437446 return true;
438447 return false;
439448 }
3939 DenseMap &VRBaseMap) {
4040 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
4141 I != E; ++I) {
42 if (I->isCtrl) continue; // ignore chain preds
43 if (I->Dep->CopyDstRC) {
42 if (I->isCtrl()) continue; // ignore chain preds
43 if (I->getSUnit()->CopyDstRC) {
4444 // Copy to physical register.
45 DenseMap::iterator VRI = VRBaseMap.find(I->Dep);
45 DenseMap::iterator VRI = VRBaseMap.find(I->getSUnit());
4646 assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
4747 // Find the destination physical register.
4848 unsigned Reg = 0;
4949 for (SUnit::const_succ_iterator II = SU->Succs.begin(),
5050 EE = SU->Succs.end(); II != EE; ++II) {
51 if (I->Reg) {
52 Reg = I->Reg;
51 if (I->getReg()) {
52 Reg = I->getReg();
5353 break;
5454 }
5555 }
56 assert(I->Reg && "Unknown physical register!");
56 assert(I->getReg() && "Unknown physical register!");
5757 TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
5858 SU->CopyDstRC, SU->CopySrcRC);
5959 } else {
6060 // Copy from physical register.
61 assert(I->Reg && "Unknown physical register!");
61 assert(I->getReg() && "Unknown physical register!");
6262 unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
6363 bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
6464 isNew = isNew; // Silence compiler warning.
6565 assert(isNew && "Node emitted out of order - early");
66 TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
66 TII->copyRegToReg(*BB, BB->end(), VRBase, I->getReg(),
6767 SU->CopyDstRC, SU->CopySrcRC);
6868 }
6969 break;
2929 void ScheduleDAGInstrs::BuildSchedUnits() {
3030 SUnits.clear();
3131 SUnits.reserve(BB->size());
32 int Cost = 1; // FIXME
3332
3433 // We build scheduling units by walking a block's instruction list from bottom
3534 // to top.
6160 MII != MIE; --MII) {
6261 MachineInstr *MI = prior(MII);
6362 SUnit *SU = NewSUnit(MI);
63
64 // Assign the Latency field of SU using target-provided information.
65 ComputeLatency(SU);
6466
6567 // Add register-based dependencies (data, anti, and output).
6668 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
7375 std::vector &UseList = Uses[Reg];
7476 SUnit *&Def = Defs[Reg];
7577 // Optionally add output and anti dependencies.
78 // TODO: Using a latency of 1 here assumes there's no cost for
79 // reusing registers.
80 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
7681 if (Def && Def != SU)
77 Def->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false,
78 /*PhyReg=*/Reg, Cost, /*isAntiDep=*/MO.isUse());
82 Def->addPred(SDep(SU, Kind, /*Latency=*/1, /*Reg=*/Reg));
7983 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
8084 SUnit *&Def = Defs[*Alias];
8185 if (Def && Def != SU)
82 Def->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false,
83 /*PhyReg=*/*Alias, Cost, /*isAntiDep=*/MO.isUse());
86 Def->addPred(SDep(SU, Kind, /*Latency=*/1, /*Reg=*/ *Alias));
8487 }
8588
8689 if (MO.isDef()) {
8790 // Add any data dependencies.
8891 for (unsigned i = 0, e = UseList.size(); i != e; ++i)
8992 if (UseList[i] != SU)
90 UseList[i]->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false,
91 /*PhysReg=*/Reg, Cost);
93 UseList[i]->addPred(SDep(SU, SDep::Data, SU->Latency, Reg));
9294 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
9395 std::vector &UseList = Uses[*Alias];
9496 for (unsigned i = 0, e = UseList.size(); i != e; ++i)
9597 if (UseList[i] != SU)
96 UseList[i]->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false,
97 /*PhysReg=*/*Alias, Cost);
98 UseList[i]->addPred(SDep(SU, SDep::Data, SU->Latency, *Alias));
9899 }
99100
100101 UseList.clear();
116117 // This is the conservative case. Add dependencies on all memory
117118 // references.
118119 if (Chain)
119 Chain->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false);
120 Chain->addPred(SDep(SU, SDep::Order, SU->Latency));
120121 Chain = SU;
121122 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
122 PendingLoads[k]->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false);
123 PendingLoads[k]->addPred(SDep(SU, SDep::Order, SU->Latency));
123124 PendingLoads.clear();
124125 for (std::map::iterator I = MemDefs.begin(),
125126 E = MemDefs.end(); I != E; ++I) {
126 I->second->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false);
127 I->second->addPred(SDep(SU, SDep::Order, SU->Latency));
127128 I->second = SU;
128129 }
129130 for (std::map >::iterator I =
130131 MemUses.begin(), E = MemUses.end(); I != E; ++I) {
131132 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
132 I->second[i]->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false);
133 I->second[i]->addPred(SDep(SU, SDep::Order, SU->Latency));
133134 I->second.clear();
134135 }
135136 // See if it is known to just have a single memory reference.
155156 // Handle the def in MemDefs, if there is one.
156157 std::map::iterator I = MemDefs.find(V);
157158 if (I != MemDefs.end()) {
158 I->second->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false);
159 I->second->addPred(SDep(SU, SDep::Order, SU->Latency, /*Reg=*/0,
160 /*isNormalMemory=*/true));
159161 I->second = SU;
160162 } else {
161163 MemDefs[V] = SU;
165167 MemUses.find(V);
166168 if (J != MemUses.end()) {
167169 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
168 J->second[i]->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false);
170 J->second[i]->addPred(SDep(SU, SDep::Order, SU->Latency, /*Reg=*/0,
171 /*isNormalMemory=*/true));
169172 J->second.clear();
170173 }
171174 // Add a general dependence too, if needed.
172175 if (Chain)
173 Chain->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false);
176 Chain->addPred(SDep(SU, SDep::Order, SU->Latency));
174177 } else
175178 // Treat all other stores conservatively.
176179 goto new_chain;
185188 const Value *V = MI->memoperands_begin()->getValue();
186189 std::map::iterator I = MemDefs.find(V);
187190 if (I != MemDefs.end())
188 I->second->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false);
191 I->second->addPred(SDep(SU, SDep::Order, SU->Latency, /*Reg=*/0,
192 /*isNormalMemory=*/true));
189193 MemUses[V].push_back(SU);
190194
191195 // Add a general dependence too, if needed.
192196 if (Chain && (!ChainMMO ||
193197 (ChainMMO->isStore() || ChainMMO->isVolatile())))
194 Chain->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false);
198 Chain->addPred(SDep(SU, SDep::Order, SU->Latency));
195199 } else if (MI->hasVolatileMemoryRef()) {
196200 // Treat volatile loads conservatively. Note that this includes
197201 // cases where memoperand information is unavailable.
199203 } else {
200204 // A normal load. Just depend on the general chain.
201205 if (Chain)
202 Chain->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false);
206 Chain->addPred(SDep(SU, SDep::Order, SU->Latency));
203207 PendingLoads.push_back(SU);
204208 }
205209 }
207211 // Add chain edges from the terminator to ensure that all the work of the
208212 // block is completed before any control transfers.
209213 if (Terminator && SU->Succs.empty())
210 Terminator->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false);
214 Terminator->addPred(SDep(SU, SDep::Order, SU->Latency));
211215 if (TID.isTerminator() || MI->isLabel())
212216 Terminator = SU;
213
214 // Assign the Latency field of SU using target-provided information.
215 ComputeLatency(SU);
216217 }
217218 }
218219
7676
7777 void Schedule();
7878
79 /// AddPred - This adds the specified node X as a predecessor of
80 /// the current node Y if not already.
79 /// AddPred - adds a predecessor edge to SUnit SU.
8180 /// This returns true if this is a new predecessor.
82 bool AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isArtificial,
83 unsigned PhyReg = 0, int Cost = 1);
84
85 /// RemovePred - This removes the specified node N from the predecessors of
86 /// the current node M.
87 bool RemovePred(SUnit *M, SUnit *N, bool isCtrl, bool isArtificial);
81 bool AddPred(SUnit *SU, const SDep &D) {
82 return SU->addPred(D);
83 }
84
85 /// RemovePred - removes a predecessor edge from SUnit SU.
86 /// This returns true if an edge was removed.
87 bool RemovePred(SUnit *SU, const SDep &D) {
88 return SU->removePred(D);
89 }
8890
8991 private:
90 void ReleasePred(SUnit *SU, SUnit *PredSU, bool isChain);
92 void ReleasePred(SUnit *SU, SDep *PredEdge);
9193 void ScheduleNodeBottomUp(SUnit*, unsigned);
9294 SUnit *CopyAndMoveSuccessors(SUnit*);
9395 void InsertCCCopiesAndMoveSuccs(SUnit*, unsigned,
124126
125127 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
126128 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
127 void ScheduleDAGFast::ReleasePred(SUnit *SU, SUnit *PredSU, bool isChain) {
129 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) {
130 SUnit *PredSU = PredEdge->getSUnit();
128131 --PredSU->NumSuccsLeft;
129132
130133 #ifndef NDEBUG
155158 // Bottom up: release predecessors
156159 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
157160 I != E; ++I) {
158 ReleasePred(SU, I->Dep, I->isCtrl);
159 if (I->Cost < 0) {
161 ReleasePred(SU, &*I);
162 if (I->isAssignedRegDep()) {
160163 // This is a physical register dependency and it's impossible or
161164 // expensive to copy the register. Make sure nothing that can
162165 // clobber the register is scheduled between the predecessor and
163166 // this node.
164 if (!LiveRegDefs[I->Reg]) {
167 if (!LiveRegDefs[I->getReg()]) {
165168 ++NumLiveRegs;
166 LiveRegDefs[I->Reg] = I->Dep;
167 LiveRegCycles[I->Reg] = CurCycle;
169 LiveRegDefs[I->getReg()] = I->getSUnit();
170 LiveRegCycles[I->getReg()] = CurCycle;
168171 }
169172 }
170173 }
172175 // Release all the implicit physical register defs that are live.
173176 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
174177 I != E; ++I) {
175 if (I->Cost < 0) {
176 if (LiveRegCycles[I->Reg] == I->Dep->Cycle) {
178 if (I->isAssignedRegDep()) {
179 if (LiveRegCycles[I->getReg()] == I->getSUnit()->Cycle) {
177180 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
178 assert(LiveRegDefs[I->Reg] == SU &&
181 assert(LiveRegDefs[I->getReg()] == SU &&
179182 "Physical register dependency violated?");
180183 --NumLiveRegs;
181 LiveRegDefs[I->Reg] = NULL;
182 LiveRegCycles[I->Reg] = 0;
184 LiveRegDefs[I->getReg()] = NULL;
185 LiveRegCycles[I->getReg()] = 0;
183186 }
184187 }
185188 }
186189
187190 SU->isScheduled = true;
188 }
189
190 /// AddPred - adds an edge from SUnit X to SUnit Y.
191 bool ScheduleDAGFast::AddPred(SUnit *Y, SUnit *X, bool isCtrl,
192 bool isArtificial, unsigned PhyReg, int Cost) {
193 return Y->addPred(X, isCtrl, isArtificial, PhyReg, Cost);
194 }
195
196 /// RemovePred - This removes the specified node N from the predecessors of
197 /// the current node M.
198 bool ScheduleDAGFast::RemovePred(SUnit *M, SUnit *N,
199 bool isCtrl, bool isArtificial) {
200 return M->removePred(N, isCtrl, isArtificial, false);
201191 }
202192
203193 /// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
276266 LoadSU->Height = SU->Height;
277267 }
278268
279 SUnit *ChainPred = NULL;
269 SDep ChainPred;
280270 SmallVector ChainSuccs;
281271 SmallVector LoadPreds;
282272 SmallVector NodePreds;
283273 SmallVector NodeSuccs;
284274 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
285275 I != E; ++I) {
286 if (I->isCtrl)
287 ChainPred = I->Dep;
288 else if (I->Dep->getNode() && I->Dep->getNode()->isOperandOf(LoadNode))
289 LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false, false));
276 if (I->isCtrl())
277 ChainPred = *I;
278 else if (I->getSUnit()->getNode() &&
279 I->getSUnit()->getNode()->isOperandOf(LoadNode))
280 LoadPreds.push_back(*I);
290281 else
291 NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false, false));
282 NodePreds.push_back(*I);
292283 }
293284 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
294285 I != E; ++I) {
295 if (I->isCtrl)
296 ChainSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost,
297 I->isCtrl, I->isArtificial, I->isAntiDep));
286 if (I->isCtrl())
287 ChainSuccs.push_back(*I);
298288 else
299 NodeSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost,
300 I->isCtrl, I->isArtificial, I->isAntiDep));
301 }
302
303 if (ChainPred) {
304 RemovePred(SU, ChainPred, true, false);
289 NodeSuccs.push_back(*I);
290 }
291
292 if (ChainPred.getSUnit()) {
293 RemovePred(SU, ChainPred);
305294 if (isNewLoad)
306 AddPred(LoadSU, ChainPred, true, false);
295 AddPred(LoadSU, ChainPred);
307296 }
308297 for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) {
309 SDep *Pred = &LoadPreds[i];
310 RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isArtificial);
298 const SDep &Pred = LoadPreds[i];
299 RemovePred(SU, Pred);
311300 if (isNewLoad) {
312 AddPred(LoadSU, Pred->Dep, Pred->isCtrl, Pred->isArtificial,
313 Pred->Reg, Pred->Cost);
301 AddPred(LoadSU, Pred);
314302 }
315303 }
316304 for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) {
317 SDep *Pred = &NodePreds[i];
318 RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isArtificial);
319 AddPred(NewSU, Pred->Dep, Pred->isCtrl, Pred->isArtificial,
320 Pred->Reg, Pred->Cost);
305 const SDep &Pred = NodePreds[i];
306 RemovePred(SU, Pred);
307 AddPred(NewSU, Pred);
321308 }
322309 for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) {
323 SDep *Succ = &NodeSuccs[i];
324 RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isArtificial);
325 AddPred(Succ->Dep, NewSU, Succ->isCtrl, Succ->isArtificial,
326 Succ->Reg, Succ->Cost);
310 SDep D = NodeSuccs[i];
311 SUnit *SuccDep = D.getSUnit();
312 D.setSUnit(SU);
313 RemovePred(SuccDep, D);
314 D.setSUnit(NewSU);
315 AddPred(SuccDep, D);
327316 }
328317 for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) {
329 SDep *Succ = &ChainSuccs[i];
330 RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isArtificial);
318 SDep D = ChainSuccs[i];
319 SUnit *SuccDep = D.getSUnit();
320 D.setSUnit(SU);
321 RemovePred(SuccDep, D);
331322 if (isNewLoad) {
332 AddPred(Succ->Dep, LoadSU, Succ->isCtrl, Succ->isArtificial,
333 Succ->Reg, Succ->Cost);
323 D.setSUnit(LoadSU);
324 AddPred(SuccDep, D);
334325 }
335326 }
336327 if (isNewLoad) {
337 AddPred(NewSU, LoadSU, false, false);
328 AddPred(NewSU, SDep(LoadSU, SDep::Order, LoadSU->Latency));
338329 }
339330
340331 ++NumUnfolds;
352343 // New SUnit has the exact same predecessors.
353344 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
354345 I != E; ++I)
355 if (!I->isArtificial) {
356 AddPred(NewSU, I->Dep, I->isCtrl, false, I->Reg, I->Cost);
357 NewSU->Depth = std::max(NewSU->Depth, I->Dep->Depth+1);
346 if (!I->isArtificial()) {
347 AddPred(NewSU, *I);
348 NewSU->Depth = std::max(NewSU->Depth, I->getSUnit()->Depth+1);
358349 }
359350
360351 // Only copy scheduled successors. Cut them from old node's successor
361352 // list and move them over.
362 SmallVector*, bool>, 4> DelDeps;
353 SmallVector *, SDep>, 4> DelDeps;
363354 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
364355 I != E; ++I) {
365 if (I->isArtificial)
356 if (I->isArtificial())
366357 continue;
367 if (I->Dep->isScheduled) {
368 NewSU->Height = std::max(NewSU->Height, I->Dep->Height+1);
369 AddPred(I->Dep, NewSU, I->isCtrl, false, I->Reg, I->Cost);
370 DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
358 SUnit *SuccSU = I->getSUnit();
359 if (SuccSU->isScheduled) {
360 NewSU->Height = std::max(NewSU->Height, SuccSU->Height+1);
361 SDep D = *I;
362 D.setSUnit(NewSU);
363 AddPred(SuccSU, D);
364 D.setSUnit(SU);
365 DelDeps.push_back(std::make_pair(SuccSU, D));
371366 }
372367 }
373368 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
374 SUnit *Succ = DelDeps[i].first;
375 bool isCtrl = DelDeps[i].second;
376 RemovePred(Succ, SU, isCtrl, false);
369 RemovePred(DelDeps[i].first, DelDeps[i].second);
377370 }
378371
379372 ++NumDups;
396389
397390 // Only copy scheduled successors. Cut them from old node's successor
398391 // list and move them over.
399 SmallVector*, bool>, 4> DelDeps;
392 SmallVector *, SDep>, 4> DelDeps;
400393 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
401394 I != E; ++I) {
402 if (I->isArtificial)
395 if (I->isArtificial())
403396 continue;
404 if (I->Dep->isScheduled) {
405 AddPred(I->Dep, CopyToSU, I->isCtrl, false, I->Reg, I->Cost);
406 DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
397 SUnit *SuccSU = I->getSUnit();
398 if (SuccSU->isScheduled) {
399 SDep D = *I;
400 D.setSUnit(CopyToSU);
401 AddPred(SuccSU, D);
402 DelDeps.push_back(std::make_pair(SuccSU, *I));
407403 }
408404 }
409405 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
410 SUnit *Succ = DelDeps[i].first;
411 bool isCtrl = DelDeps[i].second;
412 RemovePred(Succ, SU, isCtrl, false);
413 }
414
415 AddPred(CopyFromSU, SU, false, false, Reg, -1);
416 AddPred(CopyToSU, CopyFromSU, false, false, Reg, 1);
406 RemovePred(DelDeps[i].first, DelDeps[i].second);
407 }
408
409 AddPred(CopyFromSU, SDep(SU, SDep::Data, SU->Latency, Reg));
410 AddPred(CopyToSU, SDep(CopyFromSU, SDep::Data, CopyFromSU->Latency, 0));
417411
418412 Copies.push_back(CopyFromSU);
419413 Copies.push_back(CopyToSU);
450444 // If this node would clobber any "live" register, then it's not ready.
451445 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
452446 I != E; ++I) {
453 if (I->Cost < 0) {
454 unsigned Reg = I->Reg;
455 if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != I->Dep) {
447 if (I->isAssignedRegDep()) {
448 unsigned Reg = I->getReg();
449 if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != I->getSUnit()) {
456450 if (RegAdded.insert(Reg))
457451 LRegs.push_back(Reg);
458452 }
459453 for (const unsigned *Alias = TRI->getAliasSet(Reg);
460454 *Alias; ++Alias)
461 if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != I->Dep) {
455 if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != I->getSUnit()) {
462456 if (RegAdded.insert(*Alias))
463457 LRegs.push_back(*Alias);
464458 }
549543 InsertCCCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
550544 DOUT << "Adding an edge from SU # " << TrySU->NodeNum
551545 << " to SU #" << Copies.front()->NodeNum << "\n";
552 AddPred(TrySU, Copies.front(), true, true);
546 AddPred(TrySU, SDep(Copies.front(), SDep::Order, /*Latency=*/1,
547 /*Reg=*/0, /*isNormalMemory=*/false,
548 /*isMustAlias=*/false, /*isArtificial=*/true));
553549 NewDef = Copies.back();
554550 }
555551
556552 DOUT << "Adding an edge from SU # " << NewDef->NodeNum
557553 << " to SU #" << TrySU->NodeNum << "\n";
558554 LiveRegDefs[Reg] = NewDef;
559 AddPred(NewDef, TrySU, true, true);
555 AddPred(NewDef, SDep(TrySU, SDep::Order, /*Latency=*/1,
556 /*Reg=*/0, /*isNormalMemory=*/false,
557 /*isMustAlias=*/false, /*isArtificial=*/true));
560558 TrySU->isAvailable = false;
561559 CurSU = NewDef;
562560 }
7777 void Schedule();
7878
7979 private:
80 void ReleaseSucc(SUnit *SU, SUnit *SuccSU, bool isChain);
80 void ReleaseSucc(SUnit *SU, const SDep &D);
8181 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
8282 void ListScheduleTopDown();
8383 };
106106
107107 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
108108 /// the PendingQueue if the count reaches zero. Also update its cycle bound.
109 void ScheduleDAGList::ReleaseSucc(SUnit *SU, SUnit *SuccSU, bool isChain) {
109 void ScheduleDAGList::ReleaseSucc(SUnit *SU, const SDep &D) {
110 SUnit *SuccSU = D.getSUnit();
110111 --SuccSU->NumPredsLeft;
111112
112113 #ifndef NDEBUG
120121
121122 // Compute the cycle when this SUnit actually becomes available. This
122123 // is the max of the start time of all predecessors plus their latencies.
123 // If this is a token edge, we don't need to wait for the latency of the
124 // preceeding instruction (e.g. a long-latency load) unless there is also
125 // some other data dependence.
126 unsigned PredDoneCycle = SU->Cycle;
127 if (!isChain)
128 PredDoneCycle += SU->Latency;
129 else if (SU->Latency)
130 PredDoneCycle += 1;
124 unsigned PredDoneCycle = SU->Cycle + SU->Latency;
131125 SuccSU->CycleBound = std::max(SuccSU->CycleBound, PredDoneCycle);
132126
133127 if (SuccSU->NumPredsLeft == 0) {
148142 // Top down: release successors.
149143 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
150144 I != E; ++I)
151 ReleaseSucc(SU, I->Dep, I->isCtrl);
145 ReleaseSucc(SU, *I);
152146
153147 SU->isScheduled = true;
154148 AvailableQueue->ScheduledNode(SU);
9797 return Topo.WillCreateCycle(SU, TargetSU);
9898 }
9999
100 /// AddPred - This adds the specified node X as a predecessor of
101 /// the current node Y if not already.
100 /// AddPred - adds a predecessor edge to SUnit SU.
102101 /// This returns true if this is a new predecessor.
103102 /// Updates the topological ordering if required.
104 bool AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isArtificial,
105 unsigned PhyReg = 0, int Cost = 1) {
106 Topo.AddPred(Y, X);
107 return Y->addPred(X, isCtrl, isArtificial, PhyReg, Cost);
108 }
109
110 /// RemovePred - This removes the specified node N from the predecessors of
111 /// the current node M. Updates the topological ordering if required.
112 bool RemovePred(SUnit *M, SUnit *N, bool isCtrl, bool isArtificial) {
113 Topo.RemovePred(M, N);
114 return M->removePred(N, isCtrl, isArtificial, false);
103 bool AddPred(SUnit *SU, const SDep &D) {
104 Topo.AddPred(SU, D.getSUnit());
105 return SU->addPred(D);
106 }
107
108 /// RemovePred - removes a predecessor edge from SUnit SU.
109 /// This returns true if an edge was removed.
110 /// Updates the topological ordering if required.
111 bool RemovePred(SUnit *SU, const SDep &D) {
112 Topo.RemovePred(SU, D.getSUnit());
113 return SU->removePred(D);
115114 }
116115
117116 private:
118 void ReleasePred(SUnit *SU, SUnit *PredSU, bool isChain);
119 void ReleaseSucc(SUnit *SU, SUnit *SuccSU, bool isChain);
120 void CapturePred(SUnit*, SUnit*, bool);
117 void ReleasePred(SUnit *SU, SDep *PredEdge);
118 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
119 void CapturePred(SDep *PredEdge);
121120 void ScheduleNodeBottomUp(SUnit*, unsigned);
122121 void ScheduleNodeTopDown(SUnit*, unsigned);
123122 void UnscheduleNodeBottomUp(SUnit*);
234233
235234 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
236235 I != E; ++I) {
237 if (!I->isCtrl)
238 OperandSeen.insert(I->Dep->OrigNode);
236 if (!I->isCtrl())
237 OperandSeen.insert(I->getSUnit()->OrigNode);
239238 }
240239 }
241240 }
246245
247246 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
248247 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
249 void ScheduleDAGRRList::ReleasePred(SUnit *SU, SUnit *PredSU, bool isChain) {
248 void ScheduleDAGRRList::ReleasePred(SUnit *SU, SDep *PredEdge) {
249 SUnit *PredSU = PredEdge->getSUnit();
250250 --PredSU->NumSuccsLeft;
251251
252252 #ifndef NDEBUG
277277 // Bottom up: release predecessors
278278 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
279279 I != E; ++I) {
280 ReleasePred(SU, I->Dep, I->isCtrl);
281 if (I->Cost < 0) {
280 ReleasePred(SU, &*I);
281 if (I->isAssignedRegDep()) {
282282 // This is a physical register dependency and it's impossible or
283283 // expensive to copy the register. Make sure nothing that can
284284 // clobber the register is scheduled between the predecessor and
285285 // this node.
286 if (!LiveRegDefs[I->Reg]) {
286 if (!LiveRegDefs[I->getReg()]) {
287287 ++NumLiveRegs;
288 LiveRegDefs[I->Reg] = I->Dep;
289 LiveRegCycles[I->Reg] = CurCycle;
288 LiveRegDefs[I->getReg()] = I->getSUnit();
289 LiveRegCycles[I->getReg()] = CurCycle;
290290 }
291291 }
292292 }
294294 // Release all the implicit physical register defs that are live.
295295 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
296296 I != E; ++I) {
297 if (I->Cost < 0) {
298 if (LiveRegCycles[I->Reg] == I->Dep->Cycle) {
297 if (I->isAssignedRegDep()) {
298 if (LiveRegCycles[I->getReg()] == I->getSUnit()->Cycle) {
299299 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
300 assert(LiveRegDefs[I->Reg] == SU &&
300 assert(LiveRegDefs[I->getReg()] == SU &&
301301 "Physical register dependency violated?");
302302 --NumLiveRegs;
303 LiveRegDefs[I->Reg] = NULL;
304 LiveRegCycles[I->Reg] = 0;
303 LiveRegDefs[I->getReg()] = NULL;
304 LiveRegCycles[I->getReg()] = 0;
305305 }
306306 }
307307 }
313313 /// CapturePred - This does the opposite of ReleasePred. Since SU is being
314314 /// unscheduled, incrcease the succ left count of its predecessors. Remove
315315 /// them from AvailableQueue if necessary.
316 void ScheduleDAGRRList::CapturePred(SUnit *PredSU, SUnit *SU, bool isChain) {
316 void ScheduleDAGRRList::CapturePred(SDep *PredEdge) {
317 SUnit *PredSU = PredEdge->getSUnit();
317318 if (PredSU->isAvailable) {
318319 PredSU->isAvailable = false;
319320 if (!PredSU->isPending)
333334
334335 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
335336 I != E; ++I) {
336 CapturePred(I->Dep, SU, I->isCtrl);
337 if (I->Cost < 0 && SU->Cycle == LiveRegCycles[I->Reg]) {
337 CapturePred(&*I);
338 if (I->isAssignedRegDep() && SU->Cycle == LiveRegCycles[I->getReg()]) {
338339 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
339 assert(LiveRegDefs[I->Reg] == I->Dep &&
340 assert(LiveRegDefs[I->getReg()] == I->getSUnit() &&
340341 "Physical register dependency violated?");
341342 --NumLiveRegs;
342 LiveRegDefs[I->Reg] = NULL;
343 LiveRegCycles[I->Reg] = 0;
343 LiveRegDefs[I->getReg()] = NULL;
344 LiveRegCycles[I->getReg()] = 0;
344345 }
345346 }
346347
347348 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
348349 I != E; ++I) {
349 if (I->Cost < 0) {
350 if (!LiveRegDefs[I->Reg]) {
351 LiveRegDefs[I->Reg] = SU;
350 if (I->isAssignedRegDep()) {
351 if (!LiveRegDefs[I->getReg()]) {
352 LiveRegDefs[I->getReg()] = SU;
352353 ++NumLiveRegs;
353354 }
354 if (I->Dep->Cycle < LiveRegCycles[I->Reg])
355 LiveRegCycles[I->Reg] = I->Dep->Cycle;
355 if (I->getSUnit()->Cycle < LiveRegCycles[I->getReg()])
356 LiveRegCycles[I->getReg()] = I->getSUnit()->Cycle;
356357 }
357358 }
358359
465466 NewSU->Height = SU->Height;
466467 ComputeLatency(NewSU);
467468
468 SUnit *ChainPred = NULL;
469 SDep ChainPred;
469470 SmallVector ChainSuccs;
470471 SmallVector LoadPreds;
471472 SmallVector NodePreds;
472473 SmallVector NodeSuccs;
473474 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
474475 I != E; ++I) {
475 if (I->isCtrl)
476 ChainPred = I->Dep;
477 else if (I->Dep->getNode() && I->Dep->getNode()->isOperandOf(LoadNode))
478 LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false, false));
476 if (I->isCtrl())
477 ChainPred = *I;
478 else if (I->getSUnit()->getNode() &&
479 I->getSUnit()->getNode()->isOperandOf(LoadNode))
480 LoadPreds.push_back(*I);
479481 else
480 NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false, false));
482 NodePreds.push_back(*I);
481483 }
482484 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
483485 I != E; ++I) {
484 if (I->isCtrl)
485 ChainSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost,
486 I->isCtrl, I->isArtificial, I->isAntiDep));
486 if (I->isCtrl())
487 ChainSuccs.push_back(*I);
487488 else
488 NodeSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost,
489 I->isCtrl, I->isArtificial, I->isAntiDep));
490 }
491
492 if (ChainPred) {
493 RemovePred(SU, ChainPred, true, false);
489 NodeSuccs.push_back(*I);
490 }
491
492 if (ChainPred.getSUnit()) {
493 RemovePred(SU, ChainPred);
494494 if (isNewLoad)
495 AddPred(LoadSU, ChainPred, true, false);
495 AddPred(LoadSU, ChainPred);
496496 }
497497 for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) {
498 SDep *Pred = &LoadPreds[i];
499 RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isArtificial);
498 const SDep &Pred = LoadPreds[i];
499 RemovePred(SU, Pred);
500500 if (isNewLoad) {
501 AddPred(LoadSU, Pred->Dep, Pred->isCtrl, Pred->isArtificial,
502 Pred->Reg, Pred->Cost);
501 AddPred(LoadSU, Pred);
503502 }
504503 }
505504 for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) {
506 SDep *Pred = &NodePreds[i];
507 RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isArtificial);
508 AddPred(NewSU, Pred->Dep, Pred->isCtrl, Pred->isArtificial,
509 Pred->Reg, Pred->Cost);
505 const SDep &Pred = NodePreds[i];
506 RemovePred(SU, Pred);
507 AddPred(NewSU, Pred);
510508 }
511509 for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) {
512 SDep *Succ = &NodeSuccs[i];
513 RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isArtificial);
514 AddPred(Succ->Dep, NewSU, Succ->isCtrl, Succ->isArtificial,
515 Succ->Reg, Succ->Cost);
510 SDep D = NodeSuccs[i];
511 SUnit *SuccDep = D.getSUnit();
512 D.setSUnit(SU);
513 RemovePred(SuccDep, D);
514 D.setSUnit(NewSU);
515 AddPred(SuccDep, D);
516516 }
517517 for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) {
518 SDep *Succ = &ChainSuccs[i];
519 RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isArtificial);
518 SDep D = ChainSuccs[i];
519 SUnit *SuccDep = D.getSUnit();
520 D.setSUnit(SU);
521 RemovePred(SuccDep, D);
520522 if (isNewLoad) {
521 AddPred(Succ->Dep, LoadSU, Succ->isCtrl, Succ->isArtificial,
522 Succ->Reg, Succ->Cost);
523 D.setSUnit(LoadSU);
524 AddPred(SuccDep, D);
523525 }
524526 }
525527 if (isNewLoad) {
526 AddPred(NewSU, LoadSU, false, false);
528 AddPred(NewSU, SDep(LoadSU, SDep::Order, LoadSU->Latency));
527529 }
528530
529531 if (isNewLoad)
545547 // New SUnit has the exact same predecessors.
546548 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
547549 I != E; ++I)
548 if (!I->isArtificial) {
549 AddPred(NewSU, I->Dep, I->isCtrl, false, I->Reg, I->Cost);
550 NewSU->Depth = std::max(NewSU->Depth, I->Dep->Depth+1);
550 if (!I->isArtificial()) {
551 AddPred(NewSU, *I);
552 NewSU->Depth = std::max(NewSU->Depth, I->getSUnit()->Depth+1);
551553 }
552554
553555 // Only copy scheduled successors. Cut them from old node's successor
554556 // list and move them over.
555 SmallVector*, bool>, 4> DelDeps;
557 SmallVector *, SDep>, 4> DelDeps;
556558 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
557559 I != E; ++I) {
558 if (I->isArtificial)
560 if (I->isArtificial())
559561 continue;
560 if (I->Dep->isScheduled) {
561 NewSU->Height = std::max(NewSU->Height, I->Dep->Height+1);
562 AddPred(I->Dep, NewSU, I->isCtrl, false, I->Reg, I->Cost);
563 DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
562 SUnit *SuccSU = I->getSUnit();
563 if (SuccSU->isScheduled) {
564 NewSU->Height = std::max(NewSU->Height, SuccSU->Height+1);
565 SDep D = *I;
566 D.setSUnit(NewSU);
567 AddPred(SuccSU, D);
568 D.setSUnit(SU);
569 DelDeps.push_back(std::make_pair(SuccSU, D));
564570 }
565571 }
566572 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
567 SUnit *Succ = DelDeps[i].first;
568 bool isCtrl = DelDeps[i].second;
569 RemovePred(Succ, SU, isCtrl, false);
573 RemovePred(DelDeps[i].first, DelDeps[i].second);
570574 }
571575
572576 AvailableQueue->updateNode(SU);
594598
595599 // Only copy scheduled successors. Cut them from old node's successor
596600 // list and move them over.
597 SmallVector*, bool>, 4> DelDeps;
601 SmallVector *, SDep>, 4> DelDeps;
598602 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
599603 I != E; ++I) {
600 if (I->isArtificial)
604 if (I->isArtificial())
601605 continue;
602 if (I->Dep->isScheduled) {
603 CopyToSU->Height = std::max(CopyToSU->Height, I->Dep->Height+1);
604 AddPred(I->Dep, CopyToSU, I->isCtrl, false, I->Reg, I->Cost);
605 DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
606 SUnit *SuccSU = I->getSUnit();
607 if (SuccSU->isScheduled) {
608 SDep D = *I;
609 D.setSUnit(CopyToSU);
610 AddPred(SuccSU, D);
611 DelDeps.push_back(std::make_pair(SuccSU, *I));
606612 }
607613 }
608614 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
609 SUnit *Succ = DelDeps[i].first;
610 bool isCtrl = DelDeps[i].second;
611 RemovePred(Succ, SU, isCtrl, false);
612 }
613
614 AddPred(CopyFromSU, SU, false, false, Reg, -1);
615 AddPred(CopyToSU, CopyFromSU, false, false, Reg, 1);
615 RemovePred(DelDeps[i].first, DelDeps[i].second);
616 }
617
618 AddPred(CopyFromSU, SDep(SU, SDep::Data, SU->Latency, Reg));
619 AddPred(CopyToSU, SDep(CopyFromSU, SDep::Data, CopyFromSU->Latency, 0));
616620
617621 AvailableQueue->updateNode(SU);
618622 AvailableQueue->addNode(CopyFromSU);
652656 // If this node would clobber any "live" register, then it's not ready.
653657 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
654658 I != E; ++I) {
655 if (I->Cost < 0) {
656 unsigned Reg = I->Reg;
657 if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != I->Dep) {
659 if (I->isAssignedRegDep()) {
660 unsigned Reg = I->getReg();
661 if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != I->getSUnit()) {
658662 if (RegAdded.insert(Reg))
659663 LRegs.push_back(Reg);
660664 }
661665 for (const unsigned *Alias = TRI->getAliasSet(Reg);
662666 *Alias; ++Alias)
663 if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != I->Dep) {
667 if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != I->getSUnit()) {
664668 if (RegAdded.insert(*Alias))
665669 LRegs.push_back(*Alias);
666670 }
748752 OldSU->isAvailable = false;
749753 AvailableQueue->remove(OldSU);
750754 }
751 AddPred(TrySU, OldSU, true, true);
755 AddPred(TrySU, SDep(OldSU, SDep::Order, /*Latency=*/1,
756 /*Reg=*/0, /*isNormalMemory=*/false,
757 /*isMustAlias=*/false, /*isArtificial=*/true));
752758 // If one or more successors has been unscheduled, then the current
753759 // node is no longer avaialable. Schedule a successor that's now
754760 // available instead.
787793 InsertCCCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
788794 DOUT << "Adding an edge from SU # " << TrySU->NodeNum
789795 << " to SU #" << Copies.front()->NodeNum << "\n";
790 AddPred(TrySU, Copies.front(), true, true);
796 AddPred(TrySU, SDep(Copies.front(), SDep::Order, /*Latency=*/1,
797 /*Reg=*/0, /*isMustAlias=*/false,
798 /*isArtificial=*/true));
791799 NewDef = Copies.back();
792800 }
793801
794802 DOUT << "Adding an edge from SU # " << NewDef->NodeNum
795803 << " to SU #" << TrySU->NodeNum << "\n";
796804 LiveRegDefs[Reg] = NewDef;
797 AddPred(NewDef, TrySU, true, true);
805 AddPred(NewDef, SDep(TrySU, SDep::Order, /*Latency=*/1,
806 /*Reg=*/0, /*isMustAlias=*/false,
807 /*isArtificial=*/true));
798808 TrySU->isAvailable = false;
799809 CurSU = NewDef;
800810 }
833843
834844 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
835845 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
836 void ScheduleDAGRRList::ReleaseSucc(SUnit *SU, SUnit *SuccSU, bool isChain) {
846 void ScheduleDAGRRList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
847 SUnit *SuccSU = SuccEdge->getSUnit();
837848 --SuccSU->NumPredsLeft;
838849
839850 #ifndef NDEBUG
864875 // Top down: release successors
865876 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
866877 I != E; ++I)
867 ReleaseSucc(SU, I->Dep, I->isCtrl);
878 ReleaseSucc(SU, &*I);
868879
869880 SU->isScheduled = true;
870881 AvailableQueue->ScheduledNode(SU);
947958 unsigned Extra = 0;
948959 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
949960 I != E; ++I) {
950 if (I->isCtrl) continue; // ignore chain preds
951 SUnit *PredSU = I->Dep;
961 if (I->isCtrl()) continue; // ignore chain preds
962 SUnit *PredSU = I->getSUnit();
952963 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU, SUNumbers);
953964 if (PredSethiUllman > SethiUllmanNumber) {
954965 SethiUllmanNumber = PredSethiUllman;
955966 Extra = 0;
956 } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl)
967 } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl())
957968 ++Extra;
958969 }
959970
10981109 unsigned MaxCycle = 0;
10991110 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
11001111 I != E; ++I) {
1101 unsigned Cycle = I->Dep->Cycle;
1112 unsigned Cycle = I->getSUnit()->Cycle;
11021113 // If there are bunch of CopyToRegs stacked up, they should be considered
11031114 // to be at the same position.
1104 if (I->Dep->getNode() && I->Dep->getNode()->getOpcode() == ISD::CopyToReg)
1105 Cycle = closestSucc(I->Dep)+1;
1115 if (I->getSUnit()->getNode() &&
1116 I->getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)
1117 Cycle = closestSucc(I->getSUnit())+1;
11061118 if (Cycle > MaxCycle)
11071119 MaxCycle = Cycle;
11081120 }
11161128 unsigned Scratches = 0;
11171129 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
11181130 I != E; ++I) {
1119 if (I->isCtrl) continue; // ignore chain preds
1120 if (!I->Dep->getNode() || I->Dep->getNode()->getOpcode() != ISD::CopyFromReg)
1131 if (I->isCtrl()) continue; // ignore chain preds
1132 if (!I->getSUnit()->getNode() ||
1133 I->getSUnit()->getNode()->getOpcode() != ISD::CopyFromReg)
11211134 Scratches++;
11221135 }
11231136 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
11241137 I != E; ++I) {
1125 if (I->isCtrl) continue; // ignore chain succs
1126 if (!I->Dep->getNode() || I->Dep->getNode()->getOpcode() != ISD::CopyToReg)
1138 if (I->isCtrl()) continue; // ignore chain succs
1139 if (!I->getSUnit()->getNode() ||
1140 I->getSUnit()->getNode()->getOpcode() != ISD::CopyToReg)
11271141 Scratches += 10;
11281142 }
11291143 return Scratches;
12041218 static bool hasCopyToRegUse(const SUnit *SU) {
12051219 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
12061220 I != E; ++I) {
1207 if (I->isCtrl) continue;
1208 const SUnit *SuccSU = I->Dep;
1221 if (I->isCtrl()) continue;
1222 const SUnit *SuccSU = I->getSUnit();
12091223 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg)
12101224 return true;
12111225 }
12731287 if (!DUSU) continue;
12741288 for (SUnit::const_succ_iterator I = DUSU->Succs.begin(),
12751289 E = DUSU->Succs.end(); I != E; ++I) {
1276 if (I->isCtrl) continue;
1277 SUnit *SuccSU = I->Dep;
1290 if (I->isCtrl()) continue;
1291 SUnit *SuccSU = I->getSUnit();
12781292 if (SuccSU == SU)
12791293 continue;
12801294 // Be conservative. Ignore if nodes aren't at roughly the same
13011315 !scheduleDAG->IsReachable(SuccSU, SU)) {
13021316 DOUT << "Adding a pseudo-two-addr edge from SU # " << SU->NodeNum
13031317 << " to SU #" << SuccSU->NodeNum << "\n";
1304 scheduleDAG->AddPred(SU, SuccSU, true, true);
1318 scheduleDAG->AddPred(SU, SDep(SuccSU, SDep::Order, /*Latency=*/1,
1319 /*Reg=*/0, /*isMustAlias=*/false,
1320 /*isArtificial=*/true));
13051321 }
13061322 }
13071323 }
13261342 unsigned Sum = 0;
13271343 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
13281344 I != E; ++I) {
1329 const SUnit *SuccSU = I->Dep;
1345 const SUnit *SuccSU = I->getSUnit();
13301346 for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(),
13311347 EE = SuccSU->Preds.end(); II != EE; ++II) {
1332 SUnit *PredSU = II->Dep;
1348 SUnit *PredSU = II->getSUnit();
13331349 if (!PredSU->isScheduled)
13341350 if (++Sum > Limit)
13351351 return Sum;
175175 int Cost = 1;
176176 // Determine if this is a physical register dependency.
177177 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
178 SU->addPred(OpSU, isChain, false, PhysReg, Cost);
178 assert((PhysReg == 0 || !isChain) &&
179 "Chain dependence via physreg data?");
180 SU->addPred(SDep(OpSU, isChain ? SDep::Order : SDep::Data,
181 OpSU->Latency, PhysReg));
179182 }
180183 }
181184 }