llvm.org GIT mirror llvm / 54a2540
R600/SI: Use VALU for i1 XOR git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213528 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 5 years ago
3 changed file(s) with 12 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
15201520 [(set i1:$dst, (or i1:$src0, i1:$src1))]
15211521 >;
15221522
1523 def V_XOR_I1 : InstSI <
1524 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1525 [(set i1:$dst, (xor i1:$src0, i1:$src1))]
1526 >;
1527
15231528 // SI pseudo instructions. These are used by the CFG structurizer pass
15241529 // and should be lowered to ISA instructions prior to codegen.
15251530
17841789 //===----------------------------------------------------------------------===//
17851790 // SOP2 Patterns
17861791 //===----------------------------------------------------------------------===//
1787
1788 def : Pat <
1789 (i1 (xor i1:$src0, i1:$src1)),
1790 (S_XOR_B64 $src0, $src1)
1791 >;
17921792
17931793 //===----------------------------------------------------------------------===//
17941794 // SOPP Patterns
101101 continue;
102102 }
103103
104 if (MI.getOpcode() == AMDGPU::V_XOR_I1) {
105 I1Defs.push_back(MI.getOperand(0).getReg());
106 MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e32));
107 continue;
108 }
109
104110 if (MI.getOpcode() != AMDGPU::COPY ||
105111 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg()) ||
106112 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(1).getReg()))
4141 ;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}}
4242
4343 ;SI-CHECK: @xor_i1
44 ;SI-CHECK: S_XOR_B64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
44 ;SI-CHECK: V_XOR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
4545
4646 define void @xor_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
4747 %a = load float addrspace(1) * %in0