llvm.org GIT mirror llvm / 5489893
- More pre-split fixes: spill slot live interval computation bug; restore point bug. - If a def is spilt, remember its spill index to allow its reuse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58375 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 11 years ago
5 changed file(s) with 148 addition(s) and 40 deletion(s). Raw diff Collapse all Expand all
155155 return reg & ~(1U << (sizeof(unsigned)*8-1));
156156 }
157157
158 bool hasAtLeastOneValue() const { return !valnos.empty(); }
159
158160 bool containsOneValue() const { return valnos.size() == 1; }
159161
160162 unsigned getNumValNums() const { return (unsigned)valnos.size(); }
2929 #include "llvm/Support/CommandLine.h"
3030 #include "llvm/Support/Debug.h"
3131 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/DepthFirstIterator.h"
3233 #include "llvm/ADT/SmallPtrSet.h"
3334 #include "llvm/ADT/Statistic.h"
3435 using namespace llvm;
6869 // IntervalSSMap - A map from live interval to spill slots.
6970 DenseMap IntervalSSMap;
7071
71 // RestoreMIs - All the restores inserted due to live interval splitting.
72 SmallPtrSet RestoreMIs;
72 // Def2SpillMap - A map from a def instruction index to spill index.
73 DenseMap Def2SpillMap;
7374
7475 public:
7576 static char ID;
9293
9394 virtual void releaseMemory() {
9495 IntervalSSMap.clear();
95 RestoreMIs.clear();
96 Def2SpillMap.clear();
9697 }
9798
9899 virtual const char *getPassName() const {
123124
124125 int CreateSpillStackSlot(unsigned, const TargetRegisterClass *);
125126
126 bool IsAvailableInStack(unsigned, unsigned, int&) const;
127 bool IsAvailableInStack(MachineBasicBlock*, unsigned, unsigned, unsigned,
128 unsigned&, int&) const;
127129
128130 void UpdateSpillSlotInterval(VNInfo*, unsigned, unsigned);
129131
220222 unsigned LastIdx,
221223 SmallPtrSet &RefsInMBB,
222224 unsigned &RestoreIndex) {
225 // FIXME: Allow spill to be inserted to the beginning of the mbb. Update mbb
226 // begin index accordingly.
223227 MachineBasicBlock::iterator Pt = MBB->end();
224228 unsigned EndIdx = LIs->getMBBEndIdx(MBB);
225229
228232 if (RefsInMBB.empty() && LastIdx >= EndIdx) {
229233 MachineBasicBlock::iterator MII = MBB->end();
230234 MachineBasicBlock::iterator EndPt = MI;
235 --MII;
231236 do {
232 --MII;
233237 unsigned Index = LIs->getInstructionIndex(MII);
234238 unsigned Gap = LIs->findGapBeforeInstr(Index);
235239 if (Gap) {
237241 RestoreIndex = Gap;
238242 break;
239243 }
244 --MII;
240245 } while (MII != EndPt);
241246 } else {
242247 MachineBasicBlock::iterator MII = MI;
277282
278283 // Create live interval for stack slot.
279284 CurrSLI = &LSs->getOrCreateInterval(SS);
280 if (CurrSLI->getNumValNums())
285 if (CurrSLI->hasAtLeastOneValue())
281286 CurrSValNo = CurrSLI->getValNumInfo(0);
282287 else
283288 CurrSValNo = CurrSLI->getNextValue(~0U, 0, LSs->getVNInfoAllocator());
287292 /// IsAvailableInStack - Return true if register is available in a split stack
288293 /// slot at the specified index.
289294 bool
290 PreAllocSplitting::IsAvailableInStack(unsigned Reg, unsigned Index, int &SS) const {
295 PreAllocSplitting::IsAvailableInStack(MachineBasicBlock *DefMBB,
296 unsigned Reg, unsigned DefIndex,
297 unsigned RestoreIndex, unsigned &SpillIndex,
298 int& SS) const {
299 if (!DefMBB)
300 return false;
301
291302 DenseMap::iterator I = IntervalSSMap.find(Reg);
292303 if (I == IntervalSSMap.end())
293304 return false;
294 if (LSs->getInterval(I->second).liveAt(Index)) {
295 SS = I->second;
296 return true;
297 }
298 return false;
305 DenseMap::iterator II = Def2SpillMap.find(DefIndex);
306 if (II == Def2SpillMap.end())
307 return false;
308
309 // If last spill of def is in the same mbb as barrier mbb (where restore will
310 // be), make sure it's not below the intended restore index.
311 // FIXME: Undo the previous spill?
312 assert(LIs->getMBBFromIndex(II->second) == DefMBB);
313 if (DefMBB == BarrierMBB && II->second >= RestoreIndex)
314 return false;
315
316 SS = I->second;
317 SpillIndex = II->second;
318 return true;
299319 }
300320
301321 /// UpdateSpillSlotInterval - Given the specified val# of the register live
304324 void
305325 PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, unsigned SpillIndex,
306326 unsigned RestoreIndex) {
307 const LiveRange *LR = CurrLI->getLiveRangeContaining(SpillIndex);
308 if (LR->contains(RestoreIndex)) {
327 assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
328 "Expect restore in the barrier mbb");
329
330 MachineBasicBlock *MBB = LIs->getMBBFromIndex(SpillIndex);
331 if (MBB == BarrierMBB) {
332 // Intra-block spill + restore. We are done.
309333 LiveRange SLR(SpillIndex, RestoreIndex, CurrSValNo);
310334 CurrSLI->addRange(SLR);
311335 return;
312336 }
313337
314 SmallPtrSet Processed;
315 LiveRange SLR(SpillIndex, LR->end, CurrSValNo);
338 SmallPtrSet Processed;
339 unsigned EndIdx = LIs->getMBBEndIdx(MBB);
340 LiveRange SLR(SpillIndex, EndIdx+1, CurrSValNo);
316341 CurrSLI->addRange(SLR);
317 Processed.insert(LR);
342 Processed.insert(MBB);
318343
319344 // Start from the spill mbb, figure out the extend of the spill slot's
320345 // live interval.
321346 SmallVector WorkList;
322 MachineBasicBlock *MBB = LIs->getMBBFromIndex(SpillIndex);
323 if (LR->end > LIs->getMBBEndIdx(MBB))
347 const LiveRange *LR = CurrLI->getLiveRangeContaining(SpillIndex);
348 if (LR->end > EndIdx)
324349 // If live range extend beyond end of mbb, add successors to work list.
325350 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
326351 SE = MBB->succ_end(); SI != SE; ++SI)
327352 WorkList.push_back(*SI);
328 // Live range may cross multiple basic blocks, add all reachable mbbs to
329 // the work list.
330 LIs->findReachableMBBs(LR->start, LR->end, WorkList);
331353
332354 while (!WorkList.empty()) {
333355 MachineBasicBlock *MBB = WorkList.back();
334356 WorkList.pop_back();
357 if (Processed.count(MBB))
358 continue;
335359 unsigned Idx = LIs->getMBBStartIdx(MBB);
336360 LR = CurrLI->getLiveRangeContaining(Idx);
337 if (LR && LR->valno == ValNo && !Processed.count(LR)) {
338 if (LR->contains(RestoreIndex)) {
361 if (LR && LR->valno == ValNo) {
362 EndIdx = LIs->getMBBEndIdx(MBB);
363 if (Idx <= RestoreIndex && RestoreIndex < EndIdx) {
339364 // Spill slot live interval stops at the restore.
340 LiveRange SLR(LR->start, RestoreIndex, CurrSValNo);
365 LiveRange SLR(Idx, RestoreIndex, CurrSValNo);
341366 CurrSLI->addRange(SLR);
342 LIs->findReachableMBBs(LR->start, RestoreIndex, WorkList);
367 } else if (LR->end > EndIdx) {
368 // Live range extends beyond end of mbb, process successors.
369 LiveRange SLR(Idx, EndIdx+1, CurrSValNo);
370 CurrSLI->addRange(SLR);
371 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
372 SE = MBB->succ_end(); SI != SE; ++SI)
373 WorkList.push_back(*SI);
343374 } else {
344 LiveRange SLR(LR->start, LR->end, CurrSValNo);
375 LiveRange SLR(Idx, LR->end, CurrSValNo);
345376 CurrSLI->addRange(SLR);
346 LIs->findReachableMBBs(LR->start, LR->end, WorkList);
347377 }
348 Processed.insert(LR);
378 Processed.insert(MBB);
349379 }
350380 }
351381 }
356386 void
357387 PreAllocSplitting::UpdateRegisterInterval(VNInfo *ValNo, unsigned SpillIndex,
358388 unsigned RestoreIndex) {
389 assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
390 "Expect restore in the barrier mbb");
391
359392 SmallVector, 4> Before;
360393 SmallVector, 4> After;
361394 SmallVector BeforeKills;
379412 // Start from the restore mbb, figure out what part of the live interval
380413 // are defined by the restore.
381414 SmallVector WorkList;
382 MachineBasicBlock *MBB = LIs->getMBBFromIndex(RestoreIndex);
415 MachineBasicBlock *MBB = BarrierMBB;
383416 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
384417 SE = MBB->succ_end(); SI != SE; ++SI)
385418 WorkList.push_back(*SI);
546579 } else if (MBB == DefMBB) {
547580 // There are no uses after the def.
548581 MachineInstr *DefMI = LIs->getInstructionFromIndex(ValNo->def);
549 assert(RestoreMIs.count(DefMI) && "Not defined by a join?");
550582 if (UseMBBs.empty()) {
551583 // The only use must be below barrier in the barrier block. It's safe to
552584 // remove the def.
640672 TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
641673 SpillMI = prior(SpillPt);
642674 LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
643 } else if (!IsAvailableInStack(CurrLI->reg, RestoreIndex, SS)) {
675 } else if (!IsAvailableInStack(DefMBB, CurrLI->reg, ValNo->def,
676 RestoreIndex, SpillIndex, SS)) {
644677 // If it's already split, just restore the value. There is no need to spill
645678 // the def again.
646679 if (!DefMI)
666699 LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
667700 }
668701
702 // Remember def instruction index to spill index mapping.
703 if (DefMI && SpillMI)
704 Def2SpillMap[ValNo->def] = SpillIndex;
705
669706 // Add restore.
670707 TII->loadRegFromStackSlot(*BarrierMBB, RestorePt, CurrLI->reg, SS, RC);
671708 MachineInstr *LoadMI = prior(RestorePt);
672709 LIs->InsertMachineInstrInMaps(LoadMI, RestoreIndex);
673 RestoreMIs.insert(LoadMI);
674710
675711 // If live interval is spilled in the same block as the barrier, just
676712 // create a hole in the interval.
688724 }
689725
690726 // Update spill stack slot live interval.
691 if (SpillIndex)
692 // If value is already in stack at the restore point, there is
693 // no need to update the live interval.
694 UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1,
695 LIs->getDefIndex(RestoreIndex));
727 UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1,
728 LIs->getDefIndex(RestoreIndex));
696729
697730 // Shrink wrap the live interval by walking up the CFG and find the
698731 // new kills.
794827 // Make sure blocks are numbered in order.
795828 MF.RenumberBlocks();
796829
830 #if 0
831 // FIXME: Go top down.
832 MachineBasicBlock *Entry = MF.begin();
833 SmallPtrSet Visited;
834
835 for (df_ext_iterator >
836 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
837 DFI != E; ++DFI) {
838 BarrierMBB = *DFI;
839 for (MachineBasicBlock::iterator I = BarrierMBB->begin(),
840 E = BarrierMBB->end(); I != E; ++I) {
841 Barrier = &*I;
842 const TargetRegisterClass **BarrierRCs =
843 Barrier->getDesc().getRegClassBarriers();
844 if (!BarrierRCs)
845 continue;
846 BarrierIdx = LIs->getInstructionIndex(Barrier);
847 MadeChange |= SplitRegLiveIntervals(BarrierRCs);
848 }
849 }
850 #else
797851 for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
798852 I != E; ++I) {
799853 BarrierMBB = &*I;
808862 MadeChange |= SplitRegLiveIntervals(BarrierRCs);
809863 }
810864 }
865 #endif
811866
812867 return MadeChange;
813868 }
549549 SI.weight += Weight;
550550
551551 VNInfo *VNI;
552 if (SI.getNumValNums())
552 if (SI.hasAtLeastOneValue())
553553 VNI = SI.getValNumInfo(0);
554554 else
555555 VNI = SI.getNextValue(~0U, 0, ls_->getVNInfoAllocator());
0 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split
1
2 define i32 @main(i32 %argc, i8** %argv) nounwind {
3 entry:
4 br label %bb14.i
5
6 bb14.i: ; preds = %bb14.i, %entry
7 %i8.0.reg2mem.0.i = phi i32 [ 0, %entry ], [ %0, %bb14.i ] ; [#uses=1]
8 %0 = add i32 %i8.0.reg2mem.0.i, 1 ; [#uses=2]
9 %1 = add double 0.000000e+00, 0.000000e+00 ; [#uses=1]
10 %2 = add double 0.000000e+00, 0.000000e+00 ; [#uses=1]
11 %3 = add double 0.000000e+00, 0.000000e+00 ; [#uses=1]
12 %exitcond75.i = icmp eq i32 %0, 32 ; [#uses=1]
13 br i1 %exitcond75.i, label %bb24.i, label %bb14.i
14
15 bb24.i: ; preds = %bb14.i
16 %4 = fdiv double 0.000000e+00, 0.000000e+00 ; [#uses=1]
17 %5 = fdiv double %1, 0.000000e+00 ; [#uses=1]
18 %6 = fdiv double %2, 0.000000e+00 ; [#uses=1]
19 %7 = fdiv double %3, 0.000000e+00 ; [#uses=1]
20 br label %bb31.i
21
22 bb31.i: ; preds = %bb31.i, %bb24.i
23 %tmp.0.reg2mem.0.i = phi i32 [ 0, %bb24.i ], [ %indvar.next64.i, %bb31.i ] ; [#uses=1]
24 %indvar.next64.i = add i32 %tmp.0.reg2mem.0.i, 1 ; [#uses=2]
25 %exitcond65.i = icmp eq i32 %indvar.next64.i, 64 ; [#uses=1]
26 br i1 %exitcond65.i, label %bb33.i, label %bb31.i
27
28 bb33.i: ; preds = %bb31.i
29 br label %bb35.preheader.i
30
31 bb5.i.i: ; preds = %bb35.preheader.i
32 %8 = call double @floor(double 0.000000e+00) nounwind readnone ; [#uses=0]
33 br label %bb7.i.i
34
35 bb7.i.i: ; preds = %bb35.preheader.i, %bb5.i.i
36 br label %bb35.preheader.i
37
38 bb35.preheader.i: ; preds = %bb7.i.i, %bb33.i
39 %9 = sub double 0.000000e+00, %4 ; [#uses=1]
40 store double %9, double* null, align 8
41 %10 = sub double 0.000000e+00, %5 ; [#uses=1]
42 store double %10, double* null, align 8
43 %11 = sub double 0.000000e+00, %6 ; [#uses=1]
44 store double %11, double* null, align 8
45 %12 = sub double 0.000000e+00, %7 ; [#uses=1]
46 store double %12, double* null, align 8
47 br i1 false, label %bb7.i.i, label %bb5.i.i
48 }
49
50 declare double @floor(double) nounwind readnone
0 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
1 ; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 2
1 ; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
22
33 define i32 @t(i32 %arg) {
44 entry: