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[Hexagon][x86] add tests for bit-test; NFC More coverage for D66687 (assuming we make this a generic combine with TLI hook). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369874 91177308-0d34-0410-b5e6-96231b3b80d8 Sanjay Patel 22 days ago
2 changed file(s) with 114 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -march=hexagon < %s | FileCheck %s
1 ; RUN: llc -mtriple=hexagon < %s | FileCheck %s
22
33 ; Function Attrs: nounwind readnone
44 define i32 @f0(i32 %a0, i32 %a1) #0 {
1919 ret i32 %v3
2020 }
2121
22 define i64 @is_upper_bit_clear_i64(i64 %x) {
23 ; CHECK-LABEL: is_upper_bit_clear_i64:
24 ; CHECK: .cfi_startproc
25 ; CHECK-NEXT: // %bb.0:
26 ; CHECK-NEXT: {
27 ; CHECK-NEXT: r1:0 = extractu(r1:0,#1,#37)
28 ; CHECK-NEXT: }
29 ; CHECK-NEXT: {
30 ; CHECK-NEXT: r0 = togglebit(r0,#0)
31 ; CHECK-NEXT: r1 = #0
32 ; CHECK-NEXT: jumpr r31
33 ; CHECK-NEXT: }
34 %sh = lshr i64 %x, 37
35 %m = and i64 %sh, 1
36 %r = xor i64 %m, 1
37 ret i64 %r
38 }
39
40 define i64 @is_lower_bit_clear_i64(i64 %x) {
41 ; CHECK-LABEL: is_lower_bit_clear_i64:
42 ; CHECK: .cfi_startproc
43 ; CHECK-NEXT: // %bb.0:
44 ; CHECK-NEXT: {
45 ; CHECK-NEXT: r1:0 = extractu(r1:0,#1,#27)
46 ; CHECK-NEXT: }
47 ; CHECK-NEXT: {
48 ; CHECK-NEXT: r0 = togglebit(r0,#0)
49 ; CHECK-NEXT: r1 = #0
50 ; CHECK-NEXT: jumpr r31
51 ; CHECK-NEXT: }
52 %sh = lshr i64 %x, 27
53 %m = and i64 %sh, 1
54 %r = xor i64 %m, 1
55 ret i64 %r
56 }
57
58 define i32 @is_bit_clear_i32(i32 %x) {
59 ; CHECK-LABEL: is_bit_clear_i32:
60 ; CHECK: .cfi_startproc
61 ; CHECK-NEXT: // %bb.0:
62 ; CHECK-NEXT: {
63 ; CHECK-NEXT: r1 = #-1
64 ; CHECK-NEXT: }
65 ; CHECK-NEXT: {
66 ; CHECK-NEXT: r1 ^= lsr(r0,#27)
67 ; CHECK-NEXT: }
68 ; CHECK-NEXT: {
69 ; CHECK-NEXT: r0 = and(r1,#1)
70 ; CHECK-NEXT: jumpr r31
71 ; CHECK-NEXT: }
72 %sh = lshr i32 %x, 27
73 %n = xor i32 %sh, -1
74 %r = and i32 %n, 1
75 ret i32 %r
76 }
77
78 define i16 @is_bit_clear_i16(i16 %x) {
79 ; CHECK-LABEL: is_bit_clear_i16:
80 ; CHECK: .cfi_startproc
81 ; CHECK-NEXT: // %bb.0:
82 ; CHECK-NEXT: {
83 ; CHECK-NEXT: r1 = #-1
84 ; CHECK-NEXT: }
85 ; CHECK-NEXT: {
86 ; CHECK-NEXT: r1 ^= lsr(r0,#7)
87 ; CHECK-NEXT: }
88 ; CHECK-NEXT: {
89 ; CHECK-NEXT: r0 = and(r1,#1)
90 ; CHECK-NEXT: jumpr r31
91 ; CHECK-NEXT: }
92 %sh = lshr i16 %x, 7
93 %m = and i16 %sh, 1
94 %r = xor i16 %m, 1
95 ret i16 %r
96 }
97
98 define i8 @is_bit_clear_i8(i8 %x) {
99 ; CHECK-LABEL: is_bit_clear_i8:
100 ; CHECK: .cfi_startproc
101 ; CHECK-NEXT: // %bb.0:
102 ; CHECK-NEXT: {
103 ; CHECK-NEXT: r1 = #-1
104 ; CHECK-NEXT: }
105 ; CHECK-NEXT: {
106 ; CHECK-NEXT: r1 ^= lsr(r0,#3)
107 ; CHECK-NEXT: }
108 ; CHECK-NEXT: {
109 ; CHECK-NEXT: r0 = and(r1,#1)
110 ; CHECK-NEXT: jumpr r31
111 ; CHECK-NEXT: }
112 %sh = lshr i8 %x, 3
113 %m = and i8 %sh, 1
114 %r = xor i8 %m, 1
115 ret i8 %r
116 }
117
118
22119 attributes #0 = { nounwind readnone }
461461 ret i8 %r
462462 }
463463
464 define i8 @overshift(i64 %x) {
465 ; CHECK-LABEL: overshift:
466 ; CHECK: # %bb.0:
467 ; CHECK-NEXT: movq %rdi, %rax
468 ; CHECK-NEXT: shrq $42, %rax
469 ; CHECK-NEXT: notb %al
470 ; CHECK-NEXT: andb $1, %al
471 ; CHECK-NEXT: # kill: def $al killed $al killed $rax
472 ; CHECK-NEXT: retq
473 %a = lshr i64 %x, 42
474 %t = trunc i64 %a to i8
475 %n = xor i8 %t, -1
476 %r = and i8 %n, 1
477 ret i8 %r
478 }
479
464480 define i32 @setcc_is_bit_clear(i32 %x) {
465481 ; CHECK-LABEL: setcc_is_bit_clear:
466482 ; CHECK: # %bb.0: