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Fix spelling mistakes in MIPS target comments. NFC. Identified by Pedro Giffuni in PR27636. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287338 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 2 years ago
3 changed file(s) with 4 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
10431043 }
10441044
10451045 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1046 /// according to the given endianess.
1046 /// according to the given endianness.
10471047 static DecodeStatus readInstruction16(ArrayRef Bytes, uint64_t Address,
10481048 uint64_t &Size, uint32_t &Insn,
10491049 bool IsBigEndian) {
10631063 }
10641064
10651065 /// Read four bytes from the ArrayRef and return 32 bit word sorted
1066 /// according to the given endianess
1066 /// according to the given endianness.
10671067 static DecodeStatus readInstruction32(ArrayRef Bytes, uint64_t Address,
10681068 uint64_t &Size, uint32_t &Insn,
10691069 bool IsBigEndian, bool IsMicroMips) {
499499
500500 unsigned RegOp = OpNum;
501501 if (!Subtarget->isGP64bit()){
502 // Endianess reverses which register holds the high or low value
502 // Endianness reverses which register holds the high or low value
503503 // between M and L.
504504 switch(ExtraCode[0]) {
505505 case 'M':
6767 void MipsFunctionInfo::createISRRegFI() {
6868 // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers.
6969 // The current implementation only supports Mips32r2+ not Mips64rX. Status
70 // is always 32 bits, ErrorPC is 32 or 64 bits dependant on architecture,
70 // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture,
7171 // however Mips32r2+ is the supported architecture.
7272 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
7373