llvm.org GIT mirror llvm / 53e4471
Add NEON single-precision FP support for fabs and fneg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78101 91177308-0d34-0410-b5e6-96231b3b80d8 David Goodwin 10 years ago
5 changed file(s) with 58 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
10701070 let Inst{7-4} = opcod3;
10711071 }
10721072
1073 // Single precision, unary if no NEON
1074 // Same as ASuI except not available if NEON is enabled
1075 class ASuIn opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
1076 string opc, string asm, list pattern>
1077 : ASuI {
1078 list Predicates = [HasVFP2,DontUseNEONForFP];
1079 }
1080
10731081 // Single precision, binary
10741082 class ASbI opcod, dag oops, dag iops, string opc,
10751083 string asm, list pattern>
244244 : N2V
245245 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
246246 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
247
248 // Basic 2-register operations, scalar single-precision
249 class N2VDInts
250 : NEONFPPat<(f32 (OpNode SPR:$a)),
251 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
252 arm_ssubreg_0)>;
247253
248254 // Narrow 2-register intrinsics.
249255 class N2VNInt op24_23, bits<2> op21_20, bits<2> op19_18,
13371343 v2f32, v2f32, int_arm_neon_vabsf>;
13381344 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
13391345 v4f32, v4f32, int_arm_neon_vabsf>;
1346 def : N2VDInts;
13401347
13411348 // VQABS : Vector Saturating Absolute Value
13421349 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
13711378 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
13721379 (outs QPR:$dst), (ins QPR:$src), "vneg.f32\t$dst, $src", "",
13731380 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1381 def : N2VDInts;
13741382
13751383 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
13761384 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
167167 "fabsd", " $dst, $a",
168168 [(set DPR:$dst, (fabs DPR:$a))]>;
169169
170 def FABSS : ASuI<0b11101011, 0b0000, 0b1100, (outs SPR:$dst), (ins SPR:$a),
171 "fabss", " $dst, $a",
172 [(set SPR:$dst, (fabs SPR:$a))]>;
170 def FABSS : ASuIn<0b11101011, 0b0000, 0b1100, (outs SPR:$dst), (ins SPR:$a),
171 "fabss", " $dst, $a",
172 [(set SPR:$dst, (fabs SPR:$a))]>;
173173
174174 let Defs = [FPSCR] in {
175175 def FCMPEZD : ADuI<0b11101011, 0b0101, 0b1100, (outs), (ins DPR:$a),
207207 "fnegd", " $dst, $a",
208208 [(set DPR:$dst, (fneg DPR:$a))]>;
209209
210 def FNEGS : ASuI<0b11101011, 0b0001, 0b0100, (outs SPR:$dst), (ins SPR:$a),
211 "fnegs", " $dst, $a",
212 [(set SPR:$dst, (fneg SPR:$a))]>;
210 def FNEGS : ASuIn<0b11101011, 0b0001, 0b0100, (outs SPR:$dst), (ins SPR:$a),
211 "fnegs", " $dst, $a",
212 [(set SPR:$dst, (fneg SPR:$a))]>;
213213
214214 def FSQRTD : ADuI<0b11101011, 0b0001, 0b1100, (outs DPR:$dst), (ins DPR:$a),
215215 "fsqrtd", " $dst, $a",
0 ; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep -E {fabss\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
1 ; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | grep -E {vabs.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
2 ; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | grep -E {fabss\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
3
4 define float @test(float %a, float %b) {
5 entry:
6 %dum = fadd float %a, %b
7 %0 = tail call float @fabsf(float %dum)
8 %dum1 = fadd float %0, %b
9 ret float %dum1
10 }
11
12 declare float @fabsf(float)
0 ; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep -E {fnegs\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 2
1 ; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | grep -E {vneg.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 2
2 ; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | grep -E {fnegs\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 2
3
4 define float @test1(float* %a) {
5 entry:
6 %0 = load float* %a, align 4 ; [#uses=2]
7 %1 = fsub float -0.000000e+00, %0 ; [#uses=2]
8 %2 = fpext float %1 to double ; [#uses=1]
9 %3 = fcmp olt double %2, 1.234000e+00 ; [#uses=1]
10 %retval = select i1 %3, float %1, float %0 ; [#uses=1]
11 ret float %retval
12 }
13
14 define float @test2(float* %a) {
15 entry:
16 %0 = load float* %a, align 4 ; [#uses=2]
17 %1 = fmul float -1.000000e+00, %0 ; [#uses=2]
18 %2 = fpext float %1 to double ; [#uses=1]
19 %3 = fcmp olt double %2, 1.234000e+00 ; [#uses=1]
20 %retval = select i1 %3, float %1, float %0 ; [#uses=1]
21 ret float %retval
22 }