llvm.org GIT mirror llvm / 53c0c8b
Merge from mainline. Also update sub-register intervals after a trivial computation is rematt'ed for a copy instruction. PR2775. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_24@57706 91177308-0d34-0410-b5e6-96231b3b80d8 Tanya Lattner 10 years ago
2 changed file(s) with 52 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
455455 unsigned DefIdx = li_->getDefIndex(CopyIdx);
456456 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
457457 DLR->valno->copy = NULL;
458 // Don't forget to update sub-register intervals.
459 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
460 for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
461 if (!li_->hasInterval(*SR))
462 continue;
463 DLR = li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
464 if (DLR && DLR->valno->copy == CopyMI)
465 DLR->valno->copy = NULL;
466 }
467 }
458468
459469 MachineBasicBlock::iterator MII = CopyMI;
460470 MachineBasicBlock *MBB = CopyMI->getParent();
0 ; RUN: llvm-as < %s | llc -march=x86
1 ; PR2775
2
3 define i32 @func_77(i8 zeroext %p_79) nounwind {
4 entry:
5 %0 = tail call i32 (...)* @func_43(i32 1) nounwind ; [#uses=1]
6 %1 = icmp eq i32 %0, 0 ; [#uses=1]
7 br i1 %1, label %bb3, label %bb
8
9 bb: ; preds = %entry
10 br label %bb3
11
12 bb3: ; preds = %bb, %entry
13 %p_79_addr.0 = phi i8 [ 0, %bb ], [ %p_79, %entry ] ; [#uses=1]
14 %2 = zext i8 %p_79_addr.0 to i32 ; [#uses=2]
15 %3 = zext i1 false to i32 ; [#uses=2]
16 %4 = tail call i32 (...)* @rshift_u_s(i32 1) nounwind ; [#uses=0]
17 %5 = lshr i32 %2, %2 ; [#uses=3]
18 %6 = icmp eq i32 0, 0 ; [#uses=1]
19 br i1 %6, label %bb6, label %bb9
20
21 bb6: ; preds = %bb3
22 %7 = ashr i32 %5, %3 ; [#uses=1]
23 %8 = icmp eq i32 %7, 0 ; [#uses=1]
24 %9 = select i1 %8, i32 %3, i32 0 ; [#uses=1]
25 %. = shl i32 %5, %9 ; [#uses=1]
26 br label %bb9
27
28 bb9: ; preds = %bb6, %bb3
29 %.0 = phi i32 [ %., %bb6 ], [ %5, %bb3 ] ; [#uses=0]
30 br i1 false, label %return, label %bb10
31
32 bb10: ; preds = %bb9
33 ret i32 undef
34
35 return: ; preds = %bb9
36 ret i32 undef
37 }
38
39 declare i32 @func_43(...)
40
41 declare i32 @rshift_u_s(...)