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Large code model support for PowerPC. Large code model is identical to medium code model except that the addis/addi sequence for "local" accesses is never used. All accesses use the addis/ld sequence. The coding changes are straightforward; most of the patch is taken up with creating variants of the medium model tests for large model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175767 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Schmidt 7 years ago
15 changed file(s) with 228 addition(s) and 110 deletion(s). Raw diff Collapse all Expand all
463463 // associated TOC entry. Otherwise reference the symbol directly.
464464 TmpInst.setOpcode(PPC::LDrs);
465465 const MachineOperand &MO = MI->getOperand(1);
466 assert((MO.isGlobal() || MO.isJTI()) && "Invalid operand for LDtocL!");
466 assert((MO.isGlobal() || MO.isJTI() || MO.isCPI()) &&
467 "Invalid operand for LDtocL!");
467468 MCSymbol *MOSymbol = 0;
468469
469470 if (MO.isJTI())
470471 MOSymbol = lookUpOrCreateTOCEntry(GetJTISymbol(MO.getIndex()));
471 else {
472 else if (MO.isCPI())
473 MOSymbol = GetCPISymbol(MO.getIndex());
474 else if (MO.isGlobal()) {
472475 const GlobalValue *GValue = MO.getGlobal();
473476 const GlobalAlias *GAlias = dyn_cast(GValue);
474477 const GlobalValue *RealGValue = GAlias ?
12801280 case PPCISD::TOC_ENTRY: {
12811281 assert (PPCSubTarget.isPPC64() && "Only supported for 64-bit ABI");
12821282
1283 // For medium code model, we generate two instructions as described
1284 // below. Otherwise we allow SelectCodeCommon to handle this, selecting
1285 // one of LDtoc, LDtocJTI, and LDtocCPT.
1286 if (TM.getCodeModel() != CodeModel::Medium)
1283 // For medium and large code model, we generate two instructions as
1284 // described below. Otherwise we allow SelectCodeCommon to handle this,
1285 // selecting one of LDtoc, LDtocJTI, and LDtocCPT.
1286 CodeModel::Model CModel = TM.getCodeModel();
1287 if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
12871288 break;
12881289
12891290 // The first source operand is a TargetGlobalAddress or a
12901291 // TargetJumpTable. If it is an externally defined symbol, a symbol
12911292 // with common linkage, a function address, or a jump table address,
1292 // we generate:
1293 // or if we are generating code for large code model, we generate:
12931294 // LDtocL(, ADDIStocHA(%X2, ))
12941295 // Otherwise we generate:
12951296 // ADDItocL(ADDIStocHA(%X2, ), )
12981299 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
12991300 TOCbase, GA);
13001301
1301 if (isa(GA))
1302 if (isa(GA) || CModel == CodeModel::Large)
13021303 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
13031304 SDValue(Tmp, 0));
13041305
257257 /// or i32.
258258 LBRX,
259259
260 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium code model, produces
261 /// an ADDIS8 instruction that adds the TOC base register to sym@toc@ha.
260 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
261 /// produces an ADDIS8 instruction that adds the TOC base register to
262 /// sym@toc@ha.
262263 ADDIS_TOC_HA,
263264
264 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium code model, produces a
265 /// LD instruction with base register G8RReg and offset sym@toc@l.
266 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
265 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
266 /// produces a LD instruction with base register G8RReg and offset
267 /// sym@toc@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
267268 LD_TOC_L,
268269
269270 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
700700 def : Pat<(PPCload xaddr:$src),
701701 (LDX xaddr:$src)>;
702702
703 // Support for medium code model.
703 // Support for medium and large code model.
704704 def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp),
705705 "#ADDIStocHA",
706706 [(set G8RC:$rD,
180180 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
181181 [SDNPHasChain, SDNPMayStore]>;
182182
183 // Instructions to support medium code model
183 // Instructions to support medium and large code model
184184 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
185185 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
186186 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
0 ; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
1 ; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
12
2 ; Test correct code generation for medium code model (32-bit TOC offsets)
3 ; Test correct code generation for medium and large code model
34 ; for loading and storing an external variable.
45
56 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
None ; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
0 ; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck -check-prefix=MEDIUM %s
1 ; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck -check-prefix=LARGE %s
12
2 ; Test correct code generation for medium code model (32-bit TOC offsets)
3 ; Test correct code generation for medium and large code model
34 ; for loading and storing a static variable scoped to a function.
45
56 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
1516 ret i32 %0
1617 }
1718
18 ; CHECK: test_fn_static:
19 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
20 ; CHECK: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
21 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
22 ; CHECK: stw {{[0-9]+}}, 0([[REG2]])
23 ; CHECK: .type [[VAR]],@object
24 ; CHECK: .local [[VAR]]
25 ; CHECK: .comm [[VAR]],4,4
19 ; MEDIUM: test_fn_static:
20 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
21 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
22 ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
23 ; MEDIUM: stw {{[0-9]+}}, 0([[REG2]])
24 ; MEDIUM: .type [[VAR]],@object
25 ; MEDIUM: .local [[VAR]]
26 ; MEDIUM: .comm [[VAR]],4,4
27
28 ; LARGE: test_fn_static:
29 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
30 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
31 ; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
32 ; LARGE: stw {{[0-9]+}}, 0([[REG2]])
33 ; LARGE: .type [[VAR]],@object
34 ; LARGE: .local [[VAR]]
35 ; LARGE: .comm [[VAR]],4,4
36
None ; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
0 ; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck -check-prefix=MEDIUM %s
1 ; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck -check-prefix=LARGE %s
12
2 ; Test correct code generation for medium code model (32-bit TOC offsets)
3 ; Test correct code generation for medium and large code model
34 ; for loading and storing a file-scope static variable.
45
56 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
1516 ret i32 %0
1617 }
1718
18 ; CHECK: test_file_static:
19 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
20 ; CHECK: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
21 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
22 ; CHECK: stw {{[0-9]+}}, 0([[REG2]])
23 ; CHECK: .type [[VAR]],@object
24 ; CHECK: .data
25 ; CHECK: .globl [[VAR]]
26 ; CHECK: [[VAR]]:
27 ; CHECK: .long 5
19 ; MEDIUM: test_file_static:
20 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
21 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
22 ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
23 ; MEDIUM: stw {{[0-9]+}}, 0([[REG2]])
24 ; MEDIUM: .type [[VAR]],@object
25 ; MEDIUM: .data
26 ; MEDIUM: .globl [[VAR]]
27 ; MEDIUM: [[VAR]]:
28 ; MEDIUM: .long 5
29
30 ; LARGE: test_file_static:
31 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
32 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
33 ; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
34 ; LARGE: stw {{[0-9]+}}, 0([[REG2]])
35 ; LARGE: .type [[VAR]],@object
36 ; LARGE: .data
37 ; LARGE: .globl [[VAR]]
38 ; LARGE: [[VAR]]:
39 ; LARGE: .long 5
40
None ; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
0 ; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck -check-prefix=MEDIUM %s
1 ; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck -check-prefix=LARGE %s
12
2 ; Test correct code generation for medium code model (32-bit TOC offsets)
3 ; Test correct code generation for medium and large code model
34 ; for loading a value from the constant pool (TOC-relative).
45
56 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
1011 ret double 0x3F4FD4920B498CF0
1112 }
1213
13 ; CHECK: [[VAR:[a-z0-9A-Z_.]+]]:
14 ; CHECK: .quad 4562098671269285104
15 ; CHECK: test_double_const:
16 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
17 ; CHECK: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
18 ; CHECK: lfd {{[0-9]+}}, 0([[REG2]])
14 ; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]:
15 ; MEDIUM: .quad 4562098671269285104
16 ; MEDIUM: test_double_const:
17 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
18 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
19 ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
20
21 ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
22 ; LARGE: .quad 4562098671269285104
23 ; LARGE: test_double_const:
24 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
25 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
26 ; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
0 ; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
1 ; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
12
2 ; Test correct code generation for medium code model (32-bit TOC offsets)
3 ; Test correct code generation for medium and large code model
34 ; for loading the address of a jump table from the TOC.
45
56 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
0 ; RUN: llc -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s
1 ; RUN: llc -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s
12
2 ; Test correct code generation for medium code model (32-bit TOC offsets)
3 ; Test correct code generation for medium and large code model
34 ; for loading and storing a tentatively defined variable.
45
56 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
0 ; RUN: llc -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s
1 ; RUN: llc -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s
12
2 ; Test correct code generation for medium code model (32-bit TOC offsets)
3 ; Test correct code generation for medium and large code model
34 ; for loading a function address.
45
56 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
0 ; RUN: llc -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s
1 ; RUN: llc -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s
12
2 ; Test correct code generation for medium code model (32-bit TOC offsets)
3 ; Test correct code generation for medium and large code model
34 ; for loading a variable with available-externally linkage.
45
56 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
0 ; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
1 ; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
12
2 ; Test correct code generation for medium code model (32-bit TOC offsets)
3 ; Test correct code generation for medium and large code model
34 ; for loading and storing an aliased external variable.
45
56 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
0 ; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj %s -o - | \
1 ; RUN: elf-dump --dump-section-data | FileCheck %s
1 ; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=MEDIUM %s
2 ; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj %s -o - | \
3 ; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=LARGE %s
24
35 ; FIXME: When asm-parse is available, could make this an assembly test.
46
1820 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
1921 ; accessing external variable ei.
2022 ;
21 ; CHECK: '.rela.text'
22 ; CHECK: Relocation 0
23 ; CHECK-NEXT: 'r_offset'
24 ; CHECK-NEXT: 'r_sym', 0x[[SYM1:[0-9]+]]
25 ; CHECK-NEXT: 'r_type', 0x00000032
26 ; CHECK: Relocation 1
27 ; CHECK-NEXT: 'r_offset'
28 ; CHECK-NEXT: 'r_sym', 0x[[SYM1]]
29 ; CHECK-NEXT: 'r_type', 0x00000040
23 ; MEDIUM: '.rela.text'
24 ; MEDIUM: Relocation 0
25 ; MEDIUM-NEXT: 'r_offset'
26 ; MEDIUM-NEXT: 'r_sym', 0x[[SYM1:[0-9]+]]
27 ; MEDIUM-NEXT: 'r_type', 0x00000032
28 ; MEDIUM: Relocation 1
29 ; MEDIUM-NEXT: 'r_offset'
30 ; MEDIUM-NEXT: 'r_sym', 0x[[SYM1]]
31 ; MEDIUM-NEXT: 'r_type', 0x00000040
32 ;
33 ; LARGE: '.rela.text'
34 ; LARGE: Relocation 0
35 ; LARGE-NEXT: 'r_offset'
36 ; LARGE-NEXT: 'r_sym', 0x[[SYM1:[0-9]+]]
37 ; LARGE-NEXT: 'r_type', 0x00000032
38 ; LARGE: Relocation 1
39 ; LARGE-NEXT: 'r_offset'
40 ; LARGE-NEXT: 'r_sym', 0x[[SYM1]]
41 ; LARGE-NEXT: 'r_type', 0x00000040
3042
3143 @test_fn_static.si = internal global i32 0, align 4
3244
4153 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
4254 ; accessing function-scoped variable si.
4355 ;
44 ; CHECK: Relocation 2
45 ; CHECK-NEXT: 'r_offset'
46 ; CHECK-NEXT: 'r_sym', 0x[[SYM2:[0-9]+]]
47 ; CHECK-NEXT: 'r_type', 0x00000032
48 ; CHECK: Relocation 3
49 ; CHECK-NEXT: 'r_offset'
50 ; CHECK-NEXT: 'r_sym', 0x[[SYM2]]
51 ; CHECK-NEXT: 'r_type', 0x00000030
56 ; MEDIUM: Relocation 2
57 ; MEDIUM-NEXT: 'r_offset'
58 ; MEDIUM-NEXT: 'r_sym', 0x[[SYM2:[0-9]+]]
59 ; MEDIUM-NEXT: 'r_type', 0x00000032
60 ; MEDIUM: Relocation 3
61 ; MEDIUM-NEXT: 'r_offset'
62 ; MEDIUM-NEXT: 'r_sym', 0x[[SYM2]]
63 ; MEDIUM-NEXT: 'r_type', 0x00000030
64 ;
65 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
66 ; accessing function-scoped variable si.
67 ;
68 ; LARGE: Relocation 2
69 ; LARGE-NEXT: 'r_offset'
70 ; LARGE-NEXT: 'r_sym', 0x[[SYM2:[0-9]+]]
71 ; LARGE-NEXT: 'r_type', 0x00000032
72 ; LARGE: Relocation 3
73 ; LARGE-NEXT: 'r_offset'
74 ; LARGE-NEXT: 'r_sym', 0x[[SYM2]]
75 ; LARGE-NEXT: 'r_type', 0x00000040
5276
5377 @gi = global i32 5, align 4
5478
6387 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
6488 ; accessing file-scope variable gi.
6589 ;
66 ; CHECK: Relocation 4
67 ; CHECK-NEXT: 'r_offset'
68 ; CHECK-NEXT: 'r_sym', 0x[[SYM3:[0-9]+]]
69 ; CHECK-NEXT: 'r_type', 0x00000032
70 ; CHECK: Relocation 5
71 ; CHECK-NEXT: 'r_offset'
72 ; CHECK-NEXT: 'r_sym', 0x[[SYM3]]
73 ; CHECK-NEXT: 'r_type', 0x00000030
90 ; MEDIUM: Relocation 4
91 ; MEDIUM-NEXT: 'r_offset'
92 ; MEDIUM-NEXT: 'r_sym', 0x[[SYM3:[0-9]+]]
93 ; MEDIUM-NEXT: 'r_type', 0x00000032
94 ; MEDIUM: Relocation 5
95 ; MEDIUM-NEXT: 'r_offset'
96 ; MEDIUM-NEXT: 'r_sym', 0x[[SYM3]]
97 ; MEDIUM-NEXT: 'r_type', 0x00000030
98 ;
99 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
100 ; accessing file-scope variable gi.
101 ;
102 ; LARGE: Relocation 4
103 ; LARGE-NEXT: 'r_offset'
104 ; LARGE-NEXT: 'r_sym', 0x[[SYM3:[0-9]+]]
105 ; LARGE-NEXT: 'r_type', 0x00000032
106 ; LARGE: Relocation 5
107 ; LARGE-NEXT: 'r_offset'
108 ; LARGE-NEXT: 'r_sym', 0x[[SYM3]]
109 ; LARGE-NEXT: 'r_type', 0x00000040
74110
75111 define double @test_double_const() nounwind {
76112 entry:
80116 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
81117 ; accessing a constant.
82118 ;
83 ; CHECK: Relocation 6
84 ; CHECK-NEXT: 'r_offset'
85 ; CHECK-NEXT: 'r_sym', 0x[[SYM4:[0-9]+]]
86 ; CHECK-NEXT: 'r_type', 0x00000032
87 ; CHECK: Relocation 7
88 ; CHECK-NEXT: 'r_offset'
89 ; CHECK-NEXT: 'r_sym', 0x[[SYM4]]
90 ; CHECK-NEXT: 'r_type', 0x00000030
119 ; MEDIUM: Relocation 6
120 ; MEDIUM-NEXT: 'r_offset'
121 ; MEDIUM-NEXT: 'r_sym', 0x[[SYM4:[0-9]+]]
122 ; MEDIUM-NEXT: 'r_type', 0x00000032
123 ; MEDIUM: Relocation 7
124 ; MEDIUM-NEXT: 'r_offset'
125 ; MEDIUM-NEXT: 'r_sym', 0x[[SYM4]]
126 ; MEDIUM-NEXT: 'r_type', 0x00000030
127 ;
128 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
129 ; accessing a constant.
130 ;
131 ; LARGE: Relocation 6
132 ; LARGE-NEXT: 'r_offset'
133 ; LARGE-NEXT: 'r_sym', 0x[[SYM4:[0-9]+]]
134 ; LARGE-NEXT: 'r_type', 0x00000032
135 ; LARGE: Relocation 7
136 ; LARGE-NEXT: 'r_offset'
137 ; LARGE-NEXT: 'r_sym', 0x[[SYM4]]
138 ; LARGE-NEXT: 'r_type', 0x00000040
91139
92140 define signext i32 @test_jump_table(i32 signext %i) nounwind {
93141 entry:
136184 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
137185 ; accessing a jump table address.
138186 ;
139 ; CHECK: Relocation 8
140 ; CHECK-NEXT: 'r_offset'
141 ; CHECK-NEXT: 'r_sym', 0x[[SYM5:[0-9]+]]
142 ; CHECK-NEXT: 'r_type', 0x00000032
143 ; CHECK: Relocation 9
144 ; CHECK-NEXT: 'r_offset'
145 ; CHECK-NEXT: 'r_sym', 0x[[SYM5]]
146 ; CHECK-NEXT: 'r_type', 0x00000040
187 ; MEDIUM: Relocation 8
188 ; MEDIUM-NEXT: 'r_offset'
189 ; MEDIUM-NEXT: 'r_sym', 0x[[SYM5:[0-9]+]]
190 ; MEDIUM-NEXT: 'r_type', 0x00000032
191 ; MEDIUM: Relocation 9
192 ; MEDIUM-NEXT: 'r_offset'
193 ; MEDIUM-NEXT: 'r_sym', 0x[[SYM5]]
194 ; MEDIUM-NEXT: 'r_type', 0x00000040
195 ;
196 ; LARGE: Relocation 8
197 ; LARGE-NEXT: 'r_offset'
198 ; LARGE-NEXT: 'r_sym', 0x[[SYM5:[0-9]+]]
199 ; LARGE-NEXT: 'r_type', 0x00000032
200 ; LARGE: Relocation 9
201 ; LARGE-NEXT: 'r_offset'
202 ; LARGE-NEXT: 'r_sym', 0x[[SYM5]]
203 ; LARGE-NEXT: 'r_type', 0x00000040
147204
148205 @ti = common global i32 0, align 4
149206
158215 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
159216 ; accessing tentatively declared variable ti.
160217 ;
161 ; CHECK: Relocation 10
162 ; CHECK-NEXT: 'r_offset'
163 ; CHECK-NEXT: 'r_sym', 0x[[SYM6:[0-9]+]]
164 ; CHECK-NEXT: 'r_type', 0x00000032
165 ; CHECK: Relocation 11
166 ; CHECK-NEXT: 'r_offset'
167 ; CHECK-NEXT: 'r_sym', 0x[[SYM6]]
168 ; CHECK-NEXT: 'r_type', 0x00000040
218 ; MEDIUM: Relocation 10
219 ; MEDIUM-NEXT: 'r_offset'
220 ; MEDIUM-NEXT: 'r_sym', 0x[[SYM6:[0-9]+]]
221 ; MEDIUM-NEXT: 'r_type', 0x00000032
222 ; MEDIUM: Relocation 11
223 ; MEDIUM-NEXT: 'r_offset'
224 ; MEDIUM-NEXT: 'r_sym', 0x[[SYM6]]
225 ; MEDIUM-NEXT: 'r_type', 0x00000040
226 ;
227 ; LARGE: Relocation 10
228 ; LARGE-NEXT: 'r_offset'
229 ; LARGE-NEXT: 'r_sym', 0x[[SYM6:[0-9]+]]
230 ; LARGE-NEXT: 'r_type', 0x00000032
231 ; LARGE: Relocation 11
232 ; LARGE-NEXT: 'r_offset'
233 ; LARGE-NEXT: 'r_sym', 0x[[SYM6]]
234 ; LARGE-NEXT: 'r_type', 0x00000040
169235
170236 define i8* @test_fnaddr() nounwind {
171237 entry:
181247 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
182248 ; accessing function address foo.
183249 ;
184 ; CHECK: Relocation 12
185 ; CHECK-NEXT: 'r_offset'
186 ; CHECK-NEXT: 'r_sym', 0x[[SYM7:[0-9]+]]
187 ; CHECK-NEXT: 'r_type', 0x00000032
188 ; CHECK: Relocation 13
189 ; CHECK-NEXT: 'r_offset'
190 ; CHECK-NEXT: 'r_sym', 0x[[SYM7]]
191 ; CHECK-NEXT: 'r_type', 0x00000040
192
250 ; MEDIUM: Relocation 12
251 ; MEDIUM-NEXT: 'r_offset'
252 ; MEDIUM-NEXT: 'r_sym', 0x[[SYM7:[0-9]+]]
253 ; MEDIUM-NEXT: 'r_type', 0x00000032
254 ; MEDIUM: Relocation 13
255 ; MEDIUM-NEXT: 'r_offset'
256 ; MEDIUM-NEXT: 'r_sym', 0x[[SYM7]]
257 ; MEDIUM-NEXT: 'r_type', 0x00000040
258 ;
259 ; LARGE: Relocation 12
260 ; LARGE-NEXT: 'r_offset'
261 ; LARGE-NEXT: 'r_sym', 0x[[SYM7:[0-9]+]]
262 ; LARGE-NEXT: 'r_type', 0x00000032
263 ; LARGE: Relocation 13
264 ; LARGE-NEXT: 'r_offset'
265 ; LARGE-NEXT: 'r_sym', 0x[[SYM7]]
266 ; LARGE-NEXT: 'r_type', 0x00000040
267