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Merging r276980: ------------------------------------------------------------------------ r276980 | tstellar | 2016-07-28 07:30:43 -0700 (Thu, 28 Jul 2016) | 12 lines AMDGPU/SI: Don't use reserved VGPRs for SGPR spilling Summary: We were using reserved VGPRs for SGPR spilling and this was causing some programs with a workgroup size of 1024 to use more than 64 registers, which is illegal. Reviewers: arsenm, mareko, nhaehnle Subscribers: nhaehnle, arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D22032 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_39@277084 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 4 years ago
4 changed file(s) with 12 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
737737 MachineBasicBlock::iterator Insert = Entry.front();
738738 DebugLoc DL = Insert->getDebugLoc();
739739
740 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
740 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass,
741 *MF);
741742 if (TIDReg == AMDGPU::NoRegister)
742743 return TIDReg;
743744
202202 Spill.Lane = Lane;
203203
204204 if (!LaneVGPRs.count(LaneVGPRIdx)) {
205 unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);
205 unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass,
206 *MF);
206207
207208 if (LaneVGPR == AMDGPU::NoRegister)
208209 // We have no VGPRs left for spilling SGPRs.
956956 /// \brief Returns a register that is not used at any point in the function.
957957 /// If all registers are used, then this function will return
958958 // AMDGPU::NoRegister.
959 unsigned SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
960 const TargetRegisterClass *RC) const {
959 unsigned
960 SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
961 const TargetRegisterClass *RC,
962 const MachineFunction &MF) const {
963
961964 for (unsigned Reg : *RC)
962 if (!MRI.isPhysRegUsed(Reg))
965 if (MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg))
963966 return Reg;
964967 return AMDGPU::NoRegister;
965968 }
184184 unsigned getNumSGPRsAllowed(const SISubtarget &ST, unsigned WaveCount) const;
185185
186186 unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
187 const TargetRegisterClass *RC) const;
187 const TargetRegisterClass *RC,
188 const MachineFunction &MF) const;
188189
189190 unsigned getSGPR32PressureSet() const { return SGPR32SetID; };
190191 unsigned getVGPR32PressureSet() const { return VGPR32SetID; };