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Merging r243469: ------------------------------------------------------------------------ r243469 | vkalintiris | 2015-07-28 12:57:25 -0700 (Tue, 28 Jul 2015) | 12 lines [mips][FastISel] Fix generated code for IR's select instruction. Summary: Generate correct code for the select instruction by zero-extending it's boolean/condition operand to GPR-width. This is necessary because the conditional-move instructions operate on the whole register. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11506 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@243646 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 5 years ago
2 changed file(s) with 20 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
980980 if (!Src1Reg || !Src2Reg || !CondReg)
981981 return false;
982982
983 unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
984 if (!ZExtCondReg)
985 return false;
986
987 if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
988 return false;
989
983990 unsigned ResultReg = createResultReg(RC);
984991 unsigned TempReg = createResultReg(RC);
985992
988995
989996 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
990997 emitInst(CondMovOpc, ResultReg)
991 .addReg(Src1Reg).addReg(CondReg).addReg(TempReg);
998 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
992999 updateValueMap(I, ResultReg);
9931000 return true;
9941001 }
77 ; FIXME: The following instruction is redundant.
88 ; CHECK: xor $[[T0:[0-9]+]], $4, $zero
99 ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
10 ; CHECK-NEXT: movn $6, $5, $[[T1]]
10 ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
11 ; CHECK-NEXT: movn $6, $5, $[[T2]]
1112 ; CHECK: move $2, $6
1213 %cond = icmp ne i1 %j, 0
1314 %res = select i1 %cond, i1 %k, i1 %l
2324 ; CHECK-DAG: seb $[[T1:[0-9]+]], $zero
2425 ; CHECK: xor $[[T2:[0-9]+]], $[[T0]], $[[T1]]
2526 ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
26 ; CHECK-NEXT: movn $6, $5, $[[T3]]
27 ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1
28 ; CHECK-NEXT: movn $6, $5, $[[T4]]
2729 ; CHECK: move $2, $6
2830 %cond = icmp ne i8 %j, 0
2931 %res = select i1 %cond, i8 %k, i8 %l
3941 ; CHECK-DAG: seh $[[T1:[0-9]+]], $zero
4042 ; CHECK: xor $[[T2:[0-9]+]], $[[T0]], $[[T1]]
4143 ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
42 ; CHECK-NEXT: movn $6, $5, $[[T3]]
44 ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1
45 ; CHECK-NEXT: movn $6, $5, $[[T4]]
4346 ; CHECK: move $2, $6
4447 %cond = icmp ne i16 %j, 0
4548 %res = select i1 %cond, i16 %k, i16 %l
5356 ; FIXME: The following instruction is redundant.
5457 ; CHECK: xor $[[T0:[0-9]+]], $4, $zero
5558 ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
56 ; CHECK-NEXT: movn $6, $5, $[[T1]]
59 ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
60 ; CHECK-NEXT: movn $6, $5, $[[T2]]
5761 ; CHECK: move $2, $6
5862 %cond = icmp ne i32 %j, 0
5963 %res = select i1 %cond, i32 %k, i32 %l
6872 ; CHECK-DAG: mtc1 $5, $f1
6973 ; CHECK-DAG: xor $[[T0:[0-9]+]], $4, $zero
7074 ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
71 ; CHECK: movn.s $f0, $f1, $[[T1]]
75 ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
76 ; CHECK: movn.s $f0, $f1, $[[T2]]
7277 %cond = icmp ne i32 %j, 0
7378 %res = select i1 %cond, float %k, float %l
7479 ret float %res
8388 ; CHECK-DAG: ldc1 $f0, 16($sp)
8489 ; CHECK-DAG: xor $[[T0:[0-9]+]], $4, $zero
8590 ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
86 ; CHECK: movn.d $f0, $f2, $[[T1]]
91 ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
92 ; CHECK: movn.d $f0, $f2, $[[T2]]
8793 %cond = icmp ne i32 %j, 0
8894 %res = select i1 %cond, double %k, double %l
8995 ret double %res