llvm.org GIT mirror llvm / 532dc2e
Change getCopyToParts and getCopyFromParts to always use target-endian register ordering, for both physical and virtual registers. Update the PPC target lowering for calls to expect registers for the call result to already be in target order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38471 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 12 years ago
3 changed file(s) with 33 addition(s) and 32 deletion(s). Raw diff Collapse all Expand all
620620 unsigned NumParts,
621621 MVT::ValueType PartVT,
622622 MVT::ValueType ValueVT,
623 bool EndianOrder,
624623 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
625624 if (!MVT::isVector(ValueVT) || NumParts == 1) {
626625 SDOperand Val = Parts[0];
630629 assert(NumParts == 2 &&
631630 "Cannot expand to more than 2 elts yet!");
632631 SDOperand Hi = Parts[1];
633 if (EndianOrder && !DAG.getTargetLoweringInfo().isLittleEndian())
632 if (!DAG.getTargetLoweringInfo().isLittleEndian())
634633 std::swap(Val, Hi);
635634 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
636635 }
691690 // as appropriate.
692691 for (unsigned i = 0; i != NumParts; ++i)
693692 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
694 PartVT, IntermediateVT, EndianOrder);
693 PartVT, IntermediateVT);
695694 } else if (NumParts > 0) {
696695 // If the intermediate type was expanded, build the intermediate operands
697696 // from the parts.
700699 unsigned Factor = NumIntermediates / NumParts;
701700 for (unsigned i = 0; i != NumIntermediates; ++i)
702701 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
703 PartVT, IntermediateVT, EndianOrder);
702 PartVT, IntermediateVT);
704703 }
705704
706705 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
717716 SDOperand Val,
718717 SDOperand *Parts,
719718 unsigned NumParts,
720 MVT::ValueType PartVT,
721 bool EndianOrder) {
719 MVT::ValueType PartVT) {
722720 MVT::ValueType ValueVT = Val.getValueType();
723721
724722 if (!MVT::isVector(ValueVT) || NumParts == 1) {
727725 for (unsigned i = 0; i != NumParts; ++i)
728726 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
729727 DAG.getConstant(i, MVT::i32));
730 if (EndianOrder && !DAG.getTargetLoweringInfo().isLittleEndian())
728 if (!DAG.getTargetLoweringInfo().isLittleEndian())
731729 std::reverse(Parts, Parts + NumParts);
732730 return;
733731 }
788786 // If the register was not expanded, promote or copy the value,
789787 // as appropriate.
790788 for (unsigned i = 0; i != NumParts; ++i)
791 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT, EndianOrder);
789 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
792790 } else if (NumParts > 0) {
793791 // If the intermediate type was expanded, split each the value into
794792 // legal parts.
796794 "Must expand into a divisible number of parts!");
797795 unsigned Factor = NumParts / NumIntermediates;
798796 for (unsigned i = 0; i != NumIntermediates; ++i)
799 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT, EndianOrder);
797 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
800798 }
801799 }
802800
927925 unsigned NumParts = TLI.getNumRegisters(VT);
928926 MVT::ValueType PartVT = TLI.getRegisterType(VT);
929927 SmallVector Parts(NumParts);
930 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, true);
928 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT);
931929 for (unsigned i = 0; i < NumParts; ++i) {
932930 NewValues.push_back(Parts[i]);
933931 NewValues.push_back(DAG.getConstant(false, MVT::i32));
29512949 /// If the Flag pointer is NULL, no flag is used.
29522950 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
29532951 SDOperand &Chain, SDOperand *Flag)const{
2954 // Get the list of registers, in the appropriate order.
2955 std::vector R(Regs);
2956 if (!DAG.getTargetLoweringInfo().isLittleEndian())
2957 std::reverse(R.begin(), R.end());
2958
29592952 // Copy the legal parts from the registers.
29602953 unsigned NumParts = Regs.size();
29612954 SmallVector Parts(NumParts);
29702963 }
29712964
29722965 // Assemble the legal parts into the final value.
2973 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT, false);
2966 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
29742967 }
29752968
29762969 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
29792972 /// If the Flag pointer is NULL, no flag is used.
29802973 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
29812974 SDOperand &Chain, SDOperand *Flag) const {
2982 // Get the list of registers, in the appropriate order.
2983 std::vector R(Regs);
2984 if (!DAG.getTargetLoweringInfo().isLittleEndian())
2985 std::reverse(R.begin(), R.end());
2986
29872975 // Get the list of the values's legal parts.
29882976 unsigned NumParts = Regs.size();
29892977 SmallVector Parts(NumParts);
2990 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT, false);
2978 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
29912979
29922980 // Copy the parts into the registers.
29932981 for (unsigned i = 0; i != NumParts; ++i) {
29942982 SDOperand Part = Flag ?
2995 DAG.getCopyToReg(Chain, R[i], Parts[i], *Flag) :
2996 DAG.getCopyToReg(Chain, R[i], Parts[i]);
2983 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
2984 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
29972985 Chain = Part.getValue(0);
29982986 if (Flag)
29992987 *Flag = Part.getValue(1);
38663854 SmallVector Parts(NumParts);
38673855 for (unsigned j = 0; j != NumParts; ++j)
38683856 Parts[j] = SDOperand(Result, i++);
3869 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT, true));
3857 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT));
38703858 break;
38713859 }
38723860 }
39383926 MVT::ValueType PartVT = getRegisterType(VT);
39393927 unsigned NumParts = getNumRegisters(VT);
39403928 SmallVector Parts(NumParts);
3941 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, true);
3929 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT);
39423930 for (unsigned i = 0; i != NumParts; ++i) {
39433931 // if it isn't first piece, alignment must be 1
39443932 unsigned MyFlags = Flags;
39783966 SmallVector Results(NumRegs);
39793967 for (unsigned i = 0; i != NumRegs; ++i)
39803968 Results[i] = Res.getValue(i);
3981 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, false, AssertOp);
3969 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp);
39823970 }
39833971
39843972 return std::make_pair(Res, Chain);
42684256 SmallVector Chains(NumRegs);
42694257
42704258 // Copy the value by legal parts into sequential virtual registers.
4271 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT, false);
4259 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
42724260 for (unsigned i = 0; i != NumRegs; ++i)
42734261 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
42744262 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
44054393 if (TI->getNumSuccessors())
44064394 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
44074395
4408 // Check successor nodes PHI nodes that expect a constant to be available from
4409 // this block.
4396 // Check successor nodes' PHI nodes that expect a constant to be available
4397 // from this block.
44104398 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
44114399 BasicBlock *SuccBB = TI->getSuccessor(succ);
44124400 if (!isa(SuccBB->begin())) continue;
17731773 case MVT::Other: break;
17741774 case MVT::i32:
17751775 if (Op.Val->getValueType(1) == MVT::i32) {
1776 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1);
1776 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
17771777 ResultVals[0] = Chain.getValue(0);
1778 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32,
1778 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32,
17791779 Chain.getValue(2)).getValue(1);
17801780 ResultVals[1] = Chain.getValue(0);
17811781 NumResults = 2;
0 ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
1 ; RUN: grep {addic 4, 4, 1}
2 ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
3 ; RUN: grep {addze 3, 3}
4
5 declare i64 @foo();
6
7 define i64 @bar()
8 {
9 %t = call i64 @foo()
10 %s = add i64 %t, 1
11 ret i64 %s
12 }