llvm.org GIT mirror llvm / 52e96d1
Merging r318207: ------------------------------------------------------------------------ r318207 | sdardis | 2017-11-14 22:26:42 +0000 (Tue, 14 Nov 2017) | 18 lines Reland "[mips][mt][6/7] Add support for mftr, mttr instructions." This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318386 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Dardis 1 year, 9 months ago
16 changed file(s) with 549 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
302302
303303 bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
304304 const MCSubtargetInfo *STI);
305
306 bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
307 const MCSubtargetInfo *STI);
305308
306309 bool reportParseError(Twine ErrorMsg);
307310 bool reportParseError(SMLoc Loc, Twine ErrorMsg);
25102513 return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
25112514 case Mips::SEQIMacro:
25122515 return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2516 case Mips::MFTC0: case Mips::MTTC0:
2517 case Mips::MFTGPR: case Mips::MTTGPR:
2518 case Mips::MFTLO: case Mips::MTTLO:
2519 case Mips::MFTHI: case Mips::MTTHI:
2520 case Mips::MFTACX: case Mips::MTTACX:
2521 case Mips::MFTDSP: case Mips::MTTDSP:
2522 case Mips::MFTC1: case Mips::MTTC1:
2523 case Mips::MFTHC1: case Mips::MTTHC1:
2524 case Mips::CFTC1: case Mips::CTTC1:
2525 return expandMXTRAlias(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
25132526 }
25142527 }
25152528
48784891 Imm, IDLoc, STI);
48794892 TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(),
48804893 Inst.getOperand(0).getReg(), 1, IDLoc, STI);
4894 return false;
4895 }
4896
4897 // Map the DSP accumulator and control register to the corresponding gpr
4898 // operand. Unlike the other alias, the m(f|t)t(lo|hi|acx) instructions
4899 // do not map the DSP registers contigously to gpr registers.
4900 static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
4901 switch (Inst.getOpcode()) {
4902 case Mips::MFTLO:
4903 case Mips::MTTLO:
4904 switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
4905 case Mips::AC0:
4906 return Mips::ZERO;
4907 case Mips::AC1:
4908 return Mips::A0;
4909 case Mips::AC2:
4910 return Mips::T0;
4911 case Mips::AC3:
4912 return Mips::T4;
4913 default:
4914 llvm_unreachable("Unknown register for 'mttr' alias!");
4915 }
4916 case Mips::MFTHI:
4917 case Mips::MTTHI:
4918 switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
4919 case Mips::AC0:
4920 return Mips::AT;
4921 case Mips::AC1:
4922 return Mips::A1;
4923 case Mips::AC2:
4924 return Mips::T1;
4925 case Mips::AC3:
4926 return Mips::T5;
4927 default:
4928 llvm_unreachable("Unknown register for 'mttr' alias!");
4929 }
4930 case Mips::MFTACX:
4931 case Mips::MTTACX:
4932 switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
4933 case Mips::AC0:
4934 return Mips::V0;
4935 case Mips::AC1:
4936 return Mips::A2;
4937 case Mips::AC2:
4938 return Mips::T2;
4939 case Mips::AC3:
4940 return Mips::T6;
4941 default:
4942 llvm_unreachable("Unknown register for 'mttr' alias!");
4943 }
4944 case Mips::MFTDSP:
4945 case Mips::MTTDSP:
4946 return Mips::S0;
4947 default:
4948 llvm_unreachable("Unknown instruction for 'mttr' dsp alias!");
4949 }
4950 }
4951
4952 // Map the floating point register operand to the corresponding register
4953 // operand.
4954 static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) {
4955 switch (Inst.getOperand(IsMFTC1 ? 1 : 0).getReg()) {
4956 case Mips::F0: return Mips::ZERO;
4957 case Mips::F1: return Mips::AT;
4958 case Mips::F2: return Mips::V0;
4959 case Mips::F3: return Mips::V1;
4960 case Mips::F4: return Mips::A0;
4961 case Mips::F5: return Mips::A1;
4962 case Mips::F6: return Mips::A2;
4963 case Mips::F7: return Mips::A3;
4964 case Mips::F8: return Mips::T0;
4965 case Mips::F9: return Mips::T1;
4966 case Mips::F10: return Mips::T2;
4967 case Mips::F11: return Mips::T3;
4968 case Mips::F12: return Mips::T4;
4969 case Mips::F13: return Mips::T5;
4970 case Mips::F14: return Mips::T6;
4971 case Mips::F15: return Mips::T7;
4972 case Mips::F16: return Mips::S0;
4973 case Mips::F17: return Mips::S1;
4974 case Mips::F18: return Mips::S2;
4975 case Mips::F19: return Mips::S3;
4976 case Mips::F20: return Mips::S4;
4977 case Mips::F21: return Mips::S5;
4978 case Mips::F22: return Mips::S6;
4979 case Mips::F23: return Mips::S7;
4980 case Mips::F24: return Mips::T8;
4981 case Mips::F25: return Mips::T9;
4982 case Mips::F26: return Mips::K0;
4983 case Mips::F27: return Mips::K1;
4984 case Mips::F28: return Mips::GP;
4985 case Mips::F29: return Mips::SP;
4986 case Mips::F30: return Mips::FP;
4987 case Mips::F31: return Mips::RA;
4988 default: llvm_unreachable("Unknown register for mttc1 alias!");
4989 }
4990 }
4991
4992 // Map the coprocessor operand the corresponding gpr register operand.
4993 static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) {
4994 switch (Inst.getOperand(IsMFTC0 ? 1 : 0).getReg()) {
4995 case Mips::COP00: return Mips::ZERO;
4996 case Mips::COP01: return Mips::AT;
4997 case Mips::COP02: return Mips::V0;
4998 case Mips::COP03: return Mips::V1;
4999 case Mips::COP04: return Mips::A0;
5000 case Mips::COP05: return Mips::A1;
5001 case Mips::COP06: return Mips::A2;
5002 case Mips::COP07: return Mips::A3;
5003 case Mips::COP08: return Mips::T0;
5004 case Mips::COP09: return Mips::T1;
5005 case Mips::COP010: return Mips::T2;
5006 case Mips::COP011: return Mips::T3;
5007 case Mips::COP012: return Mips::T4;
5008 case Mips::COP013: return Mips::T5;
5009 case Mips::COP014: return Mips::T6;
5010 case Mips::COP015: return Mips::T7;
5011 case Mips::COP016: return Mips::S0;
5012 case Mips::COP017: return Mips::S1;
5013 case Mips::COP018: return Mips::S2;
5014 case Mips::COP019: return Mips::S3;
5015 case Mips::COP020: return Mips::S4;
5016 case Mips::COP021: return Mips::S5;
5017 case Mips::COP022: return Mips::S6;
5018 case Mips::COP023: return Mips::S7;
5019 case Mips::COP024: return Mips::T8;
5020 case Mips::COP025: return Mips::T9;
5021 case Mips::COP026: return Mips::K0;
5022 case Mips::COP027: return Mips::K1;
5023 case Mips::COP028: return Mips::GP;
5024 case Mips::COP029: return Mips::SP;
5025 case Mips::COP030: return Mips::FP;
5026 case Mips::COP031: return Mips::RA;
5027 default: llvm_unreachable("Unknown register for mttc0 alias!");
5028 }
5029 }
5030
5031 /// Expand an alias of 'mftr' or 'mttr' into the full instruction, by producing
5032 /// an mftr or mttr with the correctly mapped gpr register, u, sel and h bits.
5033 bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5034 const MCSubtargetInfo *STI) {
5035 MipsTargetStreamer &TOut = getTargetStreamer();
5036 unsigned rd = 0;
5037 unsigned u = 1;
5038 unsigned sel = 0;
5039 unsigned h = 0;
5040 bool IsMFTR = false;
5041 switch (Inst.getOpcode()) {
5042 case Mips::MFTC0:
5043 IsMFTR = true;
5044 LLVM_FALLTHROUGH;
5045 case Mips::MTTC0:
5046 u = 0;
5047 rd = getRegisterForMxtrC0(Inst, IsMFTR);
5048 sel = Inst.getOperand(2).getImm();
5049 break;
5050 case Mips::MFTGPR:
5051 IsMFTR = true;
5052 LLVM_FALLTHROUGH;
5053 case Mips::MTTGPR:
5054 rd = Inst.getOperand(IsMFTR ? 1 : 0).getReg();
5055 break;
5056 case Mips::MFTLO:
5057 case Mips::MFTHI:
5058 case Mips::MFTACX:
5059 case Mips::MFTDSP:
5060 IsMFTR = true;
5061 LLVM_FALLTHROUGH;
5062 case Mips::MTTLO:
5063 case Mips::MTTHI:
5064 case Mips::MTTACX:
5065 case Mips::MTTDSP:
5066 rd = getRegisterForMxtrDSP(Inst, IsMFTR);
5067 sel = 1;
5068 break;
5069 case Mips::MFTHC1:
5070 h = 1;
5071 LLVM_FALLTHROUGH;
5072 case Mips::MFTC1:
5073 IsMFTR = true;
5074 rd = getRegisterForMxtrFP(Inst, IsMFTR);
5075 sel = 2;
5076 break;
5077 case Mips::MTTHC1:
5078 h = 1;
5079 LLVM_FALLTHROUGH;
5080 case Mips::MTTC1:
5081 rd = getRegisterForMxtrFP(Inst, IsMFTR);
5082 sel = 2;
5083 break;
5084 case Mips::CFTC1:
5085 IsMFTR = true;
5086 LLVM_FALLTHROUGH;
5087 case Mips::CTTC1:
5088 rd = getRegisterForMxtrFP(Inst, IsMFTR);
5089 sel = 3;
5090 break;
5091 }
5092 unsigned Op0 = IsMFTR ? Inst.getOperand(0).getReg() : rd;
5093 unsigned Op1 =
5094 IsMFTR ? rd
5095 : (Inst.getOpcode() != Mips::MTTDSP ? Inst.getOperand(1).getReg()
5096 : Inst.getOperand(0).getReg());
5097
5098 TOut.emitRRIII(IsMFTR ? Mips::MFTR : Mips::MTTR, Op0, Op1, u, sel, h, IDLoc,
5099 STI);
48815100 return false;
48825101 }
48835102
190190 int16_t Imm, SMLoc IDLoc,
191191 const MCSubtargetInfo *STI) {
192192 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
193 }
194
195 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
196 unsigned Reg1, int16_t Imm0, int16_t Imm1,
197 int16_t Imm2, SMLoc IDLoc,
198 const MCSubtargetInfo *STI) {
199 MCInst TmpInst;
200 TmpInst.setOpcode(Opcode);
201 TmpInst.addOperand(MCOperand::createReg(Reg0));
202 TmpInst.addOperand(MCOperand::createReg(Reg1));
203 TmpInst.addOperand(MCOperand::createImm(Imm0));
204 TmpInst.addOperand(MCOperand::createImm(Imm1));
205 TmpInst.addOperand(MCOperand::createImm(Imm2));
206 TmpInst.setLoc(IDLoc);
207 getStreamer().EmitInstruction(TmpInst, *STI);
193208 }
194209
195210 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
3434 def FIELD5_1_DMT_EMT : FIELD5<0b00001>;
3535 def FIELD5_2_DMT_EMT : FIELD5<0b01111>;
3636 def FIELD5_1_2_DVPE_EVPE : FIELD5<0b00000>;
37 def FIELD5_MFTR : FIELD5<0b01000>;
38 def FIELD5_MTTR : FIELD5<0b01100>;
3739
3840 class COP0_MFMC0_MT : MipsMTInst {
3941 bits<32> Inst;
4749 let Inst{5} = sc.Value;
4850 let Inst{4-3} = 0b00;
4951 let Inst{2-0} = 0b001;
52 }
53
54 class COP0_MFTTR_MT : MipsMTInst {
55 bits<32> Inst;
56
57 bits<5> rt;
58 bits<5> rd;
59 bits<1> u;
60 bits<1> h;
61 bits<3> sel;
62 let Inst{31-26} = 0b010000; // COP0
63 let Inst{25-21} = Op.Value; // MFMC0
64 let Inst{20-16} = rt;
65 let Inst{15-11} = rd;
66 let Inst{10-6} = 0b00000; // rx - currently unsupported.
67 let Inst{5} = u;
68 let Inst{4} = h;
69 let Inst{3} = 0b0;
70 let Inst{2-0} = sel;
5071 }
5172
5273 class SPECIAL3_MT_FORK : MipsMTInst {
55 // License. See LICENSE.TXT for details.
66 //
77 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the MIPS MT ASE as defined by MD00378 1.12.
10 //
11 // TODO: Add support for the microMIPS encodings for the MT ASE and add the
12 // instruction mappings.
13 //
14 //===----------------------------------------------------------------------===//
815
916 //===----------------------------------------------------------------------===//
1017 // MIPS MT Instruction Encodings
2532 class FORK_ENC : SPECIAL3_MT_FORK;
2633
2734 class YIELD_ENC : SPECIAL3_MT_YIELD;
35
36 class MFTR_ENC : COP0_MFTTR_MT;
37
38 class MTTR_ENC : COP0_MFTTR_MT;
2839
2940 //===----------------------------------------------------------------------===//
3041 // MIPS MT Instruction Descriptions
3849 InstrItinClass Itinerary = Itin;
3950 }
4051
52 class MFTR_DESC {
53 dag OutOperandList = (outs GPR32Opnd:$rd);
54 dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h);
55 string AsmString = "mftr\t$rd, $rt, $u, $sel, $h";
56 list Pattern = [];
57 InstrItinClass Itinerary = II_MFTR;
58 }
59
60 class MTTR_DESC {
61 dag OutOperandList = (outs GPR32Opnd:$rd);
62 dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h);
63 string AsmString = "mttr\t$rt, $rd, $u, $sel, $h";
64 list Pattern = [];
65 InstrItinClass Itinerary = II_MTTR;
66 }
67
4168 class FORK_DESC {
4269 dag OutOperandList = (outs GPR32Opnd:$rs, GPR32Opnd:$rd);
4370 dag InOperandList = (ins GPR32Opnd:$rt);
78105 def FORK : FORK_ENC, FORK_DESC, ASE_MT;
79106
80107 def YIELD : YIELD_ENC, YIELD_DESC, ASE_MT;
81 }
108
109 def MFTR : MFTR_ENC, MFTR_DESC, ASE_MT;
110
111 def MTTR : MTTR_ENC, MTTR_DESC, ASE_MT;
112 }
113
114 //===----------------------------------------------------------------------===//
115 // MIPS MT Pseudo Instructions - used to support mtfr & mttr aliases.
116 //===----------------------------------------------------------------------===//
117 def MFTC0 : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins COP0Opnd:$rt,
118 uimm3:$sel),
119 "mftc0 $rd, $rt, $sel">, ASE_MT;
120
121 def MFTGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rt,
122 uimm3:$sel),
123 "mftgpr $rd, $rt">, ASE_MT;
124
125 def MFTLO : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),
126 "mftlo $rt, $ac">, ASE_MT;
127
128 def MFTHI : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),
129 "mfthi $rt, $ac">, ASE_MT;
130
131 def MFTACX : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),
132 "mftacx $rt, $ac">, ASE_MT;
133
134 def MFTDSP : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins),
135 "mftdsp $rt">, ASE_MT;
136
137 def MFTC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGR32Opnd:$ft),
138 "mftc1 $rt, $ft">, ASE_MT;
139
140 def MFTHC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGR32Opnd:$ft),
141 "mfthc1 $rt, $ft">, ASE_MT;
142
143 def CFTC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGRCCOpnd:$ft),
144 "cftc1 $rt, $ft">, ASE_MT;
145
146
147 def MTTC0 : MipsAsmPseudoInst<(outs COP0Opnd:$rd), (ins GPR32Opnd:$rt,
148 uimm3:$sel),
149 "mttc0 $rt, $rd, $sel">, ASE_MT;
150
151 def MTTGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins GPR32Opnd:$rd),
152 "mttgpr $rd, $rt">, ASE_MT;
153
154 def MTTLO : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),
155 "mttlo $rt, $ac">, ASE_MT;
156
157 def MTTHI : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),
158 "mtthi $rt, $ac">, ASE_MT;
159
160 def MTTACX : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),
161 "mttacx $rt, $ac">, ASE_MT;
162
163 def MTTDSP : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rt),
164 "mttdsp $rt">, ASE_MT;
165
166 def MTTC1 : MipsAsmPseudoInst<(outs FGR32Opnd:$ft), (ins GPR32Opnd:$rt),
167 "mttc1 $rt, $ft">, ASE_MT;
168
169 def MTTHC1 : MipsAsmPseudoInst<(outs FGR32Opnd:$ft), (ins GPR32Opnd:$rt),
170 "mtthc1 $rt, $ft">, ASE_MT;
171
172 def CTTC1 : MipsAsmPseudoInst<(outs FGRCCOpnd:$ft), (ins GPR32Opnd:$rt),
173 "cttc1 $rt, $ft">, ASE_MT;
82174
83175 //===----------------------------------------------------------------------===//
84176 // MIPS MT Instruction Definitions
94186 def : MipsInstAlias<"evpe", (EVPE ZERO), 1>, ASE_MT;
95187
96188 def : MipsInstAlias<"yield $rs", (YIELD ZERO, GPR32Opnd:$rs), 1>, ASE_MT;
97 }
189
190 def : MipsInstAlias<"mftc0 $rd, $rt", (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0),
191 1>, ASE_MT;
192
193 def : MipsInstAlias<"mftlo $rt", (MFTLO GPR32Opnd:$rt, AC0), 1>, ASE_MT;
194
195 def : MipsInstAlias<"mfthi $rt", (MFTHI GPR32Opnd:$rt, AC0), 1>, ASE_MT;
196
197 def : MipsInstAlias<"mftacx $rt", (MFTACX GPR32Opnd:$rt, AC0), 1>, ASE_MT;
198
199 def : MipsInstAlias<"mttc0 $rd, $rt", (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0),
200 1>, ASE_MT;
201
202 def : MipsInstAlias<"mttlo $rt", (MTTLO AC0, GPR32Opnd:$rt), 1>, ASE_MT;
203
204 def : MipsInstAlias<"mtthi $rt", (MTTHI AC0, GPR32Opnd:$rt), 1>, ASE_MT;
205
206 def : MipsInstAlias<"mttacx $rt", (MTTACX AC0, GPR32Opnd:$rt), 1>, ASE_MT;
207 }
225225 def II_MFHC1 : InstrItinClass;
226226 def II_MFC2 : InstrItinClass;
227227 def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo
228 def II_MFTR : InstrItinClass;
228229 def II_MOD : InstrItinClass;
229230 def II_MODU : InstrItinClass;
230231 def II_MOVE : InstrItinClass;
254255 def II_MTHC1 : InstrItinClass;
255256 def II_MTC2 : InstrItinClass;
256257 def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo
258 def II_MTTR : InstrItinClass;
257259 def II_MUL : InstrItinClass;
258260 def II_MUH : InstrItinClass;
259261 def II_MUHU : InstrItinClass;
663665 InstrItinData]>,
664666 InstrItinData]>,
665667 InstrItinData]>,
668 InstrItinData]>,
666669 InstrItinData]>,
667670 InstrItinData]>,
668671 InstrItinData]>,
669672 InstrItinData]>,
670673 InstrItinData]>,
671674 InstrItinData]>,
675 InstrItinData]>,
672676 InstrItinData]>,
673677 InstrItinData]>,
674678 InstrItinData]>,
267267 // MIPS MT instructions
268268 // ====================
269269
270 def : ItinRW<[GenericWriteMove], [II_DMT, II_DVPE, II_EMT, II_EVPE]>;
270 def : ItinRW<[GenericWriteMove], [II_DMT, II_DVPE, II_EMT, II_EVPE, II_MFTR,
271 II_MTTR]>;
271272
272273 def : ItinRW<[GenericReadWriteCOP0Long], [II_YIELD]>;
274
273275 def : ItinRW<[GenericWriteCOP0Short], [II_FORK]>;
274276
275277 // MIPS32R6 and MIPS16e
118118 SMLoc IDLoc, const MCSubtargetInfo *STI);
119119 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
120120 SMLoc IDLoc, const MCSubtargetInfo *STI);
121 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
122 int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
123 const MCSubtargetInfo *STI);
121124 void emitAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, bool Is64Bit,
122125 const MCSubtargetInfo *STI);
123126 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
99 0x08 0x10 0x65 0x7c # CHECK: fork $2, $3, $5
1010 0x09 0x00 0x80 0x7c # CHECK: yield $4
1111 0x09 0x20 0xa0 0x7c # CHECK: yield $4, $5
12
12 0x02 0x20 0x05 0x41 # CHECK: mftr $4, $5, 0, 2, 0
13 0x20 0x20 0x05 0x41 # CHECK: mftr $4, $5, 1, 0, 0
14 0x21 0x20 0x00 0x41 # CHECK: mftr $4, $zero, 1, 1, 0
15 0x21 0x20 0x0a 0x41 # CHECK: mftr $4, $10, 1, 1, 0
16 0x22 0x20 0x0a 0x41 # CHECK: mftr $4, $10, 1, 2, 0
17 0x32 0x20 0x0a 0x41 # CHECK: mftr $4, $10, 1, 2, 1
18 0x23 0x20 0x1a 0x41 # CHECK: mftr $4, $26, 1, 3, 0
19 0x23 0x20 0x1f 0x41 # CHECK: mftr $4, $ra, 1, 3, 0
20 0x24 0x20 0x0e 0x41 # CHECK: mftr $4, $14, 1, 4, 0
21 0x25 0x20 0x0f 0x41 # CHECK: mftr $4, $15, 1, 5, 0
22 0x02 0x28 0x84 0x41 # CHECK: mttr $4, $5, 0, 2, 0
23 0x20 0x28 0x84 0x41 # CHECK: mttr $4, $5, 1, 0, 0
24 0x21 0x00 0x84 0x41 # CHECK: mttr $4, $zero, 1, 1, 0
25 0x21 0x50 0x84 0x41 # CHECK: mttr $4, $10, 1, 1, 0
26 0x22 0x50 0x84 0x41 # CHECK: mttr $4, $10, 1, 2, 0
27 0x32 0x50 0x84 0x41 # CHECK: mttr $4, $10, 1, 2, 1
28 0x23 0xd0 0x84 0x41 # CHECK: mttr $4, $26, 1, 3, 0
29 0x23 0xf8 0x84 0x41 # CHECK: mttr $4, $ra, 1, 3, 0
30 0x24 0x70 0x84 0x41 # CHECK: mttr $4, $14, 1, 4, 0
31 0x25 0x78 0x84 0x41 # CHECK: mttr $4, $15, 1, 5, 0
99 0x7c 0x65 0x10 0x08 # CHECK: fork $2, $3, $5
1010 0x7c 0x80 0x00 0x09 # CHECK: yield $4
1111 0x7c 0xa0 0x20 0x09 # CHECK: yield $4, $5
12
12 0x41 0x05 0x20 0x02 # CHECK: mftr $4, $5, 0, 2, 0
13 0x41 0x05 0x20 0x20 # CHECK: mftr $4, $5, 1, 0, 0
14 0x41 0x00 0x20 0x21 # CHECK: mftr $4, $zero, 1, 1, 0
15 0x41 0x0a 0x20 0x21 # CHECK: mftr $4, $10, 1, 1, 0
16 0x41 0x0a 0x20 0x22 # CHECK: mftr $4, $10, 1, 2, 0
17 0x41 0x0a 0x20 0x32 # CHECK: mftr $4, $10, 1, 2, 1
18 0x41 0x1a 0x20 0x23 # CHECK: mftr $4, $26, 1, 3, 0
19 0x41 0x1f 0x20 0x23 # CHECK: mftr $4, $ra, 1, 3, 0
20 0x41 0x0e 0x20 0x24 # CHECK: mftr $4, $14, 1, 4, 0
21 0x41 0x0f 0x20 0x25 # CHECK: mftr $4, $15, 1, 5, 0
22 0x41 0x84 0x28 0x02 # CHECK: mttr $4, $5, 0, 2, 0
23 0x41 0x84 0x28 0x20 # CHECK: mttr $4, $5, 1, 0, 0
24 0x41 0x84 0x00 0x21 # CHECK: mttr $4, $zero, 1, 1, 0
25 0x41 0x84 0x50 0x21 # CHECK: mttr $4, $10, 1, 1, 0
26 0x41 0x84 0x50 0x22 # CHECK: mttr $4, $10, 1, 2, 0
27 0x41 0x84 0x50 0x32 # CHECK: mttr $4, $10, 1, 2, 1
28 0x41 0x84 0xd0 0x23 # CHECK: mttr $4, $26, 1, 3, 0
29 0x41 0x84 0xf8 0x23 # CHECK: mttr $4, $ra, 1, 3, 0
30 0x41 0x84 0x70 0x24 # CHECK: mttr $4, $14, 1, 4, 0
31 0x41 0x84 0x78 0x25 # CHECK: mttr $4, $15, 1, 5, 0
0 # RUN: not llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt < %s 2>%t1
1 # RUN: FileCheck %s < %t1
2 mftr 0($4), $5, 0, 0, 0 # CHECK: error: unexpected token in argument list
3 mttr 0($4), $5, 0, 0, 0 # CHECK: error: unexpected token in argument list
1010 evpe 4 # CHECK: error: invalid operand for instruction
1111 evpe $4, $5 # CHECK: error: invalid operand for instruction
1212 evpe $5, 0($5) # CHECK: error: invalid operand for instruction
13 # FIXME: add tests for mftr/mttr.
0 # RUN: not llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s 2>%t1
1 # RUN: FileCheck %s < %t1
2
3 # The integrated assembler produces a wrong or misleading error message.
4
5 mftc0 0($4), $5 # CHECK: error: unexpected token in argument list
6 mftc0 0($4), $5, 1 # CHECK: error: unexpected token in argument list
7 mftgpr 0($4), $5 # CHECK: error: unexpected token in argument list
8 mftlo 0($3) # CHECK: error: unexpected token in argument list
9 mftlo 0($3), $ac1 # CHECK: error: unexpected token in argument list
10 mfthi 0($3) # CHECK: error: unexpected token in argument list
11 mfthi 0($3), $ac1 # CHECK: error: unexpected token in argument list
12 mftacx 0($3) # CHECK: error: unexpected token in argument list
13 mftacx 0($3), $ac1 # CHECK: error: unexpected token in argument list
14 mftdsp 0($4) # CHECK: error: unexpected token in argument list
15 mftc1 0($4), $f4 # CHECK: error: unexpected token in argument list
16 mfthc1 0($4), $f4 # CHECK: error: unexpected token in argument list
17 cftc1 0($4), $f8 # CHECK: error: unexpected token in argument list
0 # RUN: not llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s 2>%t1
1 # RUN: FileCheck %s < %t1
2
3 mftc0 $4, 0($5) # CHECK: error: invalid operand for instruction
4 mftc0 $4, 0($5), 1 # CHECK: error: invalid operand for instruction
5 mftc0 $4, $5, -1 # CHECK: error: expected 3-bit unsigned immediate
6 mftc0 $4, $5, 9 # CHECK: error: expected 3-bit unsigned immediate
7 mftc0 $4, $5, $6 # CHECK: error: expected 3-bit unsigned immediate
8 mftgpr $4, 0($5) # CHECK: error: invalid operand for instruction
9 mftgpr $4, $5, $6 # CHECK: error: invalid operand for instruction
10 mftlo $3, 0($ac1) # CHECK: error: invalid operand for instruction
11 mftlo $4, $ac1, $4 # CHECK: error: invalid operand for instruction
12 mfthi $3, 0($ac1) # CHECK: error: invalid operand for instruction
13 mfthi $4, $ac1, $4 # CHECK: error: invalid operand for instruction
14 mftacx $3, 0($ac1) # CHECK: error: invalid operand for instruction
15 mftacx $4, $ac1, $4 # CHECK: error: invalid operand for instruction
16 mftdsp $4, $5 # CHECK: error: invalid operand for instruction
17 mftdsp $4, $f5 # CHECK: error: invalid operand for instruction
18 mftdsp $4, $ac0 # CHECK: error: invalid operand for instruction
19 mftc1 $4, 0($f4) # CHECK: error: invalid operand for instruction
20 mfthc1 $4, 0($f4) # CHECK: error: invalid operand for instruction
21 cftc1 $4, 0($f4) # CHECK: error: invalid operand for instruction
22 cftc1 $4, $f4, $5 # CHECK: error: invalid operand for instruction
0 # RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s | FileCheck %s
1
2 # Check the various aliases of the m[ft]tr instruction.
3
4 mftc0 $4, $5 # CHECK: mftr $4, $5, 0, 0, 0 # encoding: [0x41,0x05,0x20,0x00]
5 mftc0 $6, $7, 1 # CHECK: mftr $6, $7, 0, 1, 0 # encoding: [0x41,0x07,0x30,0x01]
6 mftgpr $5, $9 # CHECK: mftr $5, $9, 1, 0, 0 # encoding: [0x41,0x09,0x28,0x20]
7 mftlo $3 # CHECK: mftr $3, $zero, 1, 1, 0 # encoding: [0x41,0x00,0x18,0x21]
8 mftlo $3, $ac0 # CHECK: mftr $3, $zero, 1, 1, 0 # encoding: [0x41,0x00,0x18,0x21]
9 mftlo $3, $ac1 # CHECK: mftr $3, $4, 1, 1, 0 # encoding: [0x41,0x04,0x18,0x21]
10 mftlo $3, $ac2 # CHECK: mftr $3, $8, 1, 1, 0 # encoding: [0x41,0x08,0x18,0x21]
11 mftlo $3, $ac3 # CHECK: mftr $3, $12, 1, 1, 0 # encoding: [0x41,0x0c,0x18,0x21]
12 mfthi $3, $ac0 # CHECK: mftr $3, $1, 1, 1, 0 # encoding: [0x41,0x01,0x18,0x21]
13 mfthi $3, $ac1 # CHECK: mftr $3, $5, 1, 1, 0 # encoding: [0x41,0x05,0x18,0x21]
14 mfthi $3, $ac2 # CHECK: mftr $3, $9, 1, 1, 0 # encoding: [0x41,0x09,0x18,0x21]
15 mfthi $3, $ac3 # CHECK: mftr $3, $13, 1, 1, 0 # encoding: [0x41,0x0d,0x18,0x21]
16 mftacx $3, $ac0 # CHECK: mftr $3, $2, 1, 1, 0 # encoding: [0x41,0x02,0x18,0x21]
17 mftacx $3, $ac1 # CHECK: mftr $3, $6, 1, 1, 0 # encoding: [0x41,0x06,0x18,0x21]
18 mftacx $3, $ac2 # CHECK: mftr $3, $10, 1, 1, 0 # encoding: [0x41,0x0a,0x18,0x21]
19 mftacx $3, $ac3 # CHECK: mftr $3, $14, 1, 1, 0 # encoding: [0x41,0x0e,0x18,0x21]
20 mftdsp $4 # CHECK: mftr $4, $16, 1, 1, 0 # encoding: [0x41,0x10,0x20,0x21]
21 mftc1 $4, $f5 # CHECK: mftr $4, $5, 1, 2, 0 # encoding: [0x41,0x05,0x20,0x22]
22 mfthc1 $4, $f5 # CHECK: mftr $4, $5, 1, 2, 1 # encoding: [0x41,0x05,0x20,0x32]
23 cftc1 $4, $f9 # CHECK: mftr $4, $9, 1, 3, 0 # encoding: [0x41,0x09,0x20,0x23]
24
25 mttc0 $4, $5 # CHECK: mttr $4, $5, 0, 0, 0 # encoding: [0x41,0x84,0x28,0x00]
26 mttc0 $6, $7, 1 # CHECK: mttr $6, $7, 0, 1, 0 # encoding: [0x41,0x86,0x38,0x01]
27 mttgpr $5, $9 # CHECK: mttr $5, $9, 1, 0, 0 # encoding: [0x41,0x85,0x48,0x20]
28 mttlo $3 # CHECK: mttr $3, $zero, 1, 1, 0 # encoding: [0x41,0x83,0x00,0x21]
29 mttlo $3, $ac0 # CHECK: mttr $3, $zero, 1, 1, 0 # encoding: [0x41,0x83,0x00,0x21]
30 mttlo $3, $ac1 # CHECK: mttr $3, $4, 1, 1, 0 # encoding: [0x41,0x83,0x20,0x21]
31 mttlo $3, $ac2 # CHECK: mttr $3, $8, 1, 1, 0 # encoding: [0x41,0x83,0x40,0x21]
32 mttlo $3, $ac3 # CHECK: mttr $3, $12, 1, 1, 0 # encoding: [0x41,0x83,0x60,0x21]
33 mtthi $3 # CHECK: mttr $3, $1, 1, 1, 0 # encoding: [0x41,0x83,0x08,0x21]
34 mtthi $3, $ac0 # CHECK: mttr $3, $1, 1, 1, 0 # encoding: [0x41,0x83,0x08,0x21]
35 mtthi $3, $ac1 # CHECK: mttr $3, $5, 1, 1, 0 # encoding: [0x41,0x83,0x28,0x21]
36 mtthi $3, $ac2 # CHECK: mttr $3, $9, 1, 1, 0 # encoding: [0x41,0x83,0x48,0x21]
37 mtthi $3, $ac3 # CHECK: mttr $3, $13, 1, 1, 0 # encoding: [0x41,0x83,0x68,0x21]
38 mttacx $3 # CHECK: mttr $3, $2, 1, 1, 0 # encoding: [0x41,0x83,0x10,0x21]
39 mttacx $3, $ac0 # CHECK: mttr $3, $2, 1, 1, 0 # encoding: [0x41,0x83,0x10,0x21]
40 mttacx $3, $ac1 # CHECK: mttr $3, $6, 1, 1, 0 # encoding: [0x41,0x83,0x30,0x21]
41 mttacx $3, $ac2 # CHECK: mttr $3, $10, 1, 1, 0 # encoding: [0x41,0x83,0x50,0x21]
42 mttacx $3, $ac3 # CHECK: mttr $3, $14, 1, 1, 0 # encoding: [0x41,0x83,0x70,0x21]
43 mttdsp $4 # CHECK: mttr $4, $16, 1, 1, 0 # encoding: [0x41,0x84,0x80,0x21]
44 mttc1 $4, $f5 # CHECK: mttr $4, $5, 1, 2, 0 # encoding: [0x41,0x84,0x28,0x22]
45 mtthc1 $4, $f5 # CHECK: mttr $4, $5, 1, 2, 1 # encoding: [0x41,0x84,0x28,0x32]
46 cttc1 $4, $f9 # CHECK: mttr $4, $9, 1, 3, 0 # encoding: [0x41,0x84,0x48,0x23]
0 # RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s | FileCheck %s
1
2 # The selector value and register values here are marked as reserved in the
3 # documentation, but GAS accepts them without warning.
4 mftr $31, $31, 1, 1, 0 # CHECK: mftr $ra, $ra, 1, 1, 0 # encoding: [0x41,0x1f,0xf8,0x21]
5 mttr $31, $31, 1, 1, 0 # CHECK: mttr $ra, $ra, 1, 1, 0 # encoding: [0x41,0x9f,0xf8,0x21]
6 mftr $31, $13, 1, 6, 0 # CHECK: mftr $ra, $13, 1, 6, 0 # encoding: [0x41,0x0d,0xf8,0x26]
7 mttr $31, $13, 1, 6, 0 # CHECK: mttr $ra, $13, 1, 6, 0 # encoding: [0x41,0x9f,0x68,0x26]
0 # RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s \
11 # RUN: | FileCheck %s
2 dmt # CHECK: dmt # encoding: [0x41,0x60,0x0b,0xc1]
3 dmt $5 # CHECK: dmt $5 # encoding: [0x41,0x65,0x0b,0xc1]
4 emt # CHECK: emt # encoding: [0x41,0x60,0x0b,0xe1]
5 emt $4 # CHECK: emt $4 # encoding: [0x41,0x64,0x0b,0xe1]
6 dvpe # CHECK: dvpe # encoding: [0x41,0x60,0x00,0x01]
7 dvpe $6 # CHECK: dvpe $6 # encoding: [0x41,0x66,0x00,0x01]
8 evpe # CHECK: evpe # encoding: [0x41,0x60,0x00,0x21]
9 evpe $4 # CHECK: evpe $4 # encoding: [0x41,0x64,0x00,0x21]
10 fork $2, $3, $5 # CHECK: fork $2, $3, $5 # encoding: [0x7c,0x65,0x10,0x08]
11 yield $4 # CHECK: yield $4 # encoding: [0x7c,0x80,0x00,0x09]
12 yield $4, $5 # CHECK: yield $4, $5 # encoding: [0x7c,0xa0,0x20,0x09]
2 dmt # CHECK: dmt # encoding: [0x41,0x60,0x0b,0xc1]
3 dmt $5 # CHECK: dmt $5 # encoding: [0x41,0x65,0x0b,0xc1]
4 emt # CHECK: emt # encoding: [0x41,0x60,0x0b,0xe1]
5 emt $4 # CHECK: emt $4 # encoding: [0x41,0x64,0x0b,0xe1]
6 dvpe # CHECK: dvpe # encoding: [0x41,0x60,0x00,0x01]
7 dvpe $6 # CHECK: dvpe $6 # encoding: [0x41,0x66,0x00,0x01]
8 evpe # CHECK: evpe # encoding: [0x41,0x60,0x00,0x21]
9 evpe $4 # CHECK: evpe $4 # encoding: [0x41,0x64,0x00,0x21]
10 fork $2, $3, $5 # CHECK: fork $2, $3, $5 # encoding: [0x7c,0x65,0x10,0x08]
11 yield $4 # CHECK: yield $4 # encoding: [0x7c,0x80,0x00,0x09]
12 yield $4, $5 # CHECK: yield $4, $5 # encoding: [0x7c,0xa0,0x20,0x09]
13 mftr $4, $5, 0, 2, 0 # CHECK: mftr $4, $5, 0, 2, 0 # encoding: [0x41,0x05,0x20,0x02]
14 mftr $4, $5, 1, 0, 0 # CHECK: mftr $4, $5, 1, 0, 0 # encoding: [0x41,0x05,0x20,0x20]
15 mftr $4, $0, 1, 1, 0 # CHECK: mftr $4, $zero, 1, 1, 0 # encoding: [0x41,0x00,0x20,0x21]
16 mftr $4, $10, 1, 1, 0 # CHECK: mftr $4, $10, 1, 1, 0 # encoding: [0x41,0x0a,0x20,0x21]
17 mftr $4, $10, 1, 2, 0 # CHECK: mftr $4, $10, 1, 2, 0 # encoding: [0x41,0x0a,0x20,0x22]
18 mftr $4, $10, 1, 2, 1 # CHECK: mftr $4, $10, 1, 2, 1 # encoding: [0x41,0x0a,0x20,0x32]
19 mftr $4, $26, 1, 3, 0 # CHECK: mftr $4, $26, 1, 3, 0 # encoding: [0x41,0x1a,0x20,0x23]
20 mftr $4, $31, 1, 3, 0 # CHECK: mftr $4, $ra, 1, 3, 0 # encoding: [0x41,0x1f,0x20,0x23]
21 mftr $4, $14, 1, 4, 0 # CHECK: mftr $4, $14, 1, 4, 0 # encoding: [0x41,0x0e,0x20,0x24]
22 mftr $4, $15, 1, 5, 0 # CHECK: mftr $4, $15, 1, 5, 0 # encoding: [0x41,0x0f,0x20,0x25]
23 mttr $4, $5, 0, 2, 0 # CHECK: mttr $4, $5, 0, 2, 0 # encoding: [0x41,0x84,0x28,0x02]
24 mttr $4, $5, 1, 0, 0 # CHECK: mttr $4, $5, 1, 0, 0 # encoding: [0x41,0x84,0x28,0x20]
25 mttr $4, $0, 1, 1, 0 # CHECK: mttr $4, $zero, 1, 1, 0 # encoding: [0x41,0x84,0x00,0x21]
26 mttr $4, $10, 1, 1, 0 # CHECK: mttr $4, $10, 1, 1, 0 # encoding: [0x41,0x84,0x50,0x21]
27 mttr $4, $10, 1, 2, 0 # CHECK: mttr $4, $10, 1, 2, 0 # encoding: [0x41,0x84,0x50,0x22]
28 mttr $4, $10, 1, 2, 1 # CHECK: mttr $4, $10, 1, 2, 1 # encoding: [0x41,0x84,0x50,0x32]
29 mttr $4, $26, 1, 3, 0 # CHECK: mttr $4, $26, 1, 3, 0 # encoding: [0x41,0x84,0xd0,0x23]
30 mttr $4, $31, 1, 3, 0 # CHECK: mttr $4, $ra, 1, 3, 0 # encoding: [0x41,0x84,0xf8,0x23]
31 mttr $4, $14, 1, 4, 0 # CHECK: mttr $4, $14, 1, 4, 0 # encoding: [0x41,0x84,0x70,0x24]
32 mttr $4, $15, 1, 5, 0 # CHECK: mttr $4, $15, 1, 5, 0 # encoding: [0x41,0x84,0x78,0x25]