llvm.org GIT mirror llvm / 52e724a
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8 Nicolas Geoffray 12 years ago
14 changed file(s) with 636 addition(s) and 208 deletion(s). Raw diff Collapse all Expand all
387387 abort();
388388 return 0; // Must return a value in order to compile with VS 2005
389389 }
390
391 /// GetInstSize - Returns the size of the specified Instruction.
392 ///
393 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
394 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
395 return 0;
396 }
397
398 /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction.
399 ///
400 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
401
390402 };
391403
392404 /// TargetInstrInfoImpl - This is the default implementation of
407419 MachineBasicBlock::iterator MI,
408420 unsigned DestReg,
409421 const MachineInstr *Orig) const;
422 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
410423 };
411424
412425 } // End llvm namespace
9393 MBB.insert(I, MI);
9494 }
9595
96 unsigned
97 TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
98 unsigned FnSize = 0;
99 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
100 MBBI != E; ++MBBI) {
101 const MachineBasicBlock &MBB = *MBBI;
102 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); I != E; ++I)
103 FnSize += GetInstSizeInBytes(I);
104 }
105 return FnSize;
106 }
367367 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
368368 I != E; ++I) {
369369 // Add instruction size to MBBSize.
370 MBBSize += ARM::GetInstSize(I);
370 MBBSize += TII->GetInstSizeInBytes(I);
371371
372372 int Opc = I->getOpcode();
373373 if (I->getDesc().isBranch()) {
518518 for (MachineBasicBlock::iterator I = MBB->begin(); ; ++I) {
519519 assert(I != MBB->end() && "Didn't find MI in its own basic block?");
520520 if (&*I == MI) return Offset;
521 Offset += ARM::GetInstSize(I);
521 Offset += TII->GetInstSizeInBytes(I);
522522 }
523523 }
524524
616616 unsigned NewBBSize = 0;
617617 for (MachineBasicBlock::iterator I = NewBB->begin(), E = NewBB->end();
618618 I != E; ++I)
619 NewBBSize += ARM::GetInstSize(I);
619 NewBBSize += TII->GetInstSizeInBytes(I);
620620
621621 unsigned OrigBBI = OrigBB->getNumber();
622622 unsigned NewBBI = NewBB->getNumber();
967967 MachineBasicBlock::iterator MI = UserMI;
968968 ++MI;
969969 unsigned CPUIndex = CPUserIndex+1;
970 for (unsigned Offset = UserOffset+ARM::GetInstSize(UserMI);
970 for (unsigned Offset = UserOffset+TII->GetInstSizeInBytes(UserMI);
971971 Offset < BaseInsertOffset;
972 Offset += ARM::GetInstSize(MI),
972 Offset += TII->GetInstSizeInBytes(MI),
973973 MI = next(MI)) {
974974 if (CPUIndex < CPUsers.size() && CPUsers[CPUIndex].MI == MI) {
975975 if (!OffsetIsInRange(Offset, EndInsertOffset,
12241224 SplitBlockBeforeInstr(MI);
12251225 // No need for the branch to the next block. We're adding a unconditional
12261226 // branch to the destination.
1227 int delta = ARM::GetInstSize(&MBB->back());
1227 int delta = TII->GetInstSizeInBytes(&MBB->back());
12281228 BBSizes[MBB->getNumber()] -= delta;
12291229 MachineBasicBlock* SplitBB = next(MachineFunction::iterator(MBB));
12301230 AdjustBBOffsetsAfter(SplitBB, -delta);
12421242 BuildMI(MBB, TII->get(MI->getOpcode())).addMBB(NextBB)
12431243 .addImm(CC).addReg(CCReg);
12441244 Br.MI = &MBB->back();
1245 BBSizes[MBB->getNumber()] += ARM::GetInstSize(&MBB->back());
1245 BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
12461246 BuildMI(MBB, TII->get(Br.UncondBr)).addMBB(DestBB);
1247 BBSizes[MBB->getNumber()] += ARM::GetInstSize(&MBB->back());
1247 BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
12481248 unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
12491249 ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
12501250
12511251 // Remove the old conditional branch. It may or may not still be in MBB.
1252 BBSizes[MI->getParent()->getNumber()] -= ARM::GetInstSize(MI);
1252 BBSizes[MI->getParent()->getNumber()] -= TII->GetInstSizeInBytes(MI);
12531253 MI->eraseFromParent();
12541254
12551255 // The net size change is an addition of one unconditional branch.
1256 int delta = ARM::GetInstSize(&MBB->back());
1256 int delta = TII->GetInstSizeInBytes(&MBB->back());
12571257 AdjustBBOffsetsAfter(MBB, delta);
12581258 return true;
12591259 }
876876
877877 /// GetInstSize - Return the size of the specified MachineInstr.
878878 ///
879 unsigned ARM::GetInstSize(MachineInstr *MI) {
880 MachineBasicBlock &MBB = *MI->getParent();
879 unsigned ARMInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
880 const MachineBasicBlock &MBB = *MI->getParent();
881881 const MachineFunction *MF = MBB.getParent();
882882 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
883883
936936 }
937937 return 0; // Not reached
938938 }
939
940 /// GetFunctionSize - Returns the size of the specified MachineFunction.
941 ///
942 unsigned ARM::GetFunctionSize(MachineFunction &MF) {
943 unsigned FnSize = 0;
944 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
945 MBBI != E; ++MBBI) {
946 MachineBasicBlock &MBB = *MBBI;
947 for (MachineBasicBlock::iterator I = MBB.begin(),E = MBB.end(); I != E; ++I)
948 FnSize += ARM::GetInstSize(I);
949 }
950 return FnSize;
951 }
952
224224
225225 virtual bool DefinesPredicate(MachineInstr *MI,
226226 std::vector &Pred) const;
227
228 /// GetInstSize - Returns the size of the specified MachineInstr.
229 ///
230 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
227231 };
228232
229 // Utility routines
230 namespace ARM {
231 /// GetInstSize - Returns the size of the specified MachineInstr.
232 ///
233 unsigned GetInstSize(MachineInstr *MI);
234
235 /// GetFunctionSize - Returns the size of the specified MachineFunction.
236 ///
237 unsigned GetFunctionSize(MachineFunction &MF);
238 }
239233 }
240234
241235 #endif
947947
948948 bool ForceLRSpill = false;
949949 if (!LRSpilled && AFI->isThumbFunction()) {
950 unsigned FnSize = ARM::GetFunctionSize(MF);
950 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
951951 // Force LR to be spilled if the Thumb function size is > 2048. This enables
952952 // use of BL to implement far jump. If it turns out that it's not needed
953953 // then the branch fix up path will undo it.
2121 #include "PPCPredicates.h"
2222 #include "llvm/CodeGen/MachineFunctionPass.h"
2323 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetAsmInfo.h"
2524 #include "llvm/ADT/Statistic.h"
2625 #include "llvm/Support/Compiler.h"
2726 #include "llvm/Support/MathExtras.h"
5352 return new PPCBSel();
5453 }
5554
56 /// getNumBytesForInstruction - Return the number of bytes of code the specified
57 /// instruction may be. This returns the maximum number of bytes.
58 ///
59 static unsigned getNumBytesForInstruction(MachineInstr *MI) {
60 switch (MI->getOpcode()) {
61 case PPC::INLINEASM: { // Inline Asm: Variable size.
62 MachineFunction *MF = MI->getParent()->getParent();
63 const char *AsmStr = MI->getOperand(0).getSymbolName();
64 return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
65 }
66 case PPC::LABEL: {
67 return 0;
68 }
69 default:
70 return 4; // PowerPC instructions are all 4 bytes
71 }
72 }
73
74
7555 bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
7656 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
7757 // Give the blocks of the function a dense, in-order, numbering.
8767 unsigned BlockSize = 0;
8868 for (MachineBasicBlock::iterator MBBI = MBB->begin(), EE = MBB->end();
8969 MBBI != EE; ++MBBI)
90 BlockSize += getNumBytesForInstruction(MBBI);
70 BlockSize += TII->GetInstSizeInBytes(MBBI);
9171
9272 BlockSizes[MBB->getNumber()] = BlockSize;
9373 FuncSize += BlockSize;
123103 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
124104 I != E; ++I) {
125105 if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImmediate()) {
126 MBBStartOffset += getNumBytesForInstruction(I);
106 MBBStartOffset += TII->GetInstSizeInBytes(I);
127107 continue;
128108 }
129109
1919 #include "llvm/ADT/STLExtras.h"
2020 #include "llvm/CodeGen/MachineInstrBuilder.h"
2121 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Target/TargetAsmInfo.h"
2223 using namespace llvm;
2324
2425 extern cl::opt EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
723724 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
724725 return false;
725726 }
727
728 /// GetInstSize - Return the number of bytes of code the specified
729 /// instruction may be. This returns the maximum number of bytes.
730 ///
731 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
732 switch (MI->getOpcode()) {
733 case PPC::INLINEASM: { // Inline Asm: Variable size.
734 const MachineFunction *MF = MI->getParent()->getParent();
735 const char *AsmStr = MI->getOperand(0).getSymbolName();
736 return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
737 }
738 case PPC::LABEL: {
739 return 0;
740 }
741 default:
742 return 4; // PowerPC instructions are all 4 bytes
743 }
744 }
154154
155155 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
156156 virtual bool ReverseBranchCondition(std::vector &Cond) const;
157
158 /// GetInstSize - Return the number of bytes of code the specified
159 /// instruction may be. This returns the maximum number of bytes.
160 ///
161 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
157162 };
158163
159164 }
9191 intptr_t PCAdj = 0);
9292
9393 unsigned getX86RegNum(unsigned RegNo) const;
94 bool isX86_64ExtendedReg(const MachineOperand &MO);
95 unsigned determineREX(const MachineInstr &MI);
9694
9795 bool gvNeedsLazyPtr(const GlobalValue *GV);
9896 };
404402 }
405403 }
406404
407 static unsigned sizeOfImm(const TargetInstrDesc *Desc) {
408 switch (Desc->TSFlags & X86II::ImmMask) {
409 case X86II::Imm8: return 1;
410 case X86II::Imm16: return 2;
411 case X86II::Imm32: return 4;
412 case X86II::Imm64: return 8;
413 default: assert(0 && "Immediate size not set!");
414 return 0;
415 }
416 }
417
418 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
419 /// e.g. r8, xmm8, etc.
420 bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) {
421 if (!MO.isRegister()) return false;
422 switch (MO.getReg()) {
423 default: break;
424 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
425 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
426 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
427 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
428 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
429 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
430 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
431 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
432 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
433 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
434 return true;
435 }
436 return false;
437 }
438
439 inline static bool isX86_64NonExtLowByteReg(unsigned reg) {
440 return (reg == X86::SPL || reg == X86::BPL ||
441 reg == X86::SIL || reg == X86::DIL);
442 }
443
444 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
445 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
446 /// size, and 3) use of X86-64 extended registers.
447 unsigned Emitter::determineREX(const MachineInstr &MI) {
448 unsigned REX = 0;
449 const TargetInstrDesc &Desc = MI.getDesc();
450
451 // Pseudo instructions do not need REX prefix byte.
452 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
453 return 0;
454 if (Desc.TSFlags & X86II::REX_W)
455 REX |= 1 << 3;
456
457 unsigned NumOps = Desc.getNumOperands();
458 if (NumOps) {
459 bool isTwoAddr = NumOps > 1 &&
460 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
461
462 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
463 unsigned i = isTwoAddr ? 1 : 0;
464 for (unsigned e = NumOps; i != e; ++i) {
465 const MachineOperand& MO = MI.getOperand(i);
466 if (MO.isRegister()) {
467 unsigned Reg = MO.getReg();
468 if (isX86_64NonExtLowByteReg(Reg))
469 REX |= 0x40;
470 }
471 }
472
473 switch (Desc.TSFlags & X86II::FormMask) {
474 case X86II::MRMInitReg:
475 if (isX86_64ExtendedReg(MI.getOperand(0)))
476 REX |= (1 << 0) | (1 << 2);
477 break;
478 case X86II::MRMSrcReg: {
479 if (isX86_64ExtendedReg(MI.getOperand(0)))
480 REX |= 1 << 2;
481 i = isTwoAddr ? 2 : 1;
482 for (unsigned e = NumOps; i != e; ++i) {
483 const MachineOperand& MO = MI.getOperand(i);
484 if (isX86_64ExtendedReg(MO))
485 REX |= 1 << 0;
486 }
487 break;
488 }
489 case X86II::MRMSrcMem: {
490 if (isX86_64ExtendedReg(MI.getOperand(0)))
491 REX |= 1 << 2;
492 unsigned Bit = 0;
493 i = isTwoAddr ? 2 : 1;
494 for (; i != NumOps; ++i) {
495 const MachineOperand& MO = MI.getOperand(i);
496 if (MO.isRegister()) {
497 if (isX86_64ExtendedReg(MO))
498 REX |= 1 << Bit;
499 Bit++;
500 }
501 }
502 break;
503 }
504 case X86II::MRM0m: case X86II::MRM1m:
505 case X86II::MRM2m: case X86II::MRM3m:
506 case X86II::MRM4m: case X86II::MRM5m:
507 case X86II::MRM6m: case X86II::MRM7m:
508 case X86II::MRMDestMem: {
509 unsigned e = isTwoAddr ? 5 : 4;
510 i = isTwoAddr ? 1 : 0;
511 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
512 REX |= 1 << 2;
513 unsigned Bit = 0;
514 for (; i != e; ++i) {
515 const MachineOperand& MO = MI.getOperand(i);
516 if (MO.isRegister()) {
517 if (isX86_64ExtendedReg(MO))
518 REX |= 1 << Bit;
519 Bit++;
520 }
521 }
522 break;
523 }
524 default: {
525 if (isX86_64ExtendedReg(MI.getOperand(0)))
526 REX |= 1 << 0;
527 i = isTwoAddr ? 2 : 1;
528 for (unsigned e = NumOps; i != e; ++i) {
529 const MachineOperand& MO = MI.getOperand(i);
530 if (isX86_64ExtendedReg(MO))
531 REX |= 1 << 2;
532 }
533 break;
534 }
535 }
536 }
537 return REX;
538 }
539
540405 void Emitter::emitInstruction(const MachineInstr &MI,
541406 const TargetInstrDesc *Desc) {
542407 DOUT << MI;
583448
584449 if (Is64BitMode) {
585450 // REX prefix
586 unsigned REX = determineREX(MI);
451 unsigned REX = X86InstrInfo::determineREX(MI);
587452 if (REX)
588453 MCE.emitByte(0x40 | REX);
589454 }
631496 case X86::MOVPC32r: {
632497 // This emits the "call" portion of this pseudo instruction.
633498 MCE.emitByte(BaseOpcode);
634 emitConstant(0, sizeOfImm(Desc));
499 emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
635500 // Remember PIC base.
636501 PICBaseOffset = MCE.getCurrentPCOffset();
637502 X86JITInfo *JTI = dynamic_cast(TM.getJITInfo());
656521 } else if (MO.isExternalSymbol()) {
657522 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
658523 } else if (MO.isImmediate()) {
659 emitConstant(MO.getImm(), sizeOfImm(Desc));
524 emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
660525 } else {
661526 assert(0 && "Unknown RawFrm operand!");
662527 }
668533
669534 if (CurOp != NumOps) {
670535 const MachineOperand &MO1 = MI.getOperand(CurOp++);
671 unsigned Size = sizeOfImm(Desc);
536 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
672537 if (MO1.isImmediate())
673538 emitConstant(MO1.getImm(), Size);
674539 else {
697562 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
698563 CurOp += 2;
699564 if (CurOp != NumOps)
700 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
565 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
701566 break;
702567 }
703568 case X86II::MRMDestMem: {
705570 emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
706571 CurOp += 5;
707572 if (CurOp != NumOps)
708 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
573 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
709574 break;
710575 }
711576
715580 getX86RegNum(MI.getOperand(CurOp).getReg()));
716581 CurOp += 2;
717582 if (CurOp != NumOps)
718 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
583 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
719584 break;
720585
721586 case X86II::MRMSrcMem: {
722 intptr_t PCAdj = (CurOp+5 != NumOps) ? sizeOfImm(Desc) : 0;
587 intptr_t PCAdj = (CurOp+5 != NumOps) ? X86InstrInfo::sizeOfImm(Desc) : 0;
723588
724589 MCE.emitByte(BaseOpcode);
725590 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
726591 PCAdj);
727592 CurOp += 5;
728593 if (CurOp != NumOps)
729 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
594 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
730595 break;
731596 }
732597
740605
741606 if (CurOp != NumOps) {
742607 const MachineOperand &MO1 = MI.getOperand(CurOp++);
743 unsigned Size = sizeOfImm(Desc);
608 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
744609 if (MO1.isImmediate())
745610 emitConstant(MO1.getImm(), Size);
746611 else {
768633 case X86II::MRM4m: case X86II::MRM5m:
769634 case X86II::MRM6m: case X86II::MRM7m: {
770635 intptr_t PCAdj = (CurOp+4 != NumOps) ?
771 (MI.getOperand(CurOp+4).isImmediate() ? sizeOfImm(Desc) : 4) : 0;
636 (MI.getOperand(CurOp+4).isImmediate() ? X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
772637
773638 MCE.emitByte(BaseOpcode);
774639 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
777642
778643 if (CurOp != NumOps) {
779644 const MachineOperand &MO = MI.getOperand(CurOp++);
780 unsigned Size = sizeOfImm(Desc);
645 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
781646 if (MO.isImmediate())
782647 emitConstant(MO.getImm(), Size);
783648 else {
2424 #include "llvm/CodeGen/LiveVariables.h"
2525 #include "llvm/Support/CommandLine.h"
2626 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetAsmInfo.h"
2728
2829 using namespace llvm;
2930
22622263 else
22632264 return &X86::GR32RegClass;
22642265 }
2266
2267 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2268 switch (Desc->TSFlags & X86II::ImmMask) {
2269 case X86II::Imm8: return 1;
2270 case X86II::Imm16: return 2;
2271 case X86II::Imm32: return 4;
2272 case X86II::Imm64: return 8;
2273 default: assert(0 && "Immediate size not set!");
2274 return 0;
2275 }
2276 }
2277
2278 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2279 /// e.g. r8, xmm8, etc.
2280 bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2281 if (!MO.isRegister()) return false;
2282 switch (MO.getReg()) {
2283 default: break;
2284 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
2285 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
2286 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
2287 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
2288 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
2289 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
2290 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
2291 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
2292 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
2293 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2294 return true;
2295 }
2296 return false;
2297 }
2298
2299
2300 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2301 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2302 /// size, and 3) use of X86-64 extended registers.
2303 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2304 unsigned REX = 0;
2305 const TargetInstrDesc &Desc = MI.getDesc();
2306
2307 // Pseudo instructions do not need REX prefix byte.
2308 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2309 return 0;
2310 if (Desc.TSFlags & X86II::REX_W)
2311 REX |= 1 << 3;
2312
2313 unsigned NumOps = Desc.getNumOperands();
2314 if (NumOps) {
2315 bool isTwoAddr = NumOps > 1 &&
2316 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2317
2318 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2319 unsigned i = isTwoAddr ? 1 : 0;
2320 for (unsigned e = NumOps; i != e; ++i) {
2321 const MachineOperand& MO = MI.getOperand(i);
2322 if (MO.isRegister()) {
2323 unsigned Reg = MO.getReg();
2324 if (isX86_64NonExtLowByteReg(Reg))
2325 REX |= 0x40;
2326 }
2327 }
2328
2329 switch (Desc.TSFlags & X86II::FormMask) {
2330 case X86II::MRMInitReg:
2331 if (isX86_64ExtendedReg(MI.getOperand(0)))
2332 REX |= (1 << 0) | (1 << 2);
2333 break;
2334 case X86II::MRMSrcReg: {
2335 if (isX86_64ExtendedReg(MI.getOperand(0)))
2336 REX |= 1 << 2;
2337 i = isTwoAddr ? 2 : 1;
2338 for (unsigned e = NumOps; i != e; ++i) {
2339 const MachineOperand& MO = MI.getOperand(i);
2340 if (isX86_64ExtendedReg(MO))
2341 REX |= 1 << 0;
2342 }
2343 break;
2344 }
2345 case X86II::MRMSrcMem: {
2346 if (isX86_64ExtendedReg(MI.getOperand(0)))
2347 REX |= 1 << 2;
2348 unsigned Bit = 0;
2349 i = isTwoAddr ? 2 : 1;
2350 for (; i != NumOps; ++i) {
2351 const MachineOperand& MO = MI.getOperand(i);
2352 if (MO.isRegister()) {
2353 if (isX86_64ExtendedReg(MO))
2354 REX |= 1 << Bit;
2355 Bit++;
2356 }
2357 }
2358 break;
2359 }
2360 case X86II::MRM0m: case X86II::MRM1m:
2361 case X86II::MRM2m: case X86II::MRM3m:
2362 case X86II::MRM4m: case X86II::MRM5m:
2363 case X86II::MRM6m: case X86II::MRM7m:
2364 case X86II::MRMDestMem: {
2365 unsigned e = isTwoAddr ? 5 : 4;
2366 i = isTwoAddr ? 1 : 0;
2367 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2368 REX |= 1 << 2;
2369 unsigned Bit = 0;
2370 for (; i != e; ++i) {
2371 const MachineOperand& MO = MI.getOperand(i);
2372 if (MO.isRegister()) {
2373 if (isX86_64ExtendedReg(MO))
2374 REX |= 1 << Bit;
2375 Bit++;
2376 }
2377 }
2378 break;
2379 }
2380 default: {
2381 if (isX86_64ExtendedReg(MI.getOperand(0)))
2382 REX |= 1 << 0;
2383 i = isTwoAddr ? 2 : 1;
2384 for (unsigned e = NumOps; i != e; ++i) {
2385 const MachineOperand& MO = MI.getOperand(i);
2386 if (isX86_64ExtendedReg(MO))
2387 REX |= 1 << 2;
2388 }
2389 break;
2390 }
2391 }
2392 }
2393 return REX;
2394 }
2395
2396 /// sizePCRelativeBlockAddress - This method returns the size of a PC
2397 /// relative block address instruction
2398 ///
2399 static unsigned sizePCRelativeBlockAddress() {
2400 return 4;
2401 }
2402
2403 /// sizeGlobalAddress - Give the size of the emission of this global address
2404 ///
2405 static unsigned sizeGlobalAddress(bool dword) {
2406 return dword ? 8 : 4;
2407 }
2408
2409 /// sizeConstPoolAddress - Give the size of the emission of this constant
2410 /// pool address
2411 ///
2412 static unsigned sizeConstPoolAddress(bool dword) {
2413 return dword ? 8 : 4;
2414 }
2415
2416 /// sizeExternalSymbolAddress - Give the size of the emission of this external
2417 /// symbol
2418 ///
2419 static unsigned sizeExternalSymbolAddress(bool dword) {
2420 return dword ? 8 : 4;
2421 }
2422
2423 /// sizeJumpTableAddress - Give the size of the emission of this jump
2424 /// table address
2425 ///
2426 static unsigned sizeJumpTableAddress(bool dword) {
2427 return dword ? 8 : 4;
2428 }
2429
2430 static unsigned sizeConstant(unsigned Size) {
2431 return Size;
2432 }
2433
2434 static unsigned sizeRegModRMByte(){
2435 return 1;
2436 }
2437
2438 static unsigned sizeSIBByte(){
2439 return 1;
2440 }
2441
2442 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
2443 unsigned FinalSize = 0;
2444 // If this is a simple integer displacement that doesn't require a relocation.
2445 if (!RelocOp) {
2446 FinalSize += sizeConstant(4);
2447 return FinalSize;
2448 }
2449
2450 // Otherwise, this is something that requires a relocation.
2451 if (RelocOp->isGlobalAddress()) {
2452 FinalSize += sizeGlobalAddress(false);
2453 } else if (RelocOp->isConstantPoolIndex()) {
2454 FinalSize += sizeConstPoolAddress(false);
2455 } else if (RelocOp->isJumpTableIndex()) {
2456 FinalSize += sizeJumpTableAddress(false);
2457 } else {
2458 assert(0 && "Unknown value to relocate!");
2459 }
2460 return FinalSize;
2461 }
2462
2463 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
2464 bool IsPIC, bool Is64BitMode) {
2465 const MachineOperand &Op3 = MI.getOperand(Op+3);
2466 int DispVal = 0;
2467 const MachineOperand *DispForReloc = 0;
2468 unsigned FinalSize = 0;
2469
2470 // Figure out what sort of displacement we have to handle here.
2471 if (Op3.isGlobalAddress()) {
2472 DispForReloc = &Op3;
2473 } else if (Op3.isConstantPoolIndex()) {
2474 if (Is64BitMode || IsPIC) {
2475 DispForReloc = &Op3;
2476 } else {
2477 DispVal = 1;
2478 }
2479 } else if (Op3.isJumpTableIndex()) {
2480 if (Is64BitMode || IsPIC) {
2481 DispForReloc = &Op3;
2482 } else {
2483 DispVal = 1;
2484 }
2485 } else {
2486 DispVal = 1;
2487 }
2488
2489 const MachineOperand &Base = MI.getOperand(Op);
2490 const MachineOperand &IndexReg = MI.getOperand(Op+2);
2491
2492 unsigned BaseReg = Base.getReg();
2493
2494 // Is a SIB byte needed?
2495 if (IndexReg.getReg() == 0 &&
2496 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
2497 if (BaseReg == 0) { // Just a displacement?
2498 // Emit special case [disp32] encoding
2499 ++FinalSize;
2500 FinalSize += getDisplacementFieldSize(DispForReloc);
2501 } else {
2502 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
2503 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
2504 // Emit simple indirect register encoding... [EAX] f.e.
2505 ++FinalSize;
2506 // Be pessimistic and assume it's a disp32, not a disp8
2507 } else {
2508 // Emit the most general non-SIB encoding: [REG+disp32]
2509 ++FinalSize;
2510 FinalSize += getDisplacementFieldSize(DispForReloc);
2511 }
2512 }
2513
2514 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
2515 assert(IndexReg.getReg() != X86::ESP &&
2516 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
2517
2518 bool ForceDisp32 = false;
2519 if (BaseReg == 0 || DispForReloc) {
2520 // Emit the normal disp32 encoding.
2521 ++FinalSize;
2522 ForceDisp32 = true;
2523 } else {
2524 ++FinalSize;
2525 }
2526
2527 FinalSize += sizeSIBByte();
2528
2529 // Do we need to output a displacement?
2530 if (DispVal != 0 || ForceDisp32) {
2531 FinalSize += getDisplacementFieldSize(DispForReloc);
2532 }
2533 }
2534 return FinalSize;
2535 }
2536
2537
2538 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
2539 const TargetInstrDesc *Desc,
2540 bool IsPIC, bool Is64BitMode) {
2541
2542 unsigned Opcode = Desc->Opcode;
2543 unsigned FinalSize = 0;
2544
2545 // Emit the lock opcode prefix as needed.
2546 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
2547
2548 // Emit the repeat opcode prefix as needed.
2549 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
2550
2551 // Emit the operand size opcode prefix as needed.
2552 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
2553
2554 // Emit the address size opcode prefix as needed.
2555 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
2556
2557 bool Need0FPrefix = false;
2558 switch (Desc->TSFlags & X86II::Op0Mask) {
2559 case X86II::TB: // Two-byte opcode prefix
2560 case X86II::T8: // 0F 38
2561 case X86II::TA: // 0F 3A
2562 Need0FPrefix = true;
2563 break;
2564 case X86II::REP: break; // already handled.
2565 case X86II::XS: // F3 0F
2566 ++FinalSize;
2567 Need0FPrefix = true;
2568 break;
2569 case X86II::XD: // F2 0F
2570 ++FinalSize;
2571 Need0FPrefix = true;
2572 break;
2573 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
2574 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
2575 ++FinalSize;
2576 break; // Two-byte opcode prefix
2577 default: assert(0 && "Invalid prefix!");
2578 case 0: break; // No prefix!
2579 }
2580
2581 if (Is64BitMode) {
2582 // REX prefix
2583 unsigned REX = X86InstrInfo::determineREX(MI);
2584 if (REX)
2585 ++FinalSize;
2586 }
2587
2588 // 0x0F escape code must be emitted just before the opcode.
2589 if (Need0FPrefix)
2590 ++FinalSize;
2591
2592 switch (Desc->TSFlags & X86II::Op0Mask) {
2593 case X86II::T8: // 0F 38
2594 ++FinalSize;
2595 break;
2596 case X86II::TA: // 0F 3A
2597 ++FinalSize;
2598 break;
2599 }
2600
2601 // If this is a two-address instruction, skip one of the register operands.
2602 unsigned NumOps = Desc->getNumOperands();
2603 unsigned CurOp = 0;
2604 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
2605 CurOp++;
2606
2607 switch (Desc->TSFlags & X86II::FormMask) {
2608 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
2609 case X86II::Pseudo:
2610 // Remember the current PC offset, this is the PIC relocation
2611 // base address.
2612 switch (Opcode) {
2613 default:
2614 break;
2615 case TargetInstrInfo::INLINEASM: {
2616 const MachineFunction *MF = MI.getParent()->getParent();
2617 const char *AsmStr = MI.getOperand(0).getSymbolName();
2618 const TargetAsmInfo* AI = MF->getTarget().getTargetAsmInfo();
2619 FinalSize += AI->getInlineAsmLength(AsmStr);
2620 break;
2621 }
2622 case TargetInstrInfo::LABEL:
2623 break;
2624 case TargetInstrInfo::IMPLICIT_DEF:
2625 case TargetInstrInfo::DECLARE:
2626 case X86::DWARF_LOC:
2627 case X86::FP_REG_KILL:
2628 break;
2629 case X86::MOVPC32r: {
2630 // This emits the "call" portion of this pseudo instruction.
2631 ++FinalSize;
2632 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2633 break;
2634 }
2635 }
2636 CurOp = NumOps;
2637 break;
2638 case X86II::RawFrm:
2639 ++FinalSize;
2640
2641 if (CurOp != NumOps) {
2642 const MachineOperand &MO = MI.getOperand(CurOp++);
2643 if (MO.isMachineBasicBlock()) {
2644 FinalSize += sizePCRelativeBlockAddress();
2645 } else if (MO.isGlobalAddress()) {
2646 FinalSize += sizeGlobalAddress(false);
2647 } else if (MO.isExternalSymbol()) {
2648 FinalSize += sizeExternalSymbolAddress(false);
2649 } else if (MO.isImmediate()) {
2650 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2651 } else {
2652 assert(0 && "Unknown RawFrm operand!");
2653 }
2654 }
2655 break;
2656
2657 case X86II::AddRegFrm:
2658 ++FinalSize;
2659
2660 if (CurOp != NumOps) {
2661 const MachineOperand &MO1 = MI.getOperand(CurOp++);
2662 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2663 if (MO1.isImmediate())
2664 FinalSize += sizeConstant(Size);
2665 else {
2666 bool dword = false;
2667 if (Opcode == X86::MOV64ri)
2668 dword = true;
2669 if (MO1.isGlobalAddress()) {
2670 FinalSize += sizeGlobalAddress(dword);
2671 } else if (MO1.isExternalSymbol())
2672 FinalSize += sizeExternalSymbolAddress(dword);
2673 else if (MO1.isConstantPoolIndex())
2674 FinalSize += sizeConstPoolAddress(dword);
2675 else if (MO1.isJumpTableIndex())
2676 FinalSize += sizeJumpTableAddress(dword);
2677 }
2678 }
2679 break;
2680
2681 case X86II::MRMDestReg: {
2682 ++FinalSize;
2683 FinalSize += sizeRegModRMByte();
2684 CurOp += 2;
2685 if (CurOp != NumOps)
2686 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2687 break;
2688 }
2689 case X86II::MRMDestMem: {
2690 ++FinalSize;
2691 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
2692 CurOp += 5;
2693 if (CurOp != NumOps)
2694 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2695 break;
2696 }
2697
2698 case X86II::MRMSrcReg:
2699 ++FinalSize;
2700 FinalSize += sizeRegModRMByte();
2701 CurOp += 2;
2702 if (CurOp != NumOps)
2703 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2704 break;
2705
2706 case X86II::MRMSrcMem: {
2707
2708 ++FinalSize;
2709 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
2710 CurOp += 5;
2711 if (CurOp != NumOps)
2712 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2713 break;
2714 }
2715
2716 case X86II::MRM0r: case X86II::MRM1r:
2717 case X86II::MRM2r: case X86II::MRM3r:
2718 case X86II::MRM4r: case X86II::MRM5r:
2719 case X86II::MRM6r: case X86II::MRM7r:
2720 ++FinalSize;
2721 FinalSize += sizeRegModRMByte();
2722
2723 if (CurOp != NumOps) {
2724 const MachineOperand &MO1 = MI.getOperand(CurOp++);
2725 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2726 if (MO1.isImmediate())
2727 FinalSize += sizeConstant(Size);
2728 else {
2729 bool dword = false;
2730 if (Opcode == X86::MOV64ri32)
2731 dword = true;
2732 if (MO1.isGlobalAddress()) {
2733 FinalSize += sizeGlobalAddress(dword);
2734 } else if (MO1.isExternalSymbol())
2735 FinalSize += sizeExternalSymbolAddress(dword);
2736 else if (MO1.isConstantPoolIndex())
2737 FinalSize += sizeConstPoolAddress(dword);
2738 else if (MO1.isJumpTableIndex())
2739 FinalSize += sizeJumpTableAddress(dword);
2740 }
2741 }
2742 break;
2743
2744 case X86II::MRM0m: case X86II::MRM1m:
2745 case X86II::MRM2m: case X86II::MRM3m:
2746 case X86II::MRM4m: case X86II::MRM5m:
2747 case X86II::MRM6m: case X86II::MRM7m: {
2748
2749 ++FinalSize;
2750 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
2751 CurOp += 4;
2752
2753 if (CurOp != NumOps) {
2754 const MachineOperand &MO = MI.getOperand(CurOp++);
2755 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2756 if (MO.isImmediate())
2757 FinalSize += sizeConstant(Size);
2758 else {
2759 bool dword = false;
2760 if (Opcode == X86::MOV64mi32)
2761 dword = true;
2762 if (MO.isGlobalAddress()) {
2763 FinalSize += sizeGlobalAddress(dword);
2764 } else if (MO.isExternalSymbol())
2765 FinalSize += sizeExternalSymbolAddress(dword);
2766 else if (MO.isConstantPoolIndex())
2767 FinalSize += sizeConstPoolAddress(dword);
2768 else if (MO.isJumpTableIndex())
2769 FinalSize += sizeJumpTableAddress(dword);
2770 }
2771 }
2772 break;
2773 }
2774
2775 case X86II::MRMInitReg:
2776 ++FinalSize;
2777 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
2778 FinalSize += sizeRegModRMByte();
2779 ++CurOp;
2780 break;
2781 }
2782
2783 if (!Desc->isVariadic() && CurOp != NumOps) {
2784 cerr << "Cannot determine size: ";
2785 MI.dump();
2786 cerr << '\n';
2787 abort();
2788 }
2789
2790
2791 return FinalSize;
2792 }
2793
2794
2795 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
2796 const TargetInstrDesc &Desc = MI->getDesc();
2797 bool IsPIC = (TM.getRelocationModel() == Reloc::PIC_);
2798 bool Is64BitMode = ((X86Subtarget*)TM.getSubtargetImpl())->is64Bit();
2799 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
2800 if (Desc.getOpcode() == X86::MOVPC32r) {
2801 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
2802 }
2803 return Size;
2804 }
1414 #define X86INSTRUCTIONINFO_H
1515
1616 #include "llvm/Target/TargetInstrInfo.h"
17 #include "X86.h"
1718 #include "X86RegisterInfo.h"
1819 #include "llvm/ADT/IndexedMap.h"
1920 #include "llvm/Target/TargetRegisterInfo.h"
379380 unsigned char getBaseOpcodeFor(unsigned Opcode) const {
380381 return getBaseOpcodeFor(&get(Opcode));
381382 }
383
384 static bool isX86_64NonExtLowByteReg(unsigned reg) {
385 return (reg == X86::SPL || reg == X86::BPL ||
386 reg == X86::SIL || reg == X86::DIL);
387 }
388
389 static unsigned sizeOfImm(const TargetInstrDesc *Desc);
390 static unsigned getX86RegNum(unsigned RegNo);
391 static bool isX86_64ExtendedReg(const MachineOperand &MO);
392 static unsigned determineREX(const MachineInstr &MI);
393
394 /// GetInstSize - Returns the size of the specified MachineInstr.
395 ///
396 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
382397
383398 private:
384399 MachineInstr* foldMemoryOperand(MachineInstr* MI,
8383 // getX86RegNum - This function maps LLVM register identifiers to their X86
8484 // specific numbering, which is used in various places encoding instructions.
8585 //
86 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) const {
86 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
8787 switch(RegNo) {
8888 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
8989 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
8383
8484 /// getX86RegNum - Returns the native X86 register number for the given LLVM
8585 /// register identifier.
86 unsigned getX86RegNum(unsigned RegNo) const;
86 static unsigned getX86RegNum(unsigned RegNo);
8787
8888 unsigned getStackAlignment() const { return StackAlign; }
8989