llvm.org GIT mirror llvm / 52cd70f
Merging r291909: ------------------------------------------------------------------------ r291909 | compnerd | 2017-01-13 08:25:33 -0800 (Fri, 13 Jan 2017) | 9 lines ARM: match GCC's behaviour for builtins GCC changes the CC between the user-code and the builtins based on the value of `-target` rather than `-mfloat-abi`. When a HF target is used, the VFP variant of the AAPCS CC is used. Otherwise, the AAPCS variant is used. In all cases, the AEABI functions use the AAPCS CC. Adjust the calling convention based on the target. Resolves PR30543! ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_40@292951 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 3 years ago
5 changed file(s) with 59 addition(s) and 170 deletion(s). Raw diff Collapse all Expand all
9696 };
9797 }
9898
99 void ARMTargetLowering::InitLibcallCallingConvs() {
100 // The builtins on ARM always use AAPCS, irrespective of wheter C is AAPCS or
101 // AAPCS_VFP.
102 for (const auto LC : {
103 RTLIB::SHL_I16,
104 RTLIB::SHL_I32,
105 RTLIB::SHL_I64,
106 RTLIB::SHL_I128,
107 RTLIB::SRL_I16,
108 RTLIB::SRL_I32,
109 RTLIB::SRL_I64,
110 RTLIB::SRL_I128,
111 RTLIB::SRA_I16,
112 RTLIB::SRA_I32,
113 RTLIB::SRA_I64,
114 RTLIB::SRA_I128,
115 RTLIB::MUL_I8,
116 RTLIB::MUL_I16,
117 RTLIB::MUL_I32,
118 RTLIB::MUL_I64,
119 RTLIB::MUL_I128,
120 RTLIB::MULO_I32,
121 RTLIB::MULO_I64,
122 RTLIB::MULO_I128,
123 RTLIB::SDIV_I8,
124 RTLIB::SDIV_I16,
125 RTLIB::SDIV_I32,
126 RTLIB::SDIV_I64,
127 RTLIB::SDIV_I128,
128 RTLIB::UDIV_I8,
129 RTLIB::UDIV_I16,
130 RTLIB::UDIV_I32,
131 RTLIB::UDIV_I64,
132 RTLIB::UDIV_I128,
133 RTLIB::SREM_I8,
134 RTLIB::SREM_I16,
135 RTLIB::SREM_I32,
136 RTLIB::SREM_I64,
137 RTLIB::SREM_I128,
138 RTLIB::UREM_I8,
139 RTLIB::UREM_I16,
140 RTLIB::UREM_I32,
141 RTLIB::UREM_I64,
142 RTLIB::UREM_I128,
143 RTLIB::SDIVREM_I8,
144 RTLIB::SDIVREM_I16,
145 RTLIB::SDIVREM_I32,
146 RTLIB::SDIVREM_I64,
147 RTLIB::SDIVREM_I128,
148 RTLIB::UDIVREM_I8,
149 RTLIB::UDIVREM_I16,
150 RTLIB::UDIVREM_I32,
151 RTLIB::UDIVREM_I64,
152 RTLIB::UDIVREM_I128,
153 RTLIB::NEG_I32,
154 RTLIB::NEG_I64,
155 RTLIB::ADD_F32,
156 RTLIB::ADD_F64,
157 RTLIB::ADD_F80,
158 RTLIB::ADD_F128,
159 RTLIB::SUB_F32,
160 RTLIB::SUB_F64,
161 RTLIB::SUB_F80,
162 RTLIB::SUB_F128,
163 RTLIB::MUL_F32,
164 RTLIB::MUL_F64,
165 RTLIB::MUL_F80,
166 RTLIB::MUL_F128,
167 RTLIB::DIV_F32,
168 RTLIB::DIV_F64,
169 RTLIB::DIV_F80,
170 RTLIB::DIV_F128,
171 RTLIB::POWI_F32,
172 RTLIB::POWI_F64,
173 RTLIB::POWI_F80,
174 RTLIB::POWI_F128,
175 RTLIB::FPEXT_F64_F128,
176 RTLIB::FPEXT_F32_F128,
177 RTLIB::FPEXT_F32_F64,
178 RTLIB::FPEXT_F16_F32,
179 RTLIB::FPROUND_F32_F16,
180 RTLIB::FPROUND_F64_F16,
181 RTLIB::FPROUND_F80_F16,
182 RTLIB::FPROUND_F128_F16,
183 RTLIB::FPROUND_F64_F32,
184 RTLIB::FPROUND_F80_F32,
185 RTLIB::FPROUND_F128_F32,
186 RTLIB::FPROUND_F80_F64,
187 RTLIB::FPROUND_F128_F64,
188 RTLIB::FPTOSINT_F32_I32,
189 RTLIB::FPTOSINT_F32_I64,
190 RTLIB::FPTOSINT_F32_I128,
191 RTLIB::FPTOSINT_F64_I32,
192 RTLIB::FPTOSINT_F64_I64,
193 RTLIB::FPTOSINT_F64_I128,
194 RTLIB::FPTOSINT_F80_I32,
195 RTLIB::FPTOSINT_F80_I64,
196 RTLIB::FPTOSINT_F80_I128,
197 RTLIB::FPTOSINT_F128_I32,
198 RTLIB::FPTOSINT_F128_I64,
199 RTLIB::FPTOSINT_F128_I128,
200 RTLIB::FPTOUINT_F32_I32,
201 RTLIB::FPTOUINT_F32_I64,
202 RTLIB::FPTOUINT_F32_I128,
203 RTLIB::FPTOUINT_F64_I32,
204 RTLIB::FPTOUINT_F64_I64,
205 RTLIB::FPTOUINT_F64_I128,
206 RTLIB::FPTOUINT_F80_I32,
207 RTLIB::FPTOUINT_F80_I64,
208 RTLIB::FPTOUINT_F80_I128,
209 RTLIB::FPTOUINT_F128_I32,
210 RTLIB::FPTOUINT_F128_I64,
211 RTLIB::FPTOUINT_F128_I128,
212 RTLIB::SINTTOFP_I32_F32,
213 RTLIB::SINTTOFP_I32_F64,
214 RTLIB::SINTTOFP_I32_F80,
215 RTLIB::SINTTOFP_I32_F128,
216 RTLIB::SINTTOFP_I64_F32,
217 RTLIB::SINTTOFP_I64_F64,
218 RTLIB::SINTTOFP_I64_F80,
219 RTLIB::SINTTOFP_I64_F128,
220 RTLIB::SINTTOFP_I128_F32,
221 RTLIB::SINTTOFP_I128_F64,
222 RTLIB::SINTTOFP_I128_F80,
223 RTLIB::SINTTOFP_I128_F128,
224 RTLIB::UINTTOFP_I32_F32,
225 RTLIB::UINTTOFP_I32_F64,
226 RTLIB::UINTTOFP_I32_F80,
227 RTLIB::UINTTOFP_I32_F128,
228 RTLIB::UINTTOFP_I64_F32,
229 RTLIB::UINTTOFP_I64_F64,
230 RTLIB::UINTTOFP_I64_F80,
231 RTLIB::UINTTOFP_I64_F128,
232 RTLIB::UINTTOFP_I128_F32,
233 RTLIB::UINTTOFP_I128_F64,
234 RTLIB::UINTTOFP_I128_F80,
235 RTLIB::UINTTOFP_I128_F128,
236 RTLIB::OEQ_F32,
237 RTLIB::OEQ_F64,
238 RTLIB::OEQ_F128,
239 RTLIB::UNE_F32,
240 RTLIB::UNE_F64,
241 RTLIB::UNE_F128,
242 RTLIB::OGE_F32,
243 RTLIB::OGE_F64,
244 RTLIB::OGE_F128,
245 RTLIB::OLT_F32,
246 RTLIB::OLT_F64,
247 RTLIB::OLT_F128,
248 RTLIB::OLE_F32,
249 RTLIB::OLE_F64,
250 RTLIB::OLE_F128,
251 RTLIB::OGT_F32,
252 RTLIB::OGT_F64,
253 RTLIB::OGT_F128,
254 RTLIB::UO_F32,
255 RTLIB::UO_F64,
256 RTLIB::UO_F128,
257 RTLIB::O_F32,
258 RTLIB::O_F64,
259 RTLIB::O_F128,
260 })
261 setLibcallCallingConv(LC, CallingConv::ARM_AAPCS);
262 }
263
26499 // The APCS parameter registers.
265100 static const MCPhysReg GPRArgRegs[] = {
266101 ARM::R0, ARM::R1, ARM::R2, ARM::R3
348183
349184 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
350185
351 InitLibcallCallingConvs();
186 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
187 !Subtarget->isTargetWatchOS()) {
188 const auto &E = Subtarget->getTargetTriple().getEnvironment();
189
190 bool IsHFTarget = E == Triple::EABIHF || E == Triple::GNUEABIHF ||
191 E == Triple::MuslEABIHF;
192 // Windows is a special case. Technically, we will replace all of the "GNU"
193 // calls with calls to MSVCRT if appropriate and adjust the calling
194 // convention then.
195 IsHFTarget = IsHFTarget || Subtarget->isTargetWindows();
196
197 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
198 setLibcallCallingConv(static_cast(LCID),
199 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
200 : CallingConv::ARM_AAPCS);
201 }
352202
353203 if (Subtarget->isTargetMachO()) {
354204 // Uses VFP for Thumb libfuncs if available.
536536 bool InsertFencesForAtomic;
537537
538538 bool HasStandaloneRem = true;
539
540 void InitLibcallCallingConvs();
541539
542540 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
543541 void addDRTypeForNEON(MVT VT);
1717 define double @powi_d(double %a, i32 %b) {
1818 ; CHECK-LABEL: powi_d:
1919 ; SOFT: {{(bl|b)}} __powidf2
20 ; HARD: bl __powidf2
20 ; HARD: b __powidf2
2121 %1 = call double @llvm.powi.f64(double %a, i32 %b)
2222 ret double %1
2323 }
1717 define float @powi_f(float %a, i32 %b) {
1818 ; CHECK-LABEL: powi_f:
1919 ; SOFT: bl __powisf2
20 ; HARD: bl __powisf2
20 ; HARD: b __powisf2
2121 %1 = call float @llvm.powi.f32(float %a, i32 %b)
2222 ret float %1
2323 }
0 ; RUN: llc -mtriple thumbv7-unknown-none-eabi -float-abi soft -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-MATCH
1 ; RUN: llc -mtriple thumbv7-unknown-none-eabi -float-abi hard -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-MISMATCH -check-prefix CHECK-TO-SOFT
2 ; RUN: llc -mtriple thumbv7-unknown-none-eabihf -float-abi soft -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-MISMATCH -check-prefix CHECK-TO-HARD
3 ; RUN: llc -mtriple thumbv7-unknown-none-eabihf -float-abi hard -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-MATCH
4
5 ; RUN: llc -mtriple thumbv7-unknown-none-gnueabi -float-abi soft -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-MATCH
6 ; RUN: llc -mtriple thumbv7-unknown-none-gnueabi -float-abi hard -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-MISMATCH -check-prefix CHECK-TO-SOFT
7 ; RUN: llc -mtriple thumbv7-unknown-none-gnueabihf -float-abi soft -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-MISMATCH -check-prefix CHECK-TO-HARD
8 ; RUN: llc -mtriple thumbv7-unknown-none-gnueabihf -float-abi hard -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-MATCH
9
10 ; RUN: llc -mtriple thumbv7-unknown-none-musleabi -float-abi soft -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-MATCH
11 ; RUN: llc -mtriple thumbv7-unknown-none-musleabi -float-abi hard -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-MISMATCH -check-prefix CHECK-TO-SOFT
12 ; RUN: llc -mtriple thumbv7-unknown-none-musleabihf -float-abi soft -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-MISMATCH -check-prefix CHECK-TO-HARD
13 ; RUN: llc -mtriple thumbv7-unknown-none-musleabihf -float-abi hard -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-MATCH
14
15 declare float @llvm.powi.f32(float, i32)
16
17 define float @f(float %f, i32 %i) {
18 entry:
19 %0 = call float @llvm.powi.f32(float %f, i32 %i)
20 ret float %0
21 }
22
23 ; CHECK-MATCH: b __powisf2
24 ; CHECK-MISMATCH: bl __powisf2
25 ; CHECK-TO-SOFT: vmov s0, r0
26 ; CHECK-TO-HARD: vmov r0, s0
27
28 declare double @llvm.powi.f64(double, i32)
29
30 define double @g(double %d, i32 %i) {
31 entry:
32 %0 = call double @llvm.powi.f64(double %d, i32 %i)
33 ret double %0
34 }
35
36 ; CHECK-MATCH: b __powidf2
37 ; CHECK-MISMATCH: bl __powidf2
38 ; CHECK-TO-SOFT: vmov d0, r0, r1
39 ; CHECK-TO-HARD: vmov r0, r1, d0
40