llvm.org GIT mirror llvm / 525ae45
Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199193 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 6 years ago
12 changed file(s) with 361 addition(s) and 330 deletion(s). Raw diff Collapse all Expand all
353353
354354 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
355355 XOPA = 22 << Op0Shift,
356
357 // PD - Prefix code for packed double precision vector floating point
358 // operations performed in the SSE registers.
359 PD = 23 << Op0Shift,
360
361 // T8PD - Prefix before and after 0x0F. Combination of T8 and PD.
362 T8PD = 24 << Op0Shift,
363
364 // TAPD - Prefix before and after 0x0F. Combination of TA and PD.
365 TAPD = 25 << Op0Shift,
356366
357367 //===------------------------------------------------------------------===//
358368 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
716716 case X86II::TA: // 0F 3A
717717 VEX_5M = 0x3;
718718 break;
719 case X86II::T8PD: // 66 0F 38
720 VEX_PP = 0x1;
721 VEX_5M = 0x2;
722 break;
719723 case X86II::T8XS: // F3 0F 38
720724 VEX_PP = 0x2;
721725 VEX_5M = 0x2;
724728 VEX_PP = 0x3;
725729 VEX_5M = 0x2;
726730 break;
731 case X86II::TAPD: // 66 0F 3A
732 VEX_PP = 0x1;
733 VEX_5M = 0x3;
734 break;
727735 case X86II::TAXD: // F2 0F 3A
728736 VEX_PP = 0x3;
729737 VEX_5M = 0x3;
738 break;
739 case X86II::PD: // 66 0F
740 VEX_PP = 0x1;
730741 break;
731742 case X86II::XS: // F3 0F
732743 VEX_PP = 0x2;
12141225 case X86II::A7: // 0F A7
12151226 Need0FPrefix = true;
12161227 break;
1228 case X86II::PD: // 66 0F
1229 case X86II::T8PD: // 66 0F 38
1230 case X86II::TAPD: // 66 0F 3A
1231 EmitByte(0x66, CurByte, OS);
1232 Need0FPrefix = true;
1233 break;
12171234 case X86II::XS: // F3 0F
12181235 case X86II::T8XS: // F3 0F 38
12191236 EmitByte(0xF3, CurByte, OS);
12511268
12521269 // FIXME: Pull this up into previous switch if REX can be moved earlier.
12531270 switch (TSFlags & X86II::Op0Mask) {
1271 case X86II::T8PD: // 66 0F 38
12541272 case X86II::T8XS: // F3 0F 38
12551273 case X86II::T8XD: // F2 0F 38
12561274 case X86II::T8: // 0F 38
12571275 EmitByte(0x38, CurByte, OS);
12581276 break;
1277 case X86II::TAPD: // 66 0F 3A
12591278 case X86II::TAXD: // F2 0F 3A
12601279 case X86II::TA: // 0F 3A
12611280 EmitByte(0x3A, CurByte, OS);
695695 Need0FPrefix = true;
696696 break;
697697 case X86II::REP: break; // already handled.
698 case X86II::PD: // 66 0F
699 case X86II::T8PD: // 66 0F 38
700 case X86II::TAPD: // 66 0F 3A
701 MCE.emitByte(0x66);
702 Need0FPrefix = true;
703 break;
698704 case X86II::T8XS: // F3 0F 38
699705 case X86II::XS: // F3 0F
700706 MCE.emitByte(0xF3);
727733 MCE.emitByte(0x0F);
728734
729735 switch (Desc->TSFlags & X86II::Op0Mask) {
736 case X86II::T8PD: // 66 0F 38
730737 case X86II::T8XD: // F2 0F 38
731738 case X86II::T8XS: // F3 0F 38
732739 case X86II::T8: // 0F 38
733740 MCE.emitByte(0x38);
734741 break;
742 case X86II::TAPD: // 66 0F 38
735743 case X86II::TAXD: // F2 0F 38
736744 case X86II::TA: // 0F 3A
737745 MCE.emitByte(0x3A);
881889 case X86II::TA: // 0F 3A
882890 VEX_5M = 0x3;
883891 break;
892 case X86II::T8PD: // 66 0F 38
893 VEX_PP = 0x1;
894 VEX_5M = 0x2;
895 break;
884896 case X86II::T8XS: // F3 0F 38
885897 VEX_PP = 0x2;
886898 VEX_5M = 0x2;
889901 VEX_PP = 0x3;
890902 VEX_5M = 0x2;
891903 break;
904 case X86II::TAPD: // 66 0F 3A
905 VEX_PP = 0x1;
906 VEX_5M = 0x3;
907 break;
892908 case X86II::TAXD: // F2 0F 3A
893909 VEX_PP = 0x3;
894910 VEX_5M = 0x3;
911 break;
912 case X86II::PD: // 66 0F
913 VEX_PP = 0x1;
895914 break;
896915 case X86II::XS: // F3 0F
897916 VEX_PP = 0x2;
743743 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
744744 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
745745 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
746 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
746 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512, VEX_W;
747747
748748 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
749749 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
750750 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
751 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
751 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512, VEX_W;
752752
753753 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
754754 (COPY_TO_REGCLASS (VPCMPGTDZrr
842842 defm VCMPPSZ : avx512_cmp_packed
843843 "ps", SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
844844 defm VCMPPDZ : avx512_cmp_packed
845 "pd", SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
845 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
846846 EVEX_CD8<64, CD8VF>;
847847
848848 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
11021102
11031103 multiclass avx512_mask_unpck_bw opc, string OpcodeStr> {
11041104 defm BW : avx512_mask_unpck,
1105 VEX_4V, VEX_L, OpSize, TB;
1105 VEX_4V, VEX_L, PD;
11061106 }
11071107
11081108 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
11541154 multiclass avx512_mask_shiftop_w opc1, bits<8> opc2, string OpcodeStr,
11551155 SDNode OpNode> {
11561156 defm W : avx512_mask_shiftop,
1157 VEX, OpSize, TA, VEX_W;
1157 VEX, TAPD, VEX_W;
11581158 }
11591159
11601160 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
12271227 EVEX_V512, EVEX_CD8<32, CD8VF>;
12281228 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
12291229 "vmovapd", SSEPackedDouble>,
1230 OpSize, EVEX_V512, VEX_W,
1230 PD, EVEX_V512, VEX_W,
12311231 EVEX_CD8<64, CD8VF>;
12321232 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
12331233 "vmovups", SSEPackedSingle>,
12341234 EVEX_V512, EVEX_CD8<32, CD8VF>;
12351235 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
12361236 "vmovupd", SSEPackedDouble>,
1237 OpSize, EVEX_V512, VEX_W,
1237 PD, EVEX_V512, VEX_W,
12381238 EVEX_CD8<64, CD8VF>;
12391239 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
12401240 "vmovaps\t{$src, $dst|$dst, $src}",
12441244 "vmovapd\t{$src, $dst|$dst, $src}",
12451245 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
12461246 SSEPackedDouble>, EVEX, EVEX_V512,
1247 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1247 PD, VEX_W, EVEX_CD8<64, CD8VF>;
12481248 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
12491249 "vmovups\t{$src, $dst|$dst, $src}",
12501250 [(store (v16f32 VR512:$src), addr:$dst)],
12531253 "vmovupd\t{$src, $dst|$dst, $src}",
12541254 [(store (v8f64 VR512:$src), addr:$dst)],
12551255 SSEPackedDouble>, EVEX, EVEX_V512,
1256 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1256 PD, VEX_W, EVEX_CD8<64, CD8VF>;
12571257
12581258 let hasSideEffects = 0 in {
12591259 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
14201420 "vmovq\t{$src, $dst|$dst, $src}",
14211421 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
14221422 (iPTR 0)))],
1423 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1423 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
14241424 Requires<[HasAVX512, In64BitMode]>;
14251425
14261426 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
14281428 "vmovq\t{$src, $dst|$dst, $src}",
14291429 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
14301430 addr:$dst)], IIC_SSE_MOVDQ>,
1431 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1431 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
14321432 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
14331433
14341434 // Move Scalar Single to Double Int
17691769
17701770 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
17711771 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1772 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1772 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
17731773
17741774 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
17751775 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
17801780 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
17811781
17821782 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1783 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1783 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8PD,
17841784 EVEX_V512, EVEX_CD8<64, CD8VF>;
17851785
17861786 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
17991799
18001800 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
18011801 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1802 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1802 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
18031803 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
18041804 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1805 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1805 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
18061806
18071807 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
18081808 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1809 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1809 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
18101810 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
18111811 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1812 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1812 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
18131813
18141814 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
18151815 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1816 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1816 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
18171817 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
18181818 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1819 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1819 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
18201820
18211821 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
18221822 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1823 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1823 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
18241824 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
18251825 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1826 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1826 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
18271827
18281828 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
18291829 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
18751875 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
18761876 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
18771877 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1878 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1878 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
18791879 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
18801880 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
18811881 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
18821882 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
18831883 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1884 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1884 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
18851885
18861886 multiclass avx512_unpack_int opc, string OpcodeStr, SDNode OpNode,
18871887 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
19341934 }
19351935
19361936 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1937 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1937 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
19381938
19391939 let ExeDomain = SSEPackedSingle in
19401940 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1941 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1941 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
19421942 EVEX_CD8<32, CD8VF>;
19431943 let ExeDomain = SSEPackedDouble in
19441944 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1945 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1945 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
19461946 VEX_W, EVEX_CD8<32, CD8VF>;
19471947
19481948 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
20372037 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
20382038 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
20392039 SSE_ALU_ITINS_P.d, 1>,
2040 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2040 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
20412041
20422042 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
20432043 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
20452045 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
20462046 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
20472047 SSE_ALU_ITINS_P.d, 1>,
2048 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2048 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
20492049
20502050 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
20512051 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
20592059 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
20602060 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
20612061 SSE_ALU_ITINS_P.d, 1>,
2062 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2062 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
20632063 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
20642064 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
20652065 SSE_ALU_ITINS_P.d, 1>,
2066 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2066 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
20672067
20682068 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
20692069 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
20752075 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
20762076 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
20772077 SSE_ALU_ITINS_P.d, 0>,
2078 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2078 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
20792079 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
20802080 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
20812081 SSE_ALU_ITINS_P.d, 0>,
2082 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2082 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
20832083
20842084 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
20852085 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
28392839
28402840 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
28412841 memopv8f64, f512mem, v8f32, v8f64,
2842 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2842 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
28432843 EVEX_CD8<64, CD8VF>;
28442844
28452845 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
28762876
28772877 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
28782878 memopv8f64, f512mem, v8i32, v8f64,
2879 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2879 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
28802880 EVEX_CD8<64, CD8VF>;
28812881
28822882 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
29452945 }
29462946
29472947 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
2948 memopv16f32, f512mem, SSEPackedSingle>, OpSize,
2948 memopv16f32, f512mem, SSEPackedSingle>, PD,
29492949 EVEX_V512, EVEX_CD8<32, CD8VF>;
29502950 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
29512951 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
30183018 "ucomiss">, TB, EVEX, VEX_LIG,
30193019 EVEX_CD8<32, CD8VT1>;
30203020 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3021 "ucomisd">, TB, OpSize, EVEX,
3021 "ucomisd">, PD, EVEX,
30223022 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
30233023 let Pattern = [] in {
30243024 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
30253025 "comiss">, TB, EVEX, VEX_LIG,
30263026 EVEX_CD8<32, CD8VT1>;
30273027 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3028 "comisd">, TB, OpSize, EVEX,
3028 "comisd">, PD, EVEX,
30293029 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
30303030 }
30313031 let isCodeGenOnly = 1 in {
30333033 load, "ucomiss">, TB, EVEX, VEX_LIG,
30343034 EVEX_CD8<32, CD8VT1>;
30353035 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3036 load, "ucomisd">, TB, OpSize, EVEX,
3036 load, "ucomisd">, PD, EVEX,
30373037 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
30383038
30393039 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
30403040 load, "comiss">, TB, EVEX, VEX_LIG,
30413041 EVEX_CD8<32, CD8VT1>;
30423042 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3043 load, "comisd">, TB, OpSize, EVEX,
3043 load, "comisd">, PD, EVEX,
30443044 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
30453045 }
30463046 }
37953795 defm VSHUFPSZ : avx512_shufp
37963796 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
37973797 defm VSHUFPDZ : avx512_shufp
3798 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3798 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
37993799
38003800 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
38013801 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
13621362 let SchedRW = [WriteALU] in {
13631363 def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
13641364 "adcx{l}\t{$src, $dst|$dst, $src}",
1365 [], IIC_BIN_NONMEM>, T8, OpSize;
1365 [], IIC_BIN_NONMEM>, T8PD;
13661366
13671367 def ADCX64rr : I<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
13681368 "adcx{q}\t{$src, $dst|$dst, $src}",
1369 [], IIC_BIN_NONMEM>, T8, OpSize, REX_W, Requires<[In64BitMode]>;
1369 [], IIC_BIN_NONMEM>, T8PD, REX_W, Requires<[In64BitMode]>;
13701370 } // SchedRW
13711371
13721372 let mayLoad = 1, SchedRW = [WriteALULd] in {
13731373 def ADCX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
13741374 "adcx{l}\t{$src, $dst|$dst, $src}",
1375 [], IIC_BIN_MEM>, T8, OpSize;
1375 [], IIC_BIN_MEM>, T8PD;
13761376
13771377 def ADCX64rm : I<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
13781378 "adcx{q}\t{$src, $dst|$dst, $src}",
1379 [], IIC_BIN_MEM>, T8, OpSize, REX_W, Requires<[In64BitMode]>;
1379 [], IIC_BIN_MEM>, T8PD, REX_W, Requires<[In64BitMode]>;
13801380 }
13811381 }
13821382
137137 class XOP8 { bits<5> Prefix = 20; }
138138 class XOP9 { bits<5> Prefix = 21; }
139139 class XOPA { bits<5> Prefix = 22; }
140 class PD { bits<5> Prefix = 23; }
141 class T8PD { bits<5> Prefix = 24; }
142 class TAPD { bits<5> Prefix = 25; }
140143 class VEX { bit hasVEXPrefix = 1; }
141144 class VEX_W { bit hasVEX_WPrefix = 1; }
142145 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
339342
340343 def __xs : XS;
341344 def __xd : XD;
345 def __pd : PD;
342346
343347 // SI - SSE 1 & 2 scalar instructions
344348 class SI o, Format F, dag outs, dag ins, string asm,
348352 !if(hasVEXPrefix /* VEX */, [UseAVX],
349353 !if(!eq(Prefix, __xs.Prefix), [UseSSE1],
350354 !if(!eq(Prefix, __xd.Prefix), [UseSSE2],
351 !if(hasOpSizePrefix, [UseSSE2], [UseSSE1])))));
355 !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1])))));
352356
353357 // AVX instructions have a 'v' prefix in the mnemonic
354358 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
372376 : I {
373377 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
374378 !if(hasVEXPrefix /* VEX */, [HasAVX],
375 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1])));
379 !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1])));
376380
377381 // AVX instructions have a 'v' prefix in the mnemonic
378382 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
382386 class MMXPI o, Format F, dag outs, dag ins, string asm, list pattern,
383387 InstrItinClass itin, Domain d>
384388 : I {
385 let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]);
389 let Predicates = !if(!eq(Prefix, __pd.Prefix), [HasSSE2], [HasSSE1]);
386390 }
387391
388392 // PIi8 - SSE 1 & 2 packed instructions with immediate
391395 : Ii8 {
392396 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
393397 !if(hasVEXPrefix /* VEX */, [HasAVX],
394 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1])));
398 !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1])));
395399
396400 // AVX instructions have a 'v' prefix in the mnemonic
397401 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
434438 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
435439 // S2SI - SSE2 instructions with XS prefix.
436440 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
437 // PDI - SSE2 instructions with TB and OpSize prefixes, packed double domain.
438 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
441 // PDI - SSE2 instructions with PD prefix, packed double domain.
442 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.
439443 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
440 // VPDI - SSE2 vector instructions with TB and OpSize prefixes in AVX form,
444 // VPDI - SSE2 vector instructions with PD prefix in AVX form,
441445 // packed double domain.
442 // VS2I - SSE2 scalar instructions with TB and OpSize prefixes in AVX form.
443 // S2I - SSE2 scalar instructions with TB and OpSize prefixes.
446 // VS2I - SSE2 scalar instructions with PD prefix in AVX form.
447 // S2I - SSE2 scalar instructions with PD prefix.
444448 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
445449 // MMX operands.
446450 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
460464 : Ii8, XS, Requires<[UseSSE2]>;
461465 class PDI o, Format F, dag outs, dag ins, string asm,
462466 list pattern, InstrItinClass itin = NoItinerary>
463 : I, TB, OpSize,
467 : I, PD,
464468 Requires<[UseSSE2]>;
465469 class PDIi8 o, Format F, dag outs, dag ins, string asm,
466470 list pattern, InstrItinClass itin = NoItinerary>
467 : Ii8, TB, OpSize,
471 : Ii8, PD,
468472 Requires<[UseSSE2]>;
469473 class VSDI o, Format F, dag outs, dag ins, string asm,
470474 list pattern, InstrItinClass itin = NoItinerary>
476480 Requires<[HasAVX]>;
477481 class VPDI o, Format F, dag outs, dag ins, string asm,
478482 list pattern, InstrItinClass itin = NoItinerary>
479 : I, TB,
480 OpSize, Requires<[HasAVX]>;
483 : I,
484 PD, Requires<[HasAVX]>;
481485 class VS2I o, Format F, dag outs, dag ins, string asm,
482486 list pattern, InstrItinClass itin = NoItinerary>
483 : I, TB,
484 OpSize, Requires<[UseAVX]>;
487 : I, PD,
488 Requires<[UseAVX]>;
485489 class S2I o, Format F, dag outs, dag ins, string asm,
486490 list pattern, InstrItinClass itin = NoItinerary>
487 : I, TB,
488 OpSize, Requires<[UseSSE2]>;
491 : I, PD, Requires<[UseSSE2]>;
489492 class MMXSDIi8 o, Format F, dag outs, dag ins, string asm,
490493 list pattern, InstrItinClass itin = NoItinerary>
491494 : Ii8, XD, Requires<[HasSSE2]>;
495498
496499 // SSE3 Instruction Templates:
497500 //
498 // S3I - SSE3 instructions with TB and OpSize prefixes.
501 // S3I - SSE3 instructions with PD prefixes.
499502 // S3SI - SSE3 instructions with XS prefix.
500503 // S3DI - SSE3 instructions with XD prefix.
501504
509512 Requires<[UseSSE3]>;
510513 class S3I o, Format F, dag outs, dag ins, string asm,
511514 list pattern, InstrItinClass itin = NoItinerary>
512 : I, TB, OpSize,
515 : I, PD,
513516 Requires<[UseSSE3]>;
514517
515518
526529
527530 class SS38I o, Format F, dag outs, dag ins, string asm,
528531 list pattern, InstrItinClass itin = NoItinerary>
529 : I, T8,
532 : I, T8PD,
530533 Requires<[UseSSSE3]>;
531534 class SS3AI o, Format F, dag outs, dag ins, string asm,
532535 list pattern, InstrItinClass itin = NoItinerary>
533 : Ii8, TA,
536 : Ii8, TAPD,
534537 Requires<[UseSSSE3]>;
535538 class MMXSS38I o, Format F, dag outs, dag ins, string asm,
536539 list pattern, InstrItinClass itin = NoItinerary>
548551 //
549552 class SS48I o, Format F, dag outs, dag ins, string asm,
550553 list pattern, InstrItinClass itin = NoItinerary>
551 : I, T8,
554 : I, T8PD,
552555 Requires<[UseSSE41]>;
553556 class SS4AIi8 o, Format F, dag outs, dag ins, string asm,
554557 list pattern, InstrItinClass itin = NoItinerary>
555 : Ii8, TA,
558 : Ii8, TAPD,
556559 Requires<[UseSSE41]>;
557560
558561 // SSE4.2 Instruction Templates:
560563 // SS428I - SSE 4.2 instructions with T8 prefix.
561564 class SS428I o, Format F, dag outs, dag ins, string asm,
562565 list pattern, InstrItinClass itin = NoItinerary>
563 : I, T8,
566 : I, T8PD,
564567 Requires<[UseSSE42]>;
565568
566569 // SS42FI - SSE 4.2 instructions with T8XD prefix.
572575 // SS42AI = SSE 4.2 instructions with TA prefix
573576 class SS42AI o, Format F, dag outs, dag ins, string asm,
574577 list pattern, InstrItinClass itin = NoItinerary>
575 : Ii8, TA,
578 : Ii8, TAPD,
576579 Requires<[UseSSE42]>;
577580
578581 // AVX Instruction Templates:
579582 // Instructions introduced in AVX (no SSE equivalent forms)
580583 //
581 // AVX8I - AVX instructions with T8 and OpSize prefix.
582 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
584 // AVX8I - AVX instructions with T8PD prefix.
585 // AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8.
583586 class AVX8I o, Format F, dag outs, dag ins, string asm,
584587 list pattern, InstrItinClass itin = NoItinerary>
585 : I, T8, OpSize,
588 : I, T8PD,
586589 Requires<[HasAVX]>;
587590 class AVXAIi8 o, Format F, dag outs, dag ins, string asm,
588591 list pattern, InstrItinClass itin = NoItinerary>
589 : Ii8, TA, OpSize,
592 : Ii8, TAPD,
590593 Requires<[HasAVX]>;
591594
592595 // AVX2 Instruction Templates:
593596 // Instructions introduced in AVX2 (no SSE equivalent forms)
594597 //
595 // AVX28I - AVX2 instructions with T8 and OpSize prefix.
596 // AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
598 // AVX28I - AVX2 instructions with T8PD prefix.
599 // AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8.
597600 class AVX28I o, Format F, dag outs, dag ins, string asm,
598601 list pattern, InstrItinClass itin = NoItinerary>
599 : I, T8, OpSize,
602 : I, T8PD,
600603 Requires<[HasAVX2]>;
601604 class AVX2AIi8 o, Format F, dag outs, dag ins, string asm,
602605 list pattern, InstrItinClass itin = NoItinerary>
603 : Ii8, TA, OpSize,
606 : Ii8, TAPD,
604607 Requires<[HasAVX2]>;
605608
606609
607610 // AVX-512 Instruction Templates:
608611 // Instructions introduced in AVX-512 (no SSE equivalent forms)
609612 //
610 // AVX5128I - AVX-512 instructions with T8 and OpSize prefix.
611 // AVX512AIi8 - AVX-512 instructions with TA, OpSize prefix and ImmT = Imm8.
612 // AVX512PDI - AVX-512 instructions with TB, OpSize, double packed.
613 // AVX5128I - AVX-512 instructions with T8PD prefix.
614 // AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8.
615 // AVX512PDI - AVX-512 instructions with PD, double packed.
613616 // AVX512PSI - AVX-512 instructions with TB, single packed.
614617 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
615618 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
616 // AVX512BI - AVX-512 instructions with TB, OpSize, int packed domain.
617 // AVX512SI - AVX-512 scalar instructions with TB and OpSize prefixes.
619 // AVX512BI - AVX-512 instructions with PD, int packed domain.
620 // AVX512SI - AVX-512 scalar instructions with PD prefix.
618621
619622 class AVX5128I o, Format F, dag outs, dag ins, string asm,
620623 list pattern, InstrItinClass itin = NoItinerary>
621 : I, T8, OpSize,
624 : I, T8PD,
622625 Requires<[HasAVX512]>;
623626 class AVX512XS8I o, Format F, dag outs, dag ins, string asm,
624627 list pattern, InstrItinClass itin = NoItinerary>
634637 Requires<[HasAVX512]>;
635638 class AVX512BI o, Format F, dag outs, dag ins, string asm,
636639 list pattern, InstrItinClass itin = NoItinerary>
637 : I, TB, OpSize,
640 : I, PD,
638641 Requires<[HasAVX512]>;
639642 class AVX512BIi8 o, Format F, dag outs, dag ins, string asm,
640643 list pattern, InstrItinClass itin = NoItinerary>
641 : Ii8, TB, OpSize,
644 : Ii8, PD,
642645 Requires<[HasAVX512]>;
643646 class AVX512SI o, Format F, dag outs, dag ins, string asm,
644647 list pattern, InstrItinClass itin = NoItinerary>
645 : I, TB, OpSize,
648 : I, PD,
646649 Requires<[HasAVX512]>;
647650 class AVX512AIi8 o, Format F, dag outs, dag ins, string asm,
648651 list pattern, InstrItinClass itin = NoItinerary>
649 : Ii8, TA, OpSize,
652 : Ii8, TAPD,
650653 Requires<[HasAVX512]>;
651654 class AVX512Ii8 o, Format F, dag outs, dag ins, string asm,
652655 list pattern, InstrItinClass itin = NoItinerary>
653656 : Ii8, TB,
654 Requires<[HasAVX512]>;
657 Requires<[HasAVX512]>;
655658 class AVX512PDI o, Format F, dag outs, dag ins, string asm,
656659 list pattern, InstrItinClass itin = NoItinerary>
657 : I, TB,
658 OpSize, Requires<[HasAVX512]>;
660 : I, PD,
661 Requires<[HasAVX512]>;
659662 class AVX512PSI o, Format F, dag outs, dag ins, string asm,
660663 list pattern, InstrItinClass itin = NoItinerary>
661664 : I, TB,
668671 : I, TB, Requires<[HasAVX512]>;
669672 class AVX512FMA3 o, Format F, dag outs, dag ins, string asm,
670673 listpattern, InstrItinClass itin = NoItinerary>
671 : I, T8,
672 OpSize, EVEX_4V, Requires<[HasAVX512]>;
674 : I, T8PD,
675 EVEX_4V, Requires<[HasAVX512]>;
673676
674677 // AES Instruction Templates:
675678 //
677680 // These use the same encoding as the SSE4.2 T8 and TA encodings.
678681 class AES8I o, Format F, dag outs, dag ins, string asm,
679682 listpattern, InstrItinClass itin = IIC_AES>
680 : I, T8,
683 : I, T8PD,
681684 Requires<[HasAES]>;
682685
683686 class AESAI o, Format F, dag outs, dag ins, string asm,
684687 list pattern, InstrItinClass itin = NoItinerary>
685 : Ii8, TA,
688 : Ii8, TAPD,
686689 Requires<[HasAES]>;
687690
688691 // PCLMUL Instruction Templates
689692 class PCLMULIi8 o, Format F, dag outs, dag ins, string asm,
690693 listpattern, InstrItinClass itin = NoItinerary>
691 : Ii8, TA,
692 OpSize, Requires<[HasPCLMUL]>;
694 : Ii8, TAPD,
695 Requires<[HasPCLMUL]>;
693696
694697 class AVXPCLMULIi8 o, Format F, dag outs, dag ins, string asm,
695698 listpattern, InstrItinClass itin = NoItinerary>
696 : Ii8, TA,
697 OpSize, VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
699 : Ii8, TAPD,
700 VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
698701
699702 // FMA3 Instruction Templates
700703 class FMA3 o, Format F, dag outs, dag ins, string asm,
701704 listpattern, InstrItinClass itin = NoItinerary>
702 : I, T8,
703 OpSize, VEX_4V, FMASC, Requires<[HasFMA]>;
705 : I, T8PD,
706 VEX_4V, FMASC, Requires<[HasFMA]>;
704707
705708 // FMA4 Instruction Templates
706709 class FMA4 o, Format F, dag outs, dag ins, string asm,
707710 listpattern, InstrItinClass itin = NoItinerary>
708 : Ii8, TA,
709 OpSize, VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
711 : Ii8, TAPD,
712 VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
710713
711714 // XOP 2, 3 and 4 Operand Instruction Template
712715 class IXOP o, Format F, dag outs, dag ins, string asm,
723726 // XOP 5 operand instruction (VEX encoding!)
724727 class IXOP5 o, Format F, dag outs, dag ins, string asm,
725728 listpattern, InstrItinClass itin = NoItinerary>
726 : Ii8, TA,
727 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
729 : Ii8, TAPD,
730 VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
728731
729732 // X86-64 Instruction templates...
730733 //
781784 // MMXI - MMX instructions with TB prefix.
782785 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
783786 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
784 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
787 // MMX2I - MMX / SSE2 instructions with PD prefix.
785788 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
786789 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
787790 // MMXID - MMX instructions with XD prefix.
800803 : I, TB, REX_W, Requires<[HasMMX]>;
801804 class MMX2I o, Format F, dag outs, dag ins, string asm,
802805 list pattern, InstrItinClass itin = NoItinerary>
803 : I, TB, OpSize, Requires<[HasMMX]>;
806 : I, PD, Requires<[HasMMX]>;
804807 class MMXIi8 o, Format F, dag outs, dag ins, string asm,
805808 list pattern, InstrItinClass itin = NoItinerary>
806809 : Ii8, TB, Requires<[HasMMX]>;
526526 MMX_CVT_PS_ITINS, SSEPackedSingle>, TB;
527527 defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
528528 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
529 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
529 MMX_CVT_PD_ITINS, SSEPackedDouble>, PD;
530530 defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
531531 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
532532 MMX_CVT_PS_ITINS, SSEPackedSingle>, TB;
533533 defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
534534 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
535 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
535 MMX_CVT_PD_ITINS, SSEPackedDouble>, PD;
536536 defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
537537 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
538 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
538 MMX_CVT_PD_ITINS, SSEPackedDouble>, PD;
539539 let Constraints = "$src1 = $dst" in {
540540 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
541541 int_x86_sse_cvtpi2ps,
814814 TB, VEX;
815815 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
816816 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
817 TB, OpSize, VEX;
817 PD, VEX;
818818 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
819819 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
820820 TB, VEX;
821821 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
822822 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
823 TB, OpSize, VEX;
823 PD, VEX;
824824
825825 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
826826 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
827827 TB, VEX, VEX_L;
828828 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
829829 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
830 TB, OpSize, VEX, VEX_L;
830 PD, VEX, VEX_L;
831831 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
832832 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
833833 TB, VEX, VEX_L;
834834 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
835835 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
836 TB, OpSize, VEX, VEX_L;
836 PD, VEX, VEX_L;
837837 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
838838 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
839839 TB;
840840 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
841841 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
842 TB, OpSize;
842 PD;
843843 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
844844 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
845845 TB;
846846 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
847847 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
848 TB, OpSize;
848 PD;
849849
850850 let SchedRW = [WriteStore] in {
851851 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
11491149 !strconcat(base_opc, "d", asm_opr),
11501150 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
11511151 (scalar_to_vector (loadf64 addr:$src2)))))],
1152 itin, SSEPackedDouble>, TB, OpSize,
1152 itin, SSEPackedDouble>, PD,
11531153 Sched<[WriteShuffleLd, ReadAfterLd]>;
11541154
11551155 }
23922392 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
23932393 "ucomiss">, TB, VEX, VEX_LIG;
23942394 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2395 "ucomisd">, TB, OpSize, VEX, VEX_LIG;
2395 "ucomisd">, PD, VEX, VEX_LIG;
23962396 let Pattern = [] in {
23972397 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
23982398 "comiss">, TB, VEX, VEX_LIG;
23992399 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2400 "comisd">, TB, OpSize, VEX, VEX_LIG;
2400 "comisd">, PD, VEX, VEX_LIG;
24012401 }
24022402
24032403 let isCodeGenOnly = 1 in {
24042404 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
24052405 load, "ucomiss">, TB, VEX;
24062406 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2407 load, "ucomisd">, TB, OpSize, VEX;
2407 load, "ucomisd">, PD, VEX;
24082408
24092409 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
24102410 load, "comiss">, TB, VEX;
24112411 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2412 load, "comisd">, TB, OpSize, VEX;
2412 load, "comisd">, PD, VEX;
24132413 }
24142414 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
24152415 "ucomiss">, TB;
24162416 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2417 "ucomisd">, TB, OpSize;
2417 "ucomisd">, PD;
24182418
24192419 let Pattern = [] in {
24202420 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
24212421 "comiss">, TB;
24222422 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2423 "comisd">, TB, OpSize;
2423 "comisd">, PD;
24242424 }
24252425
24262426 let isCodeGenOnly = 1 in {
24272427 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
24282428 load, "ucomiss">, TB;
24292429 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2430 load, "ucomisd">, TB, OpSize;
2430 load, "ucomisd">, PD;
24312431
24322432 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
24332433 "comiss">, TB;
24342434 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2435 "comisd">, TB, OpSize;
2435 "comisd">, PD;
24362436 }
24372437 } // Defs = [EFLAGS]
24382438
24712471 defm VCMPPD : sse12_cmp_packed
24722472 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
24732473 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2474 SSEPackedDouble>, TB, OpSize, VEX_4V;
2474 SSEPackedDouble>, PD, VEX_4V;
24752475 defm VCMPPSY : sse12_cmp_packed
24762476 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
24772477 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
24792479 defm VCMPPDY : sse12_cmp_packed
24802480 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
24812481 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2482 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2482 SSEPackedDouble>, PD, VEX_4V, VEX_L;
24832483 let Constraints = "$src1 = $dst" in {
24842484 defm CMPPS : sse12_cmp_packed
24852485 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
24882488 defm CMPPD : sse12_cmp_packed
24892489 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
24902490 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2491 SSEPackedDouble, SSE_ALU_F64P>, TB, OpSize;
2491 SSEPackedDouble, SSE_ALU_F64P>, PD;
24922492 }
24932493
24942494 let Predicates = [HasAVX] in {
25542554 loadv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
25552555 defm VSHUFPD : sse12_shuffle
25562556 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2557 loadv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2557 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
25582558 defm VSHUFPDY : sse12_shuffle
25592559 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2560 loadv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2560 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
25612561
25622562 let Constraints = "$src1 = $dst" in {
25632563 defm SHUFPS : sse12_shuffle
25642564 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2565 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2566 TB;
2565 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>, TB;
25672566 defm SHUFPD : sse12_shuffle
25682567 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2569 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2570 TB, OpSize;
2568 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>, PD;
25712569 }
25722570
25732571 let Predicates = [HasAVX] in {
26422640 SSEPackedSingle>, TB, VEX_4V;
26432641 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
26442642 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2645 SSEPackedDouble>, TB, OpSize, VEX_4V;
2643 SSEPackedDouble>, PD, VEX_4V;
26462644 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
26472645 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
26482646 SSEPackedSingle>, TB, VEX_4V;
26492647 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
26502648 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2651 SSEPackedDouble>, TB, OpSize, VEX_4V;
2649 SSEPackedDouble>, PD, VEX_4V;
26522650
26532651 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
26542652 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
26552653 SSEPackedSingle>, TB, VEX_4V, VEX_L;
26562654 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
26572655 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2658 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2656 SSEPackedDouble>, PD, VEX_4V, VEX_L;
26592657 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
26602658 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
26612659 SSEPackedSingle>, TB, VEX_4V, VEX_L;
26622660 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
26632661 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2664 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2662 SSEPackedDouble>, PD, VEX_4V, VEX_L;
26652663
26662664 let Constraints = "$src1 = $dst" in {
26672665 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
26692667 SSEPackedSingle>, TB;
26702668 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
26712669 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2672 SSEPackedDouble>, TB, OpSize;
2670 SSEPackedDouble>, PD;
26732671 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
26742672 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
26752673 SSEPackedSingle>, TB;
26762674 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
26772675 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2678 SSEPackedDouble>, TB, OpSize;
2676 SSEPackedDouble>, PD;
26792677 } // Constraints = "$src1 = $dst"
26802678
26812679 let Predicates = [HasAVX1Only] in {
27332731 defm VMOVMSKPS : sse12_extr_sign_mask
27342732 "movmskps", SSEPackedSingle>, TB, VEX;
27352733 defm VMOVMSKPD : sse12_extr_sign_mask
2736 "movmskpd", SSEPackedDouble>, TB,
2737 OpSize, VEX;
2734 "movmskpd", SSEPackedDouble>, PD, VEX;
27382735 defm VMOVMSKPSY : sse12_extr_sign_mask
27392736 "movmskps", SSEPackedSingle>, TB,
27402737 VEX, VEX_L;
27412738 defm VMOVMSKPDY : sse12_extr_sign_mask
2742 "movmskpd", SSEPackedDouble>, TB,
2743 OpSize, VEX, VEX_L;
2739 "movmskpd", SSEPackedDouble>, PD,
2740 VEX, VEX_L;
27442741
27452742 def : Pat<(i32 (X86fgetsign FR32:$src)),
27462743 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
27572754 defm MOVMSKPS : sse12_extr_sign_mask
27582755 SSEPackedSingle>, TB;
27592756 defm MOVMSKPD : sse12_extr_sign_mask
2760 SSEPackedDouble>, TB, OpSize;
2757 SSEPackedDouble>, PD;
27612758
27622759 def : Pat<(i32 (X86fgetsign FR32:$src)),
27632760 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
28442841
28452842 defm V#NAME#PD : sse12_fp_packed
28462843 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2847 TB, OpSize, VEX_4V;
2844 PD, VEX_4V;
28482845
28492846 let Constraints = "$src1 = $dst" in {
28502847 defm PS : sse12_fp_packed
28532850
28542851 defm PD : sse12_fp_packed
28552852 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2856 TB, OpSize;
2853 PD;
28572854 }
28582855 }
28592856
28872884 (bc_v4i64 (v4f64 VR256:$src2))))],
28882885 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
28892886 (loadv4i64 addr:$src2)))], 0>,
2890 TB, OpSize, VEX_4V, VEX_L;
2887 PD, VEX_4V, VEX_L;
28912888
28922889 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
28932890 // are all promoted to v2i64, and the patterns are covered by the int
29042901 (bc_v2i64 (v2f64 VR128:$src2))))],
29052902 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
29062903 (loadv2i64 addr:$src2)))], 0>,
2907 TB, OpSize, VEX_4V;
2904 PD, VEX_4V;
29082905
29092906 let Constraints = "$src1 = $dst" in {
29102907 defm PS : sse12_fp_packed_logical_rm
29182915 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
29192916 (bc_v2i64 (v2f64 VR128:$src2))))],
29202917 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2921 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2918 (memopv2i64 addr:$src2)))]>, PD;
29222919 }
29232920 }
29242921
29522949 SSEPackedSingle, itins.s, 0>, TB, VEX_4V;
29532950 defm V#NAME#PD : sse12_fp_packed
29542951 VR128, v2f64, f128mem, loadv2f64,
2955 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V;
2952 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
29562953
29572954 defm V#NAME#PSY : sse12_fp_packed
29582955 OpNode, VR256, v8f32, f256mem, loadv8f32,
29592956 SSEPackedSingle, itins.s, 0>, TB, VEX_4V, VEX_L;
29602957 defm V#NAME#PDY : sse12_fp_packed
29612958 OpNode, VR256, v4f64, f256mem, loadv4f64,
2962 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V, VEX_L;
2959 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
29632960
29642961 let Constraints = "$src1 = $dst" in {
29652962 defm PS : sse12_fp_packed
29672964 itins.s>, TB;
29682965 defm PD : sse12_fp_packed
29692966 v2f64, f128mem, memopv2f64, SSEPackedDouble,
2970 itins.d>, TB, OpSize;
2967 itins.d>, PD;
29712968 }
29722969 }
29732970
43534350 }
43544351 } // ExeDomain = SSEPackedInt
43554352
4356 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, TB, OpSize;
4353 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
43574354 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
43584355 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
43594356
45064503 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
45074504 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
45084505 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4509 imm:$src2))]>, TB, OpSize, VEX,
4506 imm:$src2))]>, PD, VEX,
45104507 Sched<[WriteShuffle]>;
45114508 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
45124509 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
45174514
45184515 // Insert
45194516 let Predicates = [HasAVX] in
4520 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4517 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
45214518
45224519 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4523 defm PINSRW : sse2_pinsrw, TB, OpSize;
4520 defm PINSRW : sse2_pinsrw, PD;
45244521
45254522 } // ExeDomain = SSEPackedInt
45264523
51595156 let Predicates = [HasAVX] in {
51605157 let ExeDomain = SSEPackedSingle in {
51615158 defm VADDSUBPS : sse3_addsub
5162 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5159 f128mem, SSE_ALU_F32P, 0>, XD, VEX_4V;
51635160 defm VADDSUBPSY : sse3_addsub
5164 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
5161 f256mem, SSE_ALU_F32P, 0>, XD, VEX_4V, VEX_L;
51655162 }
51665163 let ExeDomain = SSEPackedDouble in {
51675164 defm VADDSUBPD : sse3_addsub
5168 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5165 f128mem, SSE_ALU_F64P, 0>, PD, VEX_4V;
51695166 defm VADDSUBPDY : sse3_addsub
5170 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
5167 f256mem, SSE_ALU_F64P, 0>, PD, VEX_4V, VEX_L;
51715168 }
51725169 }
51735170 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
51745171 let ExeDomain = SSEPackedSingle in
51755172 defm ADDSUBPS : sse3_addsub
5176 f128mem, SSE_ALU_F32P>, TB, XD;
5173 f128mem, SSE_ALU_F32P>, XD;
51775174 let ExeDomain = SSEPackedDouble in
51785175 defm ADDSUBPD : sse3_addsub
5179 f128mem, SSE_ALU_F64P>, TB, OpSize;
5176 f128mem, SSE_ALU_F64P>, PD;
51805177 }
51815178
51825179 //===---------------------------------------------------------------------===//
52635260 (ins VR128:$src),
52645261 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
52655262 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5266 OpSize, Sched<[WriteVecALU]>;
5263 Sched<[WriteVecALU]>;
52675264
52685265 def rm128 : SS38I
52695266 (ins i128mem:$src),
52715268 [(set VR128:$dst,
52725269 (IntId128
52735270 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5274 OpSize, Sched<[WriteVecALULd]>;
5271 Sched<[WriteVecALULd]>;
52755272 }
52765273
52775274 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
52815278 (ins VR256:$src),
52825279 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
52835280 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5284 OpSize, Sched<[WriteVecALU]>;
5281 Sched<[WriteVecALU]>;
52855282
52865283 def rm256 : SS38I
52875284 (ins i256mem:$src),
52885285 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
52895286 [(set VR256:$dst,
52905287 (IntId256
5291 (bitconvert (memopv4i64 addr:$src))))]>, OpSize,
5288 (bitconvert (memopv4i64 addr:$src))))]>,
52925289 Sched<[WriteVecALULd]>;
52935290 }
52945291
54085405 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
54095406 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
54105407 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5411 OpSize, Sched<[itins.Sched]>;
5408 Sched<[itins.Sched]>;
54125409 def rm : SS38I
54135410 (ins RC:$src1, x86memop:$src2),
54145411 !if(Is2Addr,
54165413 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
54175414 [(set RC:$dst,
54185415 (OpVT (OpNode RC:$src1,
5419 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize,
5416 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
54205417 Sched<[itins.Sched.Folded, ReadAfterLd]>;
54215418 }
54225419
54315428 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
54325429 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
54335430 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5434 OpSize, Sched<[itins.Sched]>;
5431 Sched<[itins.Sched]>;
54355432 def rm128 : SS38I
54365433 (ins VR128:$src1, i128mem:$src2),
54375434 !if(Is2Addr,
54395436 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
54405437 [(set VR128:$dst,
54415438 (IntId128 VR128:$src1,
5442 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize,
5439 (bitconvert (memopv2i64 addr:$src2))))]>,
54435440 Sched<[itins.Sched.Folded, ReadAfterLd]>;
54445441 }
54455442
54495446 def rr256 : SS38I
54505447 (ins VR256:$src1, VR256:$src2),
54515448 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5452 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5453 OpSize;
5449 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>;
54545450 def rm256 : SS38I
54555451 (ins VR256:$src1, i256mem:$src2),
54565452 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
54575453 [(set VR256:$dst,
5458 (IntId256 VR256:$src1,
5459 (bitconvert (loadv4i64 addr:$src2))))]>, OpSize;
5454 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>;
54605455 }
54615456
54625457 let ImmT = NoImm, Predicates = [HasAVX] in {
55825577 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
55835578 !strconcat(asm,
55845579 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5585 [], IIC_SSE_PALIGNRR>, OpSize, Sched<[WriteShuffle]>;
5580 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
55865581 let mayLoad = 1 in
55875582 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
55885583 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
55905585 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
55915586 !strconcat(asm,
55925587 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5593 [], IIC_SSE_PALIGNRM>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5588 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
55945589 }
55955590 }
55965591
56005595 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
56015596 !strconcat(asm,
56025597 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5603 []>, OpSize, Sched<[WriteShuffle]>;
5598 []>, Sched<[WriteShuffle]>;
56045599 let mayLoad = 1 in
56055600 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
56065601 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
56075602 !strconcat(asm,
56085603 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5609 []>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5604 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
56105605 }
56115606 }
56125607
56865681 OpndItins itins = DEFAULT_ITINS> {
56875682 def rr : SS48I
56885683 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5689 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>, OpSize;
5684 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>;
56905685
56915686 def rm : SS48I
56925687 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
56935688 [(set VR128:$dst,
56945689 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))],
5695 itins.rm>, OpSize;
5690 itins.rm>;
56965691 }
56975692
56985693 multiclass SS41I_binop_rm_int16_y opc, string OpcodeStr,
56995694 Intrinsic IntId> {
57005695 def Yrr : SS48I
57015696 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5702 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5697 [(set VR256:$dst, (IntId VR128:$src))]>;
57035698
57045699 def Yrm : SS48I
57055700 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5706 [(set VR256:$dst, (IntId (load addr:$src)))]>,
5707 OpSize;
5701 [(set VR256:$dst, (IntId (load addr:$src)))]>;
57085702 }
57095703
57105704 let Predicates = [HasAVX] in {
58665860 OpndItins itins = DEFAULT_ITINS> {
58675861 def rr : SS48I
58685862 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5869 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>, OpSize;
5863 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>;
58705864
58715865 def rm : SS48I
58725866 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
58735867 [(set VR128:$dst,
58745868 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))],
5875 itins.rm>,
5876 OpSize;
5869 itins.rm>;
58775870 }
58785871
58795872 multiclass SS41I_binop_rm_int8_y opc, string OpcodeStr,
58805873 Intrinsic IntId> {
58815874 def Yrr : SS48I
58825875 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5883 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5876 [(set VR256:$dst, (IntId VR128:$src))]>;
58845877
58855878 def Yrm : SS48I
58865879 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
58875880 [(set VR256:$dst,
5888 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5889 OpSize;
5881 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>;
58905882 }
58915883
58925884 let Predicates = [HasAVX] in {
59505942 OpndItins itins = DEFAULT_ITINS> {
59515943 def rr : SS48I
59525944 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5953 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5945 [(set VR128:$dst, (IntId VR128:$src))]>;
59545946
59555947 // Expecting a i16 load any extended to i32 value.
59565948 def rm : SS48I
59575949 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
59585950 [(set VR128:$dst, (IntId (bitconvert
5959 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5960 OpSize;
5951 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>;
59615952 }
59625953
59635954 multiclass SS41I_binop_rm_int4_y opc, string OpcodeStr,
59645955 Intrinsic IntId> {
59655956 def Yrr : SS48I
59665957 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5967 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5958 [(set VR256:$dst, (IntId VR128:$src))]>;
59685959
59695960 // Expecting a i16 load any extended to i32 value.
59705961 def Yrm : SS48I
59715962 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
59725963 [(set VR256:$dst, (IntId (bitconvert
5973 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5974 OpSize;
5964 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>;
59755965 }
59765966
59775967 let Predicates = [HasAVX] in {
62466236 !strconcat(OpcodeStr,
62476237 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
62486238 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6249 imm:$src2))]>,
6250 OpSize;
6239 imm:$src2))]>;
62516240 let neverHasSideEffects = 1, mayStore = 1 in
62526241 def mr : SS4AIi8
62536242 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
62546243 !strconcat(OpcodeStr,
62556244 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6256 []>, OpSize;
6245 []>;
62576246 // FIXME:
62586247 // There's an AssertZext in the way of writing the store pattern
62596248 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
62726261 (ins VR128:$src1, i32i8imm:$src2),
62736262 !strconcat(OpcodeStr,
62746263 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6275 []>, OpSize;
6264 []>;
62766265
62776266 let neverHasSideEffects = 1, mayStore = 1 in
62786267 def mr : SS4AIi8
62796268 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
62806269 !strconcat(OpcodeStr,
62816270 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6282 []>, OpSize;
6271 []>;
62836272 // FIXME:
62846273 // There's an AssertZext in the way of writing the store pattern
62856274 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
62986287 !strconcat(OpcodeStr,
62996288 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
63006289 [(set GR32:$dst,
6301 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
6290 (extractelt (v4i32 VR128:$src1), imm:$src2))]>;
63026291 def mr : SS4AIi8
63036292 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
63046293 !strconcat(OpcodeStr,
63056294 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
63066295 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6307 addr:$dst)]>, OpSize;
6296 addr:$dst)]>;
63086297 }
63096298
63106299 let Predicates = [HasAVX] in
63196308 !strconcat(OpcodeStr,
63206309 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
63216310 [(set GR64:$dst,
6322 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
6311 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, REX_W;
63236312 def mr : SS4AIi8
63246313 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
63256314 !strconcat(OpcodeStr,
63266315 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
63276316 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6328 addr:$dst)]>, OpSize, REX_W;
6317 addr:$dst)]>, REX_W;
63296318 }
63306319
63316320 let Predicates = [HasAVX] in
63436332 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
63446333 [(set GR32orGR64:$dst,
63456334 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6346 itins.rr>,
6347 OpSize;
6335 itins.rr>;
63486336 def mr : SS4AIi8
63496337 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
63506338 !strconcat(OpcodeStr,
63516339 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
63526340 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6353 addr:$dst)], itins.rm>, OpSize;
6341 addr:$dst)], itins.rm>;
63546342 }
63556343
63566344 let ExeDomain = SSEPackedSingle in {
63836371 !strconcat(asm,
63846372 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
63856373 [(set VR128:$dst,
6386 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>, OpSize;
6374 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>;
63876375 def rm : SS4AIi8
63886376 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
63896377 !if(Is2Addr,
63926380 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
63936381 [(set VR128:$dst,
63946382 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6395 imm:$src3))]>, OpSize;
6383 imm:$src3))]>;
63966384 }
63976385
63986386 let Predicates = [HasAVX] in
64086396 !strconcat(asm,
64096397 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
64106398 [(set VR128:$dst,
6411 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6412 OpSize;
6399 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>;
64136400 def rm : SS4AIi8
64146401 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
64156402 !if(Is2Addr,
64186405 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
64196406 [(set VR128:$dst,
64206407 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6421 imm:$src3)))]>, OpSize;
6408 imm:$src3)))]>;
64226409 }
64236410
64246411 let Predicates = [HasAVX] in
64346421 !strconcat(asm,
64356422 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
64366423 [(set VR128:$dst,
6437 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6438 OpSize;
6424 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>;
64396425 def rm : SS4AIi8
64406426 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
64416427 !if(Is2Addr,
64446430 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
64456431 [(set VR128:$dst,
64466432 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6447 imm:$src3)))]>, OpSize;
6433 imm:$src3)))]>;
64486434 }
64496435
64506436 let Predicates = [HasAVX] in
64656451 !strconcat(asm,
64666452 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
64676453 [(set VR128:$dst,
6468 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6469 OpSize;
6454 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>;
64706455 def rm : SS4AIi8
64716456 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
64726457 !if(Is2Addr,
64766461 [(set VR128:$dst,
64776462 (X86insrtps VR128:$src1,
64786463 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6479 imm:$src3))], itins.rm>, OpSize;
6464 imm:$src3))], itins.rm>;
64806465 }
64816466
64826467 let ExeDomain = SSEPackedSingle in {
65026487 !strconcat(OpcodeStr,
65036488 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
65046489 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6505 IIC_SSE_ROUNDPS_REG>,
6506 OpSize;
6490 IIC_SSE_ROUNDPS_REG>;
65076491
65086492 // Vector intrinsic operation, mem
65096493 def PSm : SS4AIi8
65126496 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
65136497 [(set RC:$dst,
65146498 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6515 IIC_SSE_ROUNDPS_MEM>,
6516 OpSize;
6499 IIC_SSE_ROUNDPS_MEM>;
65176500 } // ExeDomain = SSEPackedSingle
65186501
65196502 let ExeDomain = SSEPackedDouble in {
65236506 !strconcat(OpcodeStr,
65246507 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
65256508 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6526 IIC_SSE_ROUNDPS_REG>,
6527 OpSize;
6509 IIC_SSE_ROUNDPS_REG>;
65286510
65296511 // Vector intrinsic operation, mem
65306512 def PDm : SS4AIi8
65336515 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
65346516 [(set RC:$dst,
65356517 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6536 IIC_SSE_ROUNDPS_REG>,
6537 OpSize;
6518 IIC_SSE_ROUNDPS_REG>;
65386519 } // ExeDomain = SSEPackedDouble
65396520 }
65406521
65526533 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
65536534 !strconcat(OpcodeStr,
65546535 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6555 []>, OpSize;
6536 []>;
65566537
65576538 // Intrinsic operation, reg.
65586539 let isCodeGenOnly = 1 in
65636544 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
65646545 !strconcat(OpcodeStr,
65656546 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6566 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6567 OpSize;
6547 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>;
65686548
65696549 // Intrinsic operation, mem.
65706550 def SSm : SS4AIi8
65756555 !strconcat(OpcodeStr,
65766556 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
65776557 [(set VR128:$dst,
6578 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6579 OpSize;
6558 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>;
65806559
65816560 // Operation, reg.
65826561 let hasSideEffects = 0 in
65876566 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
65886567 !strconcat(OpcodeStr,
65896568 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6590 []>, OpSize;
6569 []>;
65916570
65926571 // Intrinsic operation, reg.
65936572 let isCodeGenOnly = 1 in
65986577 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
65996578 !strconcat(OpcodeStr,
66006579 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6601 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6602 OpSize;
6580 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>;
66036581
66046582 // Intrinsic operation, mem.
66056583 def SDm : SS4AIi8
66106588 !strconcat(OpcodeStr,
66116589 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
66126590 [(set VR128:$dst,
6613 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6614 OpSize;
6591 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>;
66156592 } // ExeDomain = GenericDomain
66166593 }
66176594
67586735 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
67596736 "vptest\t{$src2, $src1|$src1, $src2}",
67606737 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6761 OpSize, VEX;
6738 VEX;
67626739 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
67636740 "vptest\t{$src2, $src1|$src1, $src2}",
67646741 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6765 OpSize, VEX;
6742 VEX;
67666743
67676744 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
67686745 "vptest\t{$src2, $src1|$src1, $src2}",
67696746 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6770 OpSize, VEX, VEX_L;
6747 VEX, VEX_L;
67716748 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
67726749 "vptest\t{$src2, $src1|$src1, $src2}",
67736750 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6774 OpSize, VEX, VEX_L;
6751 VEX, VEX_L;
67756752 }
67766753
67776754 let Defs = [EFLAGS] in {
67786755 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
67796756 "ptest\t{$src2, $src1|$src1, $src2}",
6780 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6781 OpSize;
6757 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>;
67826758 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
67836759 "ptest\t{$src2, $src1|$src1, $src2}",
6784 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6785 OpSize;
6760 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>;
67866761 }
67876762
67886763 // The bit test instructions below are AVX only
67906765 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
67916766 def rr : SS48I
67926767 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6793 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6768 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, VEX;
67946769 def rm : SS48I
67956770 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6796 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6797 OpSize, VEX;
6771 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>, VEX;
67986772 }
67996773
68006774 let Defs = [EFLAGS], Predicates = [HasAVX] in {
68546828 def rr128 : SS48I
68556829 (ins VR128:$src),
68566830 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6857 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6831 [(set VR128:$dst, (IntId128 VR128:$src))]>;
68586832 def rm128 : SS48I
68596833 (ins i128mem:$src),
68606834 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
68616835 [(set VR128:$dst,
6862 (IntId128
6863 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6836 (IntId128 (bitconvert (memopv2i64 addr:$src))))]>;
68646837 }
68656838
68666839 let Predicates = [HasAVX] in
68806853 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
68816854 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
68826855 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
6883 itins.rr>, OpSize;
6856 itins.rr>;
68846857 def rm : SS48I
68856858 (ins VR128:$src1, i128mem:$src2),
68866859 !if(Is2Addr,
68876860 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
68886861 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
68896862 [(set VR128:$dst,
6890 (IntId128 VR128:$src1,
6891 (bitconvert (memopv2i64 addr:$src2))))],
6892 itins.rm>, OpSize;
6863 (IntId128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))],
6864 itins.rm>;
68936865 }
68946866
68956867 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
68996871 def Yrr : SS48I
69006872 (ins VR256:$src1, VR256:$src2),
69016873 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6902 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6874 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>;
69036875 def Yrm : SS48I
69046876 (ins VR256:$src1, i256mem:$src2),
69056877 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
69066878 [(set VR256:$dst,
6907 (IntId256 VR256:$src1,
6908 (bitconvert (loadv4i64 addr:$src2))))]>, OpSize;
6879 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>;
69096880 }
69106881
69116882
69206891 !if(Is2Addr,
69216892 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69226893 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6923 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6894 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
69246895 def rm : SS48I
69256896 (ins RC:$src1, x86memop:$src2),
69266897 !if(Is2Addr,
69276898 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69286899 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
69296900 [(set RC:$dst,
6930 (OpVT (OpNode RC:$src1,
6931 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6901 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>;
69326902 }
69336903
69346904 let Predicates = [HasAVX] in {
70357005 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
70367006 !strconcat(OpcodeStr,
70377007 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7038 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
7039 OpSize;
7008 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>;
70407009 def rmi : SS4AIi8
70417010 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
70427011 !if(Is2Addr,
70467015 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
70477016 [(set RC:$dst,
70487017 (IntId RC:$src1,
7049 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
7050 OpSize;
7018 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>;
70517019 }
70527020
70537021 let Predicates = [HasAVX] in {
71277095 !strconcat(OpcodeStr,
71287096 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
71297097 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7130 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
7098 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM;
71317099
71327100 def rm : Ii8
71337101 (ins RC:$src1, x86memop:$src2, RC:$src3),
71367104 [(set RC:$dst,
71377105 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
71387106 RC:$src3))],
7139 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
7107 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM;
71407108 }
71417109
71427110 let Predicates = [HasAVX] in {
72277195 !strconcat(OpcodeStr,
72287196 "\t{$src2, $dst|$dst, $src2}"),
72297197 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7230 itins.rr>, OpSize;
7198 itins.rr>;
72317199
72327200 def rm0 : SS48I
72337201 (ins VR128:$src1, x86memop:$src2),
72367204 [(set VR128:$dst,
72377205 (IntId VR128:$src1,
72387206 (bitconvert (mem_frag addr:$src2)), XMM0))],
7239 itins.rm>, OpSize;
7207 itins.rm>;
72407208 }
72417209 }
72427210
72967264 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
72977265 "vmovntdqa\t{$src, $dst|$dst, $src}",
72987266 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7299 OpSize, VEX;
7267 VEX;
73007268 let Predicates = [HasAVX2] in
73017269 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
73027270 "vmovntdqa\t{$src, $dst|$dst, $src}",
73037271 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7304 OpSize, VEX, VEX_L;
7272 VEX, VEX_L;
73057273 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
73067274 "movntdqa\t{$src, $dst|$dst, $src}",
7307 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7308 OpSize;
7275 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
73097276
73107277 //===----------------------------------------------------------------------===//
73117278 // SSE4.2 - Compare Instructions
73207287 !if(Is2Addr,
73217288 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
73227289 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7323 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7324 OpSize;
7290 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
73257291 def rm : SS428I
73267292 (ins RC:$src1, x86memop:$src2),
73277293 !if(Is2Addr,
73287294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
73297295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
73307296 [(set RC:$dst,
7331 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
7297 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
73327298 }
73337299
73347300 let Predicates = [HasAVX] in
73687334 def rr : SS42AI<0x62, MRMSrcReg, (outs),
73697335 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
73707336 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7371 []>, OpSize;
7337 []>;
73727338 let mayLoad = 1 in
73737339 def rm :SS42AI<0x62, MRMSrcMem, (outs),
73747340 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
73757341 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7376 []>, OpSize;
7342 []>;
73777343 }
73787344
73797345 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
74037369 def rr : SS42AI<0x60, MRMSrcReg, (outs),
74047370 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
74057371 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7406 []>, OpSize;
7372 []>;
74077373 let mayLoad = 1 in
74087374 def rm : SS42AI<0x60, MRMSrcMem, (outs),
74097375 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
74107376 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7411 []>, OpSize;
7377 []>;
74127378 }
74137379
74147380 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
74387404 def rr : SS42AI<0x63, MRMSrcReg, (outs),
74397405 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
74407406 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7441 []>, OpSize;
7407 []>;
74427408 let mayLoad = 1 in
74437409 def rm : SS42AI<0x63, MRMSrcMem, (outs),
74447410 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
74457411 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7446 []>, OpSize;
7412 []>;
74477413 }
74487414
74497415 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
74747440 def rr : SS42AI<0x61, MRMSrcReg, (outs),
74757441 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
74767442 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7477 []>, OpSize;
7443 []>;
74787444 let mayLoad = 1 in
74797445 def rm : SS42AI<0x61, MRMSrcMem, (outs),
74807446 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
74817447 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7482 []>, OpSize;
7448 []>;
74837449 }
74847450
74857451 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
76027568 !if(Is2Addr,
76037569 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
76047570 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7605 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7606 OpSize;
7571 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>;
76077572 def rm : AES8I
76087573 (ins VR128:$src1, i128mem:$src2),
76097574 !if(Is2Addr,
76107575 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
76117576 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76127577 [(set VR128:$dst,
7613 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7578 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>;
76147579 }
76157580
76167581 // Perform One Round of an AES Encryption/Decryption Flow
76437608 "vaesimc\t{$src1, $dst|$dst, $src1}",
76447609 [(set VR128:$dst,
76457610 (int_x86_aesni_aesimc VR128:$src1))]>,
7646 OpSize, VEX;
7611 VEX;
76477612 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
76487613 (ins i128mem:$src1),
76497614 "vaesimc\t{$src1, $dst|$dst, $src1}",
76507615 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7651 OpSize, VEX;
7616 VEX;
76527617 }
76537618 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
76547619 (ins VR128:$src1),
76557620 "aesimc\t{$src1, $dst|$dst, $src1}",
76567621 [(set VR128:$dst,
7657 (int_x86_aesni_aesimc VR128:$src1))]>,
7658 OpSize;
7622 (int_x86_aesni_aesimc VR128:$src1))]>;
76597623 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
76607624 (ins i128mem:$src1),
76617625 "aesimc\t{$src1, $dst|$dst, $src1}",
7662 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7663 OpSize;
7626 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>;
76647627
76657628 // AES Round Key Generation Assist
76667629 let Predicates = [HasAVX, HasAES] in {
76697632 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
76707633 [(set VR128:$dst,
76717634 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7672 OpSize, VEX;
7635 VEX;
76737636 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
76747637 (ins i128mem:$src1, i8imm:$src2),
76757638 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
76767639 [(set VR128:$dst,
76777640 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7678 OpSize, VEX;
7641 VEX;
76797642 }
76807643 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
76817644 (ins VR128:$src1, i8imm:$src2),
76827645 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
76837646 [(set VR128:$dst,
7684 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7685 OpSize;
7647 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>;
76867648 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
76877649 (ins i128mem:$src1, i8imm:$src2),
76887650 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
76897651 [(set VR128:$dst,
7690 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7691 OpSize;
7652 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>;
76927653
76937654 //===----------------------------------------------------------------------===//
76947655 // PCLMUL Instructions
77567717 (ins VR128:$src, i8imm:$len, i8imm:$idx),
77577718 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
77587719 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7759 imm:$idx))]>, TB, OpSize;
7720 imm:$idx))]>, PD;
77607721 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
77617722 (ins VR128:$src, VR128:$mask),
77627723 "extrq\t{$mask, $src|$src, $mask}",
77637724 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7764 VR128:$mask))]>, TB, OpSize;
7725 VR128:$mask))]>, PD;
77657726
77667727 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
77677728 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
81488109 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
81498110 "vcvtph2ps\t{$src, $dst|$dst, $src}",
81508111 [(set RC:$dst, (Int VR128:$src))]>,
8151 T8, OpSize, VEX;
8112 T8PD, VEX;
81528113 let neverHasSideEffects = 1, mayLoad = 1 in
81538114 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8154 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
8115 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX;
81558116 }
81568117
81578118 multiclass f16c_ps2ph {
81598120 (ins RC:$src1, i32i8imm:$src2),
81608121 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
81618122 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8162 TA, OpSize, VEX;
8123 TAPD, VEX;
81638124 let neverHasSideEffects = 1, mayStore = 1 in
81648125 def mr : Ii8<0x1D, MRMDestMem, (outs),
81658126 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
81668127 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8167 TA, OpSize, VEX;
8128 TAPD, VEX;
81688129 }
81698130
81708131 let Predicates = [HasF16C] in {
907907 defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W;
908908 defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD;
909909 defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W;
910 defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8, OpSize;
911 defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8, OpSize, VEX_W;
910 defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8PD;
911 defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8PD, VEX_W;
912912
913913 // Prefer RORX which is non-destructive and doesn't update EFLAGS.
914914 let AddedComplexity = 10 in {
541541 //===----------------------------------------------------------------------===//
542542 // INVPCID Instruction
543543 def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
544 "invpcid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
544 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
545545 Requires<[Not64BitMode]>;
546546 def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
547 "invpcid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
547 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
548548 Requires<[In64BitMode]>;
549549
550550 //===----------------------------------------------------------------------===//
1616
1717 // 66 0F 38 80
1818 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
19 "invept\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
19 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
2020 Requires<[Not64BitMode]>;
2121 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
22 "invept\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
22 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
2323 Requires<[In64BitMode]>;
2424 // 66 0F 38 81
2525 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
26 "invvpid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
26 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
2727 Requires<[Not64BitMode]>;
2828 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
29 "invvpid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
29 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
3030 Requires<[In64BitMode]>;
3131 // 0F 01 C1
3232 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
3333 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
34 "vmclear\t$vmcs", []>, OpSize, TB;
34 "vmclear\t$vmcs", []>, PD;
3535 // OF 01 D4
3636 def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB;
3737 // 0F 01 C2
7979 XD = 11, XS = 12,
8080 T8 = 13, P_TA = 14,
8181 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
82 XOP8 = 20, XOP9 = 21, XOPA = 22
82 XOP8 = 20, XOP9 = 21, XOPA = 22, PD = 23, T8PD = 24, TAPD = 25,
8383 };
8484 }
8585
253253
254254 Operands = &insn.Operands.OperandList;
255255
256 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
256 IsSSE = ((HasOpSizePrefix || Prefix == X86Local::PD ||
257 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
258 (Name.find("16") == Name.npos)) ||
257259 (Name.find("CRC32") != Name.npos);
258260 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
259261
308310 }
309311 // VEX_L & VEX_W
310312 if (HasVEX_LPrefix && HasVEX_WPrefix) {
311 if (HasOpSizePrefix)
313 if (HasOpSizePrefix || Prefix == X86Local::PD)
312314 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
313315 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
314316 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
319321 insnContext = EVEX_KB(IC_EVEX_L_W);
320322 } else if (HasVEX_LPrefix) {
321323 // VEX_L
322 if (HasOpSizePrefix)
324 if (HasOpSizePrefix || Prefix == X86Local::PD ||
325 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
323326 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
324327 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
325328 insnContext = EVEX_KB(IC_EVEX_L_XS);
331334 }
332335 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
333336 // EVEX_L2 & VEX_W
334 if (HasOpSizePrefix)
337 if (HasOpSizePrefix || Prefix == X86Local::PD ||
338 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
335339 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
336340 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
337341 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
342346 insnContext = EVEX_KB(IC_EVEX_L2_W);
343347 } else if (HasEVEX_L2Prefix) {
344348 // EVEX_L2
345 if (HasOpSizePrefix)
349 if (HasOpSizePrefix || Prefix == X86Local::PD ||
350 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
346351 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
347352 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
348 Prefix == X86Local::TAXD)
353 Prefix == X86Local::TAXD)
349354 insnContext = EVEX_KB(IC_EVEX_L2_XD);
350355 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
351356 insnContext = EVEX_KB(IC_EVEX_L2_XS);
354359 }
355360 else if (HasVEX_WPrefix) {
356361 // VEX_W
357 if (HasOpSizePrefix)
362 if (HasOpSizePrefix || Prefix == X86Local::PD ||
363 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
358364 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
359365 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
360366 insnContext = EVEX_KB(IC_EVEX_W_XS);
365371 insnContext = EVEX_KB(IC_EVEX_W);
366372 }
367373 // No L, no W
368 else if (HasOpSizePrefix)
374 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
375 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
369376 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
370377 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
371378 Prefix == X86Local::TAXD)
377384 /// eof EVEX
378385 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
379386 if (HasVEX_LPrefix && HasVEX_WPrefix) {
380 if (HasOpSizePrefix)
387 if (HasOpSizePrefix || Prefix == X86Local::PD ||
388 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
381389 insnContext = IC_VEX_L_W_OPSIZE;
382390 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
383391 insnContext = IC_VEX_L_W_XS;
386394 insnContext = IC_VEX_L_W_XD;
387395 else
388396 insnContext = IC_VEX_L_W;
389 } else if (HasOpSizePrefix && HasVEX_LPrefix)
397 } else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
398 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
399 HasVEX_LPrefix)
390400 insnContext = IC_VEX_L_OPSIZE;
391 else if (HasOpSizePrefix && HasVEX_WPrefix)
401 else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
402 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
403 HasVEX_WPrefix)
392404 insnContext = IC_VEX_W_OPSIZE;
393 else if (HasOpSizePrefix)
405 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
406 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
394407 insnContext = IC_VEX_OPSIZE;
395408 else if (HasVEX_LPrefix &&
396409 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
418431 else
419432 insnContext = IC_VEX;
420433 } else if (Is64Bit || HasREX_WPrefix) {
421 if (HasREX_WPrefix && HasOpSizePrefix)
434 if (HasREX_WPrefix && (HasOpSizePrefix || Prefix == X86Local::PD ||
435 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD))
422436 insnContext = IC_64BIT_REXW_OPSIZE;
423437 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
424438 Prefix == X86Local::T8XD ||
427441 else if (HasOpSizePrefix &&
428442 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
429443 insnContext = IC_64BIT_XS_OPSIZE;
430 else if (HasOpSizePrefix)
444 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
445 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
431446 insnContext = IC_64BIT_OPSIZE;
432447 else if (HasAdSizePrefix)
433448 insnContext = IC_64BIT_ADSIZE;
457472 insnContext = IC_XS_OPSIZE;
458473 else if (HasOpSizePrefix && HasAdSizePrefix)
459474 insnContext = IC_OPSIZE_ADSIZE;
460 else if (HasOpSizePrefix)
475 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
476 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
461477 insnContext = IC_OPSIZE;
462478 else if (HasAdSizePrefix)
463479 insnContext = IC_ADSIZE;
850866
851867 switch (Prefix) {
852868 default: llvm_unreachable("Invalid prefix!");
853 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
869 // Extended two-byte opcodes can start with 66 0f, f2 0f, f3 0f, or 0f
870 case X86Local::PD:
854871 case X86Local::XD:
855872 case X86Local::XS:
856873 case X86Local::TB:
896913 opcodeToSet = Opcode;
897914 break;
898915 case X86Local::T8:
916 case X86Local::T8PD:
899917 case X86Local::T8XD:
900918 case X86Local::T8XS:
901919 opcodeType = THREEBYTE_38;
939957 opcodeToSet = Opcode;
940958 break;
941959 case X86Local::P_TA:
960 case X86Local::TAPD:
942961 case X86Local::TAXD:
943962 opcodeType = THREEBYTE_3A;
944963 if (needsModRMForDecode(Form))